From: Sandipan Das <sandipan.das@amd.com>
To: Ingo Molnar <mingo@kernel.org>, Vince Weaver <vincent.weaver@maine.edu>
Cc: linux-kernel@vger.kernel.org, linux-tip-commits@vger.kernel.org,
Peter Zijlstra <peterz@infradead.org>,
linux-perf-users@vger.kernel.org, x86@kernel.org
Subject: Re: [tip: perf/urgent] perf/x86/amd/core: Fix Family 17h+ instruction cache events
Date: Wed, 21 May 2025 11:00:54 +0530 [thread overview]
Message-ID: <82853f34-cd5a-43d7-81de-8e40144503e1@amd.com> (raw)
In-Reply-To: <aCiI4lcWIe6GYW4_@gmail.com>
On 5/17/2025 6:32 PM, Ingo Molnar wrote:
>
> * Vince Weaver <vincent.weaver@maine.edu> wrote:
>
>> On Fri, 16 May 2025, tip-bot2 for Sandipan Das wrote:
>>
>>> The following commit has been merged into the perf/urgent branch of tip:
>>>
>>
>>> perf/x86/amd/core: Fix Family 17h+ instruction cache events
>>>
>>> PMCx080 and PMCx081 report incorrect IC accesses and misses respectively
>>> for all Family 17h and later processors. PMCx060 unit mask 0x10 replaces
>>> PMCx081 for counting IC misses but there is no suitable replacement for
>>> counting IC accesses.
>>
>> can you link to the errata document that describes this problem as well as
>> maybe give a rundown of how and why this breaks?
>
> I've delayed this patch until these details are cleared up.
>
Both of these events were removed from the Processor Programming Reference
starting with Zen 2. Errata is missing for Zen 1 but it is known that these
events are broken. A quick test like the following will show that PMCx081
undercounts IC misses compared to PMCx060 with unit mask 0x10.
$ perf stat -e "{cpu/event=0x81/,cpu/event=0x60,umask=0x10/}" ./ic-miss
Performance counter stats for './ic-miss':
2,105 cpu/event=0x81/u
30,826 cpu/event=0x60,umask=0x10/u
1.650143599 seconds time elapsed
1.646070000 seconds user
0.000998000 seconds sys
If its acceptable, I can send out a v2 with the details above.
prev parent reply other threads:[~2025-05-21 5:31 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-16 13:43 [tip: perf/urgent] perf/x86/amd/core: Fix Family 17h+ instruction cache events tip-bot2 for Sandipan Das
2025-05-16 14:18 ` Vince Weaver
2025-05-17 13:02 ` Ingo Molnar
2025-05-21 5:30 ` Sandipan Das [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=82853f34-cd5a-43d7-81de-8e40144503e1@amd.com \
--to=sandipan.das@amd.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-perf-users@vger.kernel.org \
--cc=linux-tip-commits@vger.kernel.org \
--cc=mingo@kernel.org \
--cc=peterz@infradead.org \
--cc=vincent.weaver@maine.edu \
--cc=x86@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox