From: Vince Weaver <vincent.weaver@maine.edu>
To: linux-kernel@vger.kernel.org
Cc: linux-tip-commits@vger.kernel.org,
Sandipan Das <sandipan.das@amd.com>,
Ingo Molnar <mingo@kernel.org>,
Peter Zijlstra <peterz@infradead.org>,
linux-perf-users@vger.kernel.org, x86@kernel.org
Subject: Re: [tip: perf/urgent] perf/x86/amd/core: Fix Family 17h+ instruction cache events
Date: Fri, 16 May 2025 10:18:07 -0400 (EDT) [thread overview]
Message-ID: <c409c331-da7d-7424-e0db-a4c61ea423ca@maine.edu> (raw)
In-Reply-To: <174740303900.406.5499797802401271693.tip-bot2@tip-bot2>
On Fri, 16 May 2025, tip-bot2 for Sandipan Das wrote:
> The following commit has been merged into the perf/urgent branch of tip:
>
> perf/x86/amd/core: Fix Family 17h+ instruction cache events
>
> PMCx080 and PMCx081 report incorrect IC accesses and misses respectively
> for all Family 17h and later processors. PMCx060 unit mask 0x10 replaces
> PMCx081 for counting IC misses but there is no suitable replacement for
> counting IC accesses.
can you link to the errata document that describes this problem as well as
maybe give a rundown of how and why this breaks?
Vince Weaver
vincent.weaver@maine.edu
next prev parent reply other threads:[~2025-05-16 14:18 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-16 13:43 [tip: perf/urgent] perf/x86/amd/core: Fix Family 17h+ instruction cache events tip-bot2 for Sandipan Das
2025-05-16 14:18 ` Vince Weaver [this message]
2025-05-17 13:02 ` Ingo Molnar
2025-05-21 5:30 ` Sandipan Das
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