Re: [PATCH v4 0/4] arm64: cross-CPU NMI via SDEI

[Marc Zyngier <maz@kernel.org>]

On Fri, 19 Jun 2026 15:00:26 +0100,
Catalin Marinas <catalin.marinas@arm.com> wrote:
> 
> Hi Kiryl,
> 
> On Wed, Jun 17, 2026 at 08:20:01PM +0100, Kiryl Shutsemau wrote:
> >   - GICv3 pseudo-NMI (interrupt priority masking). Its cost is on the
> >     interrupt mask/unmask hot path: local_irq_enable() becomes an
> >     ICC_PMR_EL1 write plus a synchronising barrier, and exception
> >     entry/exit save and restore the PMR, paid on every CPU whether or not
> >     an NMI is ever delivered. In our measurements, enabling pseudo-NMI
> >     costs up to ~5% on real workloads, and ~66% on a syscall-in-a-loop
> >     microbenchmark. A fleet-wide ~5% regression is not acceptable, so
> >     these systems run with pseudo-NMI disabled.
> 
> Does your firmware set ICC_CTLR_EL1.PMHE? I'd be curious to see the
> numbers if the DSB was omitted on the enable path.

I certainly don't observe this sort of overhead on the HW I have
access to, and would like to understand where this is coming from with
actual profiling data.

	M.

-- 
Without deviation from the norm, progress is not possible.