Re: [PATCH 0/4] rawnand: pl35x: Implement mixed ECC

[Miquel Raynal <miquel.raynal@bootlin.com>]

Hello Bastien,

On 23/07/2026 at 15:41:00 +02, Bastien Curutchet <bastien.curutchet@bootlin.com> wrote:

> Hi all,
>
> This series addresses the PL353 errata "SLC ECC misses single error to
> bit0 byte0 and fails to detect some double error cases" (see 721059 in
> [1]).
>
> The ECC HW engine is known to be broken on this chip, it fails to detect
> some bitflips on reads.
>
> This series implements a mixed-ECC where the HW engine is used on writes
> and reads are done by software. To make it work, the software ECC has to
> use the same layout for the ECC bits than the HW engine. Patches 1 & 2
> add the PL35x ordering to the available orderings for soft ECC. Patches
> 3 & 4 make use of this ordering to implement the mixed-ECC for the PL353
> controller.
>
> Note that this series is based on top of nand/next.
>
> [1]: https://developer.arm.com/documentation/rlnc000227/a
>
> Signed-off-by: Bastien Curutchet <bastien.curutchet@bootlin.com>
> ---

There are several interesting Sashiko findings for this series, can you
please have a look?

Thanks!
Miquèl