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From: Thomas Gleixner <tglx@linutronix.de>
To: Balbir Singh <sblbir@amazon.com>, linux-kernel@vger.kernel.org
Cc: jpoimboe@redhat.com, tony.luck@intel.com, keescook@chromium.org,
	benh@kernel.crashing.org, x86@kernel.org, dave.hansen@intel.com,
	Balbir Singh <sblbir@amazon.com>
Subject: Re: [PATCH v3 3/5] arch/x86/mm: Refactor cond_ibpb() to support other use cases
Date: Fri, 17 Apr 2020 15:07:31 +0200	[thread overview]
Message-ID: <87sgh2l0q4.fsf@nanos.tec.linutronix.de> (raw)
In-Reply-To: <20200408090229.16467-4-sblbir@amazon.com>

Balbir Singh <sblbir@amazon.com> writes:
>  
>  /*
> - * Use bit 0 to mangle the TIF_SPEC_IB state into the mm pointer which is
> - * stored in cpu_tlb_state.last_user_mm_ibpb.
> + * Bits to mangle the TIF_SPEC_IB state into the mm pointer which is
> + * stored in cpu_tlb_state.last_user_mm_spec.
>   */
>  #define LAST_USER_MM_IBPB	0x1UL
> +#define LAST_USER_MM_SPEC_MASK	(LAST_USER_MM_IBPB)
>  
>  	/* Reinitialize tlbstate. */
> -	this_cpu_write(cpu_tlbstate.last_user_mm_ibpb, LAST_USER_MM_IBPB);
> +	this_cpu_write(cpu_tlbstate.last_user_mm_spec, LAST_USER_MM_IBPB);

Shouldn't that be LAST_USER_MM_MASK?

Thanks,

        tglx

  reply	other threads:[~2020-04-17 13:07 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-04-08  9:02 [PATCH v3 0/5] Optionally flush L1D on context switch Balbir Singh
2020-04-08  9:02 ` [PATCH v3 1/5] arch/x86/kvm: Refactor l1d flush lifecycle management Balbir Singh
2020-04-17 12:57   ` Thomas Gleixner
2020-04-17 22:34     ` Singh, Balbir
2020-04-08  9:02 ` [PATCH v3 2/5] arch/x86: Refactor tlbflush and l1d flush Balbir Singh
2020-04-17 13:03   ` Thomas Gleixner
2020-04-17 22:58     ` Singh, Balbir
2020-04-08  9:02 ` [PATCH v3 3/5] arch/x86/mm: Refactor cond_ibpb() to support other use cases Balbir Singh
2020-04-17 13:07   ` Thomas Gleixner [this message]
2020-04-17 23:02     ` Singh, Balbir
2020-04-18  9:59       ` Thomas Gleixner
2020-04-21  3:46         ` Singh, Balbir
2020-04-21  9:02           ` Thomas Gleixner
2020-04-08  9:02 ` [PATCH v3 4/5] arch/x86: Optionally flush L1D on context switch Balbir Singh
2020-04-17 14:41   ` Thomas Gleixner
2020-04-18  1:30     ` Singh, Balbir
2020-04-18 10:17       ` Thomas Gleixner
2020-04-20  0:24         ` Singh, Balbir
2020-04-08  9:02 ` [PATCH v3 5/5] arch/x86: Add L1D flushing Documentation Balbir Singh

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