From: Alexander Shishkin <alexander.shishkin@linux.intel.com>
To: Peter Zijlstra <peterz@infradead.org>
Cc: Ingo Molnar <mingo@redhat.com>,
linux-kernel@vger.kernel.org, adrian.hunter@intel.com,
x86@kernel.org, hpa@zytor.com, acme@infradead.org
Subject: Re: [PATCH 1/3] perf/x86/intel/pt: Add new timing packet enables
Date: Thu, 30 Jul 2015 14:57:17 +0300 [thread overview]
Message-ID: <87vbd1kgde.fsf@ashishki-desk.ger.corp.intel.com> (raw)
In-Reply-To: <20150730104046.GV19282@twins.programming.kicks-ass.net>
Peter Zijlstra <peterz@infradead.org> writes:
> On Fri, Jul 17, 2015 at 04:34:08PM +0300, Alexander Shishkin wrote:
>> +#define PT_CONFIG_MASK (RTIT_CTL_TSC_EN | \
>> + RTIT_CTL_DISRETC | \
>> + RTIT_CTL_CYCLEACC | \
>> + RTIT_CTL_MTC_EN | \
>> + RTIT_CTL_MTC_RANGE | \
>> + RTIT_CTL_CYC_THRESH | \
>> + RTIT_CTL_PSB_FREQ)
>>
>
> #define RTIT_CTL_CYC (RTIT_CTL_CYCLEACC | \
> RTIT_CTL_CYC_THRESH | \
> RTIT_CTL_PSB_FREQ)
PSB_FREQ is not, strictly speaking, related to cycle accurate mode. Both
adjustable psb frequency and cycle accurate mode settings are enumerated
with the same CPUID bit, but they really do different things unrelated
to one another.
>> + if (config & (RTIT_CTL_MTC_EN | RTIT_CTL_MTC_RANGE)) {
>
> if (config & RTIT_CTL_MTC) {
>
> Would that make sense?
To me either way is fine. Want me to respin it?
Regards,
--
Alex
next prev parent reply other threads:[~2015-07-30 11:57 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-07-17 13:34 [PATCH 0/3] perf/x86/intel/pt: Add new packet enables Alexander Shishkin
2015-07-17 13:34 ` [PATCH 1/3] perf/x86/intel/pt: Add new timing " Alexander Shishkin
2015-07-30 10:40 ` Peter Zijlstra
2015-07-30 11:57 ` Alexander Shishkin [this message]
2015-07-30 12:14 ` Peter Zijlstra
2015-07-30 13:15 ` [PATCH v1] " Alexander Shishkin
2015-08-04 8:55 ` [tip:perf/core] " tip-bot for Alexander Shishkin
2015-07-17 13:34 ` [PATCH 2/3] perf/x86/intel/pt: Add an option to not force PSB+ on every schedule-in Alexander Shishkin
2015-07-30 10:43 ` Peter Zijlstra
2015-07-30 11:53 ` Alexander Shishkin
2015-07-30 12:13 ` Peter Zijlstra
2015-07-30 12:49 ` Alexander Shishkin
2015-07-30 13:36 ` Alexander Shishkin
2015-07-30 13:48 ` [PATCH v1] perf/x86/intel/pt: Do not force sync packets " Alexander Shishkin
2015-07-30 15:24 ` Alexander Shishkin
2015-08-04 8:55 ` [tip:perf/core] " tip-bot for Alexander Shishkin
2015-07-31 11:47 ` [PATCH v2] " Alexander Shishkin
2015-07-17 13:34 ` [PATCH 3/3] perf/x86/intel/bts: Set itrace_started in pmu::start to match the new logic Alexander Shishkin
2015-09-08 12:02 ` Alexander Shishkin
2015-09-08 12:28 ` Peter Zijlstra
2015-09-13 10:56 ` [tip:perf/core] perf/x86/intel/bts: Set event-> hw.itrace_started " tip-bot for Alexander Shishkin
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