Re: [PATCH v11 05/31] cxl/mem: Expose dynamic ram 1 partition in sysfs

[Dave Jiang <dave.jiang@intel.com>]

On 6/25/26 4:04 AM, Anisa Su wrote:
> From: Ira Weiny <iweiny@kernel.org>
> 
> To properly configure CXL regions user space will need to know the
> details of the dynamic ram partition.
> 
> Expose the first dynamic ram partition through sysfs.
> 
> Signed-off-by: Ira Weiny <iweiny@kernel.org>
> Signed-off-by: Anisa Su <anisa.su@samsung.com>
> Reviewed-by: Dave Jiang <dave.jiang@intel.com>

Just a spelling error below

> 
> ---
> Changes:
> 1. Documentation: bump kernel version to 7.3 and date to June 2026
> 2. Pick up Dave's reviewed-by tag
> 3. Rename dynamic_ram_a to dynamic_ram_1
> ---
>  Documentation/ABI/testing/sysfs-bus-cxl | 24 +++++++++++
>  drivers/cxl/core/memdev.c               | 57 +++++++++++++++++++++++++
>  2 files changed, 81 insertions(+)
> 
> diff --git a/Documentation/ABI/testing/sysfs-bus-cxl b/Documentation/ABI/testing/sysfs-bus-cxl
> index 16a9b3d2e2c0..435495de409c 100644
> --- a/Documentation/ABI/testing/sysfs-bus-cxl
> +++ b/Documentation/ABI/testing/sysfs-bus-cxl
> @@ -89,6 +89,30 @@ Description:
>  		and there are platform specific performance related
>  		side-effects that may result. First class-id is displayed.
>  
> +What:		/sys/bus/cxl/devices/memX/dynamic_ram_1/size
> +Date:		June, 2026
> +KernelVersion:	v7.3
> +Contact:	linux-cxl@vger.kernel.org
> +Description:
> +		(RO) The first Dynamic RAM partition capacity as bytes.
> +
> +
> +What:		/sys/bus/cxl/devices/memX/dynamic_ram_1/qos_class
> +Date:		June, 2026
> +KernelVersion:	v7.3
> +Contact:	linux-cxl@vger.kernel.org
> +Description:
> +		(RO) For CXL host platforms that support "QoS Telemmetry"

Telemetry

DJ

> +		this attribute conveys a comma delimited list of platform
> +		specific cookies that identifies a QoS performance class
> +		for the partition of the CXL mem device. These
> +		class-ids can be compared against a similar "qos_class"
> +		published for a root decoder. While it is not required
> +		that the endpoints map their local memory-class to a
> +		matching platform class, mismatches are not recommended
> +		and there are platform specific performance related
> +		side-effects that may result. First class-id is displayed.
> +
>  
>  What:		/sys/bus/cxl/devices/memX/serial
>  Date:		January, 2022
> diff --git a/drivers/cxl/core/memdev.c b/drivers/cxl/core/memdev.c
> index 71602820f896..20417db933aa 100644
> --- a/drivers/cxl/core/memdev.c
> +++ b/drivers/cxl/core/memdev.c
> @@ -101,6 +101,19 @@ static ssize_t pmem_size_show(struct device *dev, struct device_attribute *attr,
>  static struct device_attribute dev_attr_pmem_size =
>  	__ATTR(size, 0444, pmem_size_show, NULL);
>  
> +static ssize_t dynamic_ram_1_size_show(struct device *dev, struct device_attribute *attr,
> +			      char *buf)
> +{
> +	struct cxl_memdev *cxlmd = to_cxl_memdev(dev);
> +	struct cxl_dev_state *cxlds = cxlmd->cxlds;
> +	unsigned long long len = cxl_part_size(cxlds, CXL_PARTMODE_DYNAMIC_RAM_1);
> +
> +	return sysfs_emit(buf, "%#llx\n", len);
> +}
> +
> +static struct device_attribute dev_attr_dynamic_ram_1_size =
> +	__ATTR(size, 0444, dynamic_ram_1_size_show, NULL);
> +
>  static ssize_t serial_show(struct device *dev, struct device_attribute *attr,
>  			   char *buf)
>  {
> @@ -443,6 +456,25 @@ static struct attribute *cxl_memdev_pmem_attributes[] = {
>  	NULL,
>  };
>  
> +static ssize_t dynamic_ram_1_qos_class_show(struct device *dev,
> +				   struct device_attribute *attr, char *buf)
> +{
> +	struct cxl_memdev *cxlmd = to_cxl_memdev(dev);
> +	struct cxl_dev_state *cxlds = cxlmd->cxlds;
> +
> +	return sysfs_emit(buf, "%d\n",
> +			  part_perf(cxlds, CXL_PARTMODE_DYNAMIC_RAM_1)->qos_class);
> +}
> +
> +static struct device_attribute dev_attr_dynamic_ram_1_qos_class =
> +	__ATTR(qos_class, 0444, dynamic_ram_1_qos_class_show, NULL);
> +
> +static struct attribute *cxl_memdev_dynamic_ram_1_attributes[] = {
> +	&dev_attr_dynamic_ram_1_size.attr,
> +	&dev_attr_dynamic_ram_1_qos_class.attr,
> +	NULL,
> +};
> +
>  static ssize_t ram_qos_class_show(struct device *dev,
>  				  struct device_attribute *attr, char *buf)
>  {
> @@ -519,6 +551,29 @@ static struct attribute_group cxl_memdev_pmem_attribute_group = {
>  	.is_visible = cxl_pmem_visible,
>  };
>  
> +static umode_t cxl_dynamic_ram_1_visible(struct kobject *kobj, struct attribute *a, int n)
> +{
> +	struct device *dev = kobj_to_dev(kobj);
> +	struct cxl_memdev *cxlmd = to_cxl_memdev(dev);
> +	struct cxl_dpa_perf *perf = part_perf(cxlmd->cxlds, CXL_PARTMODE_DYNAMIC_RAM_1);
> +
> +	if (a == &dev_attr_dynamic_ram_1_qos_class.attr &&
> +	    (!perf || perf->qos_class == CXL_QOS_CLASS_INVALID))
> +		return 0;
> +
> +	if (a == &dev_attr_dynamic_ram_1_size.attr &&
> +	    (!cxl_part_size(cxlmd->cxlds, CXL_PARTMODE_DYNAMIC_RAM_1)))
> +		return 0;
> +
> +	return a->mode;
> +}
> +
> +static struct attribute_group cxl_memdev_dynamic_ram_1_attribute_group = {
> +	.name = "dynamic_ram_1",
> +	.attrs = cxl_memdev_dynamic_ram_1_attributes,
> +	.is_visible = cxl_dynamic_ram_1_visible,
> +};
> +
>  static umode_t cxl_memdev_security_visible(struct kobject *kobj,
>  					   struct attribute *a, int n)
>  {
> @@ -547,6 +602,7 @@ static const struct attribute_group *cxl_memdev_attribute_groups[] = {
>  	&cxl_memdev_attribute_group,
>  	&cxl_memdev_ram_attribute_group,
>  	&cxl_memdev_pmem_attribute_group,
> +	&cxl_memdev_dynamic_ram_1_attribute_group,
>  	&cxl_memdev_security_attribute_group,
>  	NULL,
>  };
> @@ -555,6 +611,7 @@ void cxl_memdev_update_perf(struct cxl_memdev *cxlmd)
>  {
>  	sysfs_update_group(&cxlmd->dev.kobj, &cxl_memdev_ram_attribute_group);
>  	sysfs_update_group(&cxlmd->dev.kobj, &cxl_memdev_pmem_attribute_group);
> +	sysfs_update_group(&cxlmd->dev.kobj, &cxl_memdev_dynamic_ram_1_attribute_group);
>  }
>  EXPORT_SYMBOL_NS_GPL(cxl_memdev_update_perf, "CXL");
>