* [PATCH 1/8] perf vendor events: Update events for CascadelakeX
@ 2022-03-17 18:28 Ian Rogers
2022-03-17 18:28 ` [PATCH 2/8] perf vendor events: Update events for Elkhartlake Ian Rogers
` (8 more replies)
0 siblings, 9 replies; 18+ messages in thread
From: Ian Rogers @ 2022-03-17 18:28 UTC (permalink / raw)
To: Kan Liang, Zhengjun Xing, Peter Zijlstra, Ingo Molnar,
Arnaldo Carvalho de Melo, Mark Rutland, Alexander Shishkin,
Jiri Olsa, Namhyung Kim, Maxime Coquelin, Alexandre Torgue,
Andi Kleen, James Clark, John Garry, linux-kernel,
linux-perf-users
Cc: Stephane Eranian, Ian Rogers
The change:
https://github.com/intel/event-converter-for-linux-perf/commit/fc680410402e394eed6a1ebd909c9f649d3ed3ef
moved certain "other" type of events in to the cache topic. Update the
perf json files for this change.
Tested:
```
...
6: Parse event definition strings : Ok
7: Simple expression parser : Ok
8: PERF_RECORD_* events & perf_sample fields : Ok
9: Parse perf pmu format : Ok
10: PMU events :
10.1: PMU event table sanity : Ok
10.2: PMU event map aliases : Ok
10.3: Parsing of PMU event table metrics : Ok
10.4: Parsing of PMU event table metrics with fake PMUs : Ok
...
68: Parse and process metrics : Ok
...
89: perf all metricgroups test : Ok
90: perf all metrics test : FAILED!
91: perf all PMU test : Ok
...
```
Test 90 failed due to MEM_PMM_Read_Latency as the test machine
lacks optane memory, and the divide by 0 causes the metric not to
print - which is intended behavior.
Signed-off-by: Ian Rogers <irogers@google.com>
---
.../arch/x86/cascadelakex/cache.json | 6588 +++++++++++++++
.../arch/x86/cascadelakex/other.json | 7446 +----------------
2 files changed, 7017 insertions(+), 7017 deletions(-)
diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/cache.json b/tools/perf/pmu-events/arch/x86/cascadelakex/cache.json
index 732bf51e35af..aa906a7fa520 100644
--- a/tools/perf/pmu-events/arch/x86/cascadelakex/cache.json
+++ b/tools/perf/pmu-events/arch/x86/cascadelakex/cache.json
@@ -602,6 +602,6558 @@
"SampleAfterValue": "100003",
"UMask": "0x80"
},
+ {
+ "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3F803C0491",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x10003C0491",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x8003C0491",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x4003C0491",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x1003C0491",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x8007C0491",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_MISS OCR.ALL_DATA_RD.L3_HIT.SNOOP_MISS",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x2003C0491",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_NONE OCR.ALL_DATA_RD.L3_HIT.SNOOP_NONE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_NONE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x803C0491",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT_E.ANY_SNOOP",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.ANY_SNOOP",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3F80080491",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT_E.HITM_OTHER_CORE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.HITM_OTHER_CORE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x1000080491",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x800080491",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x400080491",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x100080491",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_MISS",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x200080491",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_NONE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_NONE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x80080491",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT_F.ANY_SNOOP",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.ANY_SNOOP",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3F80200491",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT_F.HITM_OTHER_CORE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.HITM_OTHER_CORE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x1000200491",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x800200491",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x400200491",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x100200491",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_MISS",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x200200491",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_NONE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_NONE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x80200491",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT_M.ANY_SNOOP",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.ANY_SNOOP",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3F80040491",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT_M.HITM_OTHER_CORE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.HITM_OTHER_CORE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x1000040491",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x800040491",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x400040491",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x100040491",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_MISS",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x200040491",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_NONE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_NONE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x80040491",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT_S.ANY_SNOOP",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.ANY_SNOOP",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3F80100491",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT_S.HITM_OTHER_CORE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.HITM_OTHER_CORE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x1000100491",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x800100491",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x400100491",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x100100491",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_MISS",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x200100491",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_NONE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_NONE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x80100491",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3F803C0490",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x10003C0490",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x8003C0490",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x4003C0490",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x1003C0490",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x8007C0490",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x2003C0490",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x803C0490",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT_E.ANY_SNOOP",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.ANY_SNOOP",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3F80080490",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT_E.HITM_OTHER_CORE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HITM_OTHER_CORE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x1000080490",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x800080490",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x400080490",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x100080490",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_MISS",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x200080490",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_NONE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_NONE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x80080490",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT_F.ANY_SNOOP",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.ANY_SNOOP",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3F80200490",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT_F.HITM_OTHER_CORE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HITM_OTHER_CORE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x1000200490",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x800200490",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x400200490",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x100200490",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_MISS",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x200200490",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_NONE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_NONE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x80200490",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT_M.ANY_SNOOP",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.ANY_SNOOP",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3F80040490",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT_M.HITM_OTHER_CORE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HITM_OTHER_CORE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x1000040490",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x800040490",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x400040490",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x100040490",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_MISS",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x200040490",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_NONE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_NONE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x80040490",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT_S.ANY_SNOOP",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.ANY_SNOOP",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3F80100490",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT_S.HITM_OTHER_CORE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HITM_OTHER_CORE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x1000100490",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x800100490",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x400100490",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x100100490",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_MISS",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x200100490",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_NONE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_NONE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x80100490",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3F803C0120",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x10003C0120",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x8003C0120",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x4003C0120",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x1003C0120",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x8007C0120",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_MISS OCR.ALL_PF_RFO.L3_HIT.SNOOP_MISS",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x2003C0120",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_NONE OCR.ALL_PF_RFO.L3_HIT.SNOOP_NONE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_NONE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x803C0120",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT_E.ANY_SNOOP",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.ANY_SNOOP",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3F80080120",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT_E.HITM_OTHER_CORE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.HITM_OTHER_CORE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x1000080120",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x800080120",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x400080120",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT_E.NO_SNOOP_NEEDED",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.NO_SNOOP_NEEDED",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x100080120",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_MISS",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x200080120",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_NONE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_NONE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x80080120",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT_F.ANY_SNOOP",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.ANY_SNOOP",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3F80200120",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT_F.HITM_OTHER_CORE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.HITM_OTHER_CORE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x1000200120",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x800200120",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x400200120",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT_F.NO_SNOOP_NEEDED",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.NO_SNOOP_NEEDED",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x100200120",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_MISS",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x200200120",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_NONE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_NONE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x80200120",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT_M.ANY_SNOOP",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.ANY_SNOOP",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3F80040120",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT_M.HITM_OTHER_CORE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.HITM_OTHER_CORE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x1000040120",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x800040120",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x400040120",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT_M.NO_SNOOP_NEEDED",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.NO_SNOOP_NEEDED",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x100040120",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_MISS",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x200040120",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_NONE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_NONE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x80040120",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT_S.ANY_SNOOP",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.ANY_SNOOP",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3F80100120",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT_S.HITM_OTHER_CORE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.HITM_OTHER_CORE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x1000100120",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x800100120",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x400100120",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT_S.NO_SNOOP_NEEDED",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.NO_SNOOP_NEEDED",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x100100120",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_MISS",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x200100120",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_NONE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_NONE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x80100120",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_READS.L3_HIT.ANY_SNOOP OCR.ALL_READS.L3_HIT.ANY_SNOOP OCR.ALL_READS.L3_HIT.ANY_SNOOP",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_READS.L3_HIT.ANY_SNOOP",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3F803C07F7",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x10003C07F7",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x8003C07F7",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x4003C07F7",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x1003C07F7",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_READS.L3_HIT.SNOOP_HIT_WITH_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_READS.L3_HIT.SNOOP_HIT_WITH_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x8007C07F7",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_READS.L3_HIT.SNOOP_MISS OCR.ALL_READS.L3_HIT.SNOOP_MISS",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_READS.L3_HIT.SNOOP_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x2003C07F7",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_READS.L3_HIT.SNOOP_NONE OCR.ALL_READS.L3_HIT.SNOOP_NONE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_READS.L3_HIT.SNOOP_NONE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x803C07F7",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_READS.L3_HIT_E.ANY_SNOOP OCR.ALL_READS.L3_HIT_E.ANY_SNOOP",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_READS.L3_HIT_E.ANY_SNOOP",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3F800807F7",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_READS.L3_HIT_E.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT_E.HITM_OTHER_CORE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_READS.L3_HIT_E.HITM_OTHER_CORE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x10000807F7",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x8000807F7",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x4000807F7",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_READS.L3_HIT_E.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT_E.NO_SNOOP_NEEDED",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_READS.L3_HIT_E.NO_SNOOP_NEEDED",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x1000807F7",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_READS.L3_HIT_E.SNOOP_MISS",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_READS.L3_HIT_E.SNOOP_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x2000807F7",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_READS.L3_HIT_E.SNOOP_NONE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_READS.L3_HIT_E.SNOOP_NONE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x800807F7",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_READS.L3_HIT_F.ANY_SNOOP OCR.ALL_READS.L3_HIT_F.ANY_SNOOP",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_READS.L3_HIT_F.ANY_SNOOP",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3F802007F7",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_READS.L3_HIT_F.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT_F.HITM_OTHER_CORE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_READS.L3_HIT_F.HITM_OTHER_CORE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x10002007F7",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x8002007F7",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x4002007F7",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_READS.L3_HIT_F.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT_F.NO_SNOOP_NEEDED",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_READS.L3_HIT_F.NO_SNOOP_NEEDED",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x1002007F7",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_READS.L3_HIT_F.SNOOP_MISS",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_READS.L3_HIT_F.SNOOP_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x2002007F7",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_READS.L3_HIT_F.SNOOP_NONE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_READS.L3_HIT_F.SNOOP_NONE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x802007F7",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_READS.L3_HIT_M.ANY_SNOOP OCR.ALL_READS.L3_HIT_M.ANY_SNOOP",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_READS.L3_HIT_M.ANY_SNOOP",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3F800407F7",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_READS.L3_HIT_M.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT_M.HITM_OTHER_CORE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_READS.L3_HIT_M.HITM_OTHER_CORE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x10000407F7",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x8000407F7",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x4000407F7",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_READS.L3_HIT_M.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT_M.NO_SNOOP_NEEDED",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_READS.L3_HIT_M.NO_SNOOP_NEEDED",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x1000407F7",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_READS.L3_HIT_M.SNOOP_MISS",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_READS.L3_HIT_M.SNOOP_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x2000407F7",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_READS.L3_HIT_M.SNOOP_NONE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_READS.L3_HIT_M.SNOOP_NONE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x800407F7",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_READS.L3_HIT_S.ANY_SNOOP OCR.ALL_READS.L3_HIT_S.ANY_SNOOP",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_READS.L3_HIT_S.ANY_SNOOP",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3F801007F7",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_READS.L3_HIT_S.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT_S.HITM_OTHER_CORE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_READS.L3_HIT_S.HITM_OTHER_CORE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x10001007F7",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x8001007F7",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x4001007F7",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_READS.L3_HIT_S.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT_S.NO_SNOOP_NEEDED",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_READS.L3_HIT_S.NO_SNOOP_NEEDED",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x1001007F7",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_READS.L3_HIT_S.SNOOP_MISS",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_READS.L3_HIT_S.SNOOP_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x2001007F7",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_READS.L3_HIT_S.SNOOP_NONE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_READS.L3_HIT_S.SNOOP_NONE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x801007F7",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_RFO.L3_HIT.ANY_SNOOP OCR.ALL_RFO.L3_HIT.ANY_SNOOP OCR.ALL_RFO.L3_HIT.ANY_SNOOP",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_RFO.L3_HIT.ANY_SNOOP",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3F803C0122",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x10003C0122",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x8003C0122",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x4003C0122",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x1003C0122",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x8007C0122",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_RFO.L3_HIT.SNOOP_MISS OCR.ALL_RFO.L3_HIT.SNOOP_MISS",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_RFO.L3_HIT.SNOOP_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x2003C0122",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_RFO.L3_HIT.SNOOP_NONE OCR.ALL_RFO.L3_HIT.SNOOP_NONE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_RFO.L3_HIT.SNOOP_NONE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x803C0122",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.ANY_SNOOP OCR.ALL_RFO.L3_HIT_E.ANY_SNOOP",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_RFO.L3_HIT_E.ANY_SNOOP",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3F80080122",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT_E.HITM_OTHER_CORE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_RFO.L3_HIT_E.HITM_OTHER_CORE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x1000080122",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x800080122",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x400080122",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT_E.NO_SNOOP_NEEDED",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_RFO.L3_HIT_E.NO_SNOOP_NEEDED",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x100080122",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.SNOOP_MISS",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_RFO.L3_HIT_E.SNOOP_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x200080122",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.SNOOP_NONE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_RFO.L3_HIT_E.SNOOP_NONE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x80080122",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.ANY_SNOOP OCR.ALL_RFO.L3_HIT_F.ANY_SNOOP",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_RFO.L3_HIT_F.ANY_SNOOP",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3F80200122",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT_F.HITM_OTHER_CORE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_RFO.L3_HIT_F.HITM_OTHER_CORE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x1000200122",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x800200122",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x400200122",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT_F.NO_SNOOP_NEEDED",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_RFO.L3_HIT_F.NO_SNOOP_NEEDED",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x100200122",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.SNOOP_MISS",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_RFO.L3_HIT_F.SNOOP_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x200200122",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.SNOOP_NONE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_RFO.L3_HIT_F.SNOOP_NONE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x80200122",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.ANY_SNOOP OCR.ALL_RFO.L3_HIT_M.ANY_SNOOP",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_RFO.L3_HIT_M.ANY_SNOOP",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3F80040122",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT_M.HITM_OTHER_CORE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_RFO.L3_HIT_M.HITM_OTHER_CORE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x1000040122",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x800040122",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x400040122",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT_M.NO_SNOOP_NEEDED",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_RFO.L3_HIT_M.NO_SNOOP_NEEDED",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x100040122",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.SNOOP_MISS",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_RFO.L3_HIT_M.SNOOP_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x200040122",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.SNOOP_NONE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_RFO.L3_HIT_M.SNOOP_NONE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x80040122",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.ANY_SNOOP OCR.ALL_RFO.L3_HIT_S.ANY_SNOOP",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_RFO.L3_HIT_S.ANY_SNOOP",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3F80100122",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT_S.HITM_OTHER_CORE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_RFO.L3_HIT_S.HITM_OTHER_CORE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x1000100122",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x800100122",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x400100122",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT_S.NO_SNOOP_NEEDED",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_RFO.L3_HIT_S.NO_SNOOP_NEEDED",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x100100122",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.SNOOP_MISS",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_RFO.L3_HIT_S.SNOOP_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x200100122",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.SNOOP_NONE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.ALL_RFO.L3_HIT_S.SNOOP_NONE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x80100122",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP OCR.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3F803C0004",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE OCR.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x10003C0004",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x8003C0004",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x4003C0004",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDED OCR.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDED",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDED",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x1003C0004",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all demand code reads",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x8007C0004",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x2003C0004",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NONE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NONE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x803C0004",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_E.ANY_SNOOP",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.ANY_SNOOP",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3F80080004",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_E.HITM_OTHER_CORE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.HITM_OTHER_CORE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x1000080004",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x800080004",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x400080004",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_E.NO_SNOOP_NEEDED",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.NO_SNOOP_NEEDED",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x100080004",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all demand code reads",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.SNOOP_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x200080004",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all demand code reads",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NONE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x80080004",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_F.ANY_SNOOP",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.ANY_SNOOP",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3F80200004",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_F.HITM_OTHER_CORE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.HITM_OTHER_CORE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x1000200004",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x800200004",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x400200004",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_F.NO_SNOOP_NEEDED",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.NO_SNOOP_NEEDED",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x100200004",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all demand code reads",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.SNOOP_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x200200004",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all demand code reads",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.SNOOP_NONE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x80200004",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_M.ANY_SNOOP",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.ANY_SNOOP",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3F80040004",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_M.HITM_OTHER_CORE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.HITM_OTHER_CORE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x1000040004",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x800040004",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x400040004",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_M.NO_SNOOP_NEEDED",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.NO_SNOOP_NEEDED",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x100040004",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all demand code reads",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.SNOOP_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x200040004",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all demand code reads",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NONE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x80040004",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_S.ANY_SNOOP",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.ANY_SNOOP",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3F80100004",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_S.HITM_OTHER_CORE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.HITM_OTHER_CORE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x1000100004",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x800100004",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x400100004",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_S.NO_SNOOP_NEEDED",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.NO_SNOOP_NEEDED",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x100100004",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all demand code reads",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.SNOOP_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x200100004",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all demand code reads",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NONE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x80100004",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP OCR.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3F803C0001",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x10003C0001",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x8003C0001",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x4003C0001",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x1003C0001",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts demand data reads",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x8007C0001",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x2003C0001",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NONE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NONE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x803C0001",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_E.ANY_SNOOP",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.ANY_SNOOP",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3F80080001",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_E.HITM_OTHER_CORE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.HITM_OTHER_CORE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x1000080001",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x800080001",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x400080001",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x100080001",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts demand data reads",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.SNOOP_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x200080001",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts demand data reads",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NONE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x80080001",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_F.ANY_SNOOP",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.ANY_SNOOP",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3F80200001",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_F.HITM_OTHER_CORE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.HITM_OTHER_CORE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x1000200001",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x800200001",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x400200001",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x100200001",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts demand data reads",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.SNOOP_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x200200001",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts demand data reads",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.SNOOP_NONE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x80200001",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_M.ANY_SNOOP",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.ANY_SNOOP",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3F80040001",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_M.HITM_OTHER_CORE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.HITM_OTHER_CORE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x1000040001",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x800040001",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x400040001",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x100040001",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts demand data reads",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.SNOOP_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x200040001",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts demand data reads",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.SNOOP_NONE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x80040001",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_S.ANY_SNOOP",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.ANY_SNOOP",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3F80100001",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_S.HITM_OTHER_CORE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.HITM_OTHER_CORE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x1000100001",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x800100001",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x400100001",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x100100001",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts demand data reads",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.SNOOP_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x200100001",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts demand data reads",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.SNOOP_NONE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x80100001",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.ANY_SNOOP OCR.DEMAND_RFO.L3_HIT.ANY_SNOOP",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_RFO.L3_HIT.ANY_SNOOP",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3F803C0002",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x10003C0002",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x8003C0002",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x4003C0002",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x1003C0002",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all demand data writes (RFOs)",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x8007C0002",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x2003C0002",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.SNOOP_NONE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_NONE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x803C0002",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_E.ANY_SNOOP",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_RFO.L3_HIT_E.ANY_SNOOP",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3F80080002",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_E.HITM_OTHER_CORE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_RFO.L3_HIT_E.HITM_OTHER_CORE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x1000080002",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x800080002",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x400080002",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_E.NO_SNOOP_NEEDED",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_RFO.L3_HIT_E.NO_SNOOP_NEEDED",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x100080002",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all demand data writes (RFOs)",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_RFO.L3_HIT_E.SNOOP_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x200080002",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all demand data writes (RFOs)",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_RFO.L3_HIT_E.SNOOP_NONE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x80080002",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_F.ANY_SNOOP",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_RFO.L3_HIT_F.ANY_SNOOP",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3F80200002",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_F.HITM_OTHER_CORE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_RFO.L3_HIT_F.HITM_OTHER_CORE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x1000200002",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x800200002",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x400200002",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_F.NO_SNOOP_NEEDED",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_RFO.L3_HIT_F.NO_SNOOP_NEEDED",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x100200002",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all demand data writes (RFOs)",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_RFO.L3_HIT_F.SNOOP_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x200200002",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all demand data writes (RFOs)",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_RFO.L3_HIT_F.SNOOP_NONE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x80200002",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_M.ANY_SNOOP",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_RFO.L3_HIT_M.ANY_SNOOP",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3F80040002",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_M.HITM_OTHER_CORE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_RFO.L3_HIT_M.HITM_OTHER_CORE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x1000040002",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x800040002",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x400040002",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_M.NO_SNOOP_NEEDED",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_RFO.L3_HIT_M.NO_SNOOP_NEEDED",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x100040002",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all demand data writes (RFOs)",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_RFO.L3_HIT_M.SNOOP_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x200040002",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all demand data writes (RFOs)",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_RFO.L3_HIT_M.SNOOP_NONE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x80040002",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_S.ANY_SNOOP",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_RFO.L3_HIT_S.ANY_SNOOP",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3F80100002",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_S.HITM_OTHER_CORE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_RFO.L3_HIT_S.HITM_OTHER_CORE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x1000100002",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x800100002",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x400100002",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_S.NO_SNOOP_NEEDED",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_RFO.L3_HIT_S.NO_SNOOP_NEEDED",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x100100002",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all demand data writes (RFOs)",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_RFO.L3_HIT_S.SNOOP_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x200100002",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all demand data writes (RFOs)",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_RFO.L3_HIT_S.SNOOP_NONE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x80100002",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.ANY_SNOOP OCR.OTHER.L3_HIT.ANY_SNOOP",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.OTHER.L3_HIT.ANY_SNOOP",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3F803C8000",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.HITM_OTHER_CORE OCR.OTHER.L3_HIT.HITM_OTHER_CORE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.OTHER.L3_HIT.HITM_OTHER_CORE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x10003C8000",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.HIT_OTHER_CORE_FWD OCR.OTHER.L3_HIT.HIT_OTHER_CORE_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.OTHER.L3_HIT.HIT_OTHER_CORE_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x8003C8000",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.OTHER.L3_HIT.HIT_OTHER_CORE_NO_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.OTHER.L3_HIT.HIT_OTHER_CORE_NO_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x4003C8000",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.NO_SNOOP_NEEDED OCR.OTHER.L3_HIT.NO_SNOOP_NEEDED",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.OTHER.L3_HIT.NO_SNOOP_NEEDED",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x1003C8000",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts any other requests",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.OTHER.L3_HIT.SNOOP_HIT_WITH_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x8007C8000",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.SNOOP_MISS",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.OTHER.L3_HIT.SNOOP_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x2003C8000",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.SNOOP_NONE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.OTHER.L3_HIT.SNOOP_NONE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x803C8000",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_E.ANY_SNOOP",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.OTHER.L3_HIT_E.ANY_SNOOP",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3F80088000",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_E.HITM_OTHER_CORE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.OTHER.L3_HIT_E.HITM_OTHER_CORE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x1000088000",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x800088000",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x400088000",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_E.NO_SNOOP_NEEDED",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.OTHER.L3_HIT_E.NO_SNOOP_NEEDED",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x100088000",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts any other requests",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.OTHER.L3_HIT_E.SNOOP_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x200088000",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts any other requests",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.OTHER.L3_HIT_E.SNOOP_NONE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x80088000",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_F.ANY_SNOOP",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.OTHER.L3_HIT_F.ANY_SNOOP",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3F80208000",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_F.HITM_OTHER_CORE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.OTHER.L3_HIT_F.HITM_OTHER_CORE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x1000208000",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x800208000",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x400208000",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_F.NO_SNOOP_NEEDED",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.OTHER.L3_HIT_F.NO_SNOOP_NEEDED",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x100208000",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts any other requests",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.OTHER.L3_HIT_F.SNOOP_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x200208000",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts any other requests",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.OTHER.L3_HIT_F.SNOOP_NONE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x80208000",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_M.ANY_SNOOP",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.OTHER.L3_HIT_M.ANY_SNOOP",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3F80048000",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_M.HITM_OTHER_CORE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.OTHER.L3_HIT_M.HITM_OTHER_CORE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x1000048000",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x800048000",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x400048000",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_M.NO_SNOOP_NEEDED",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.OTHER.L3_HIT_M.NO_SNOOP_NEEDED",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x100048000",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts any other requests",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.OTHER.L3_HIT_M.SNOOP_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x200048000",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts any other requests",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.OTHER.L3_HIT_M.SNOOP_NONE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x80048000",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_S.ANY_SNOOP",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.OTHER.L3_HIT_S.ANY_SNOOP",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3F80108000",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_S.HITM_OTHER_CORE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.OTHER.L3_HIT_S.HITM_OTHER_CORE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x1000108000",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x800108000",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x400108000",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_S.NO_SNOOP_NEEDED",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.OTHER.L3_HIT_S.NO_SNOOP_NEEDED",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x100108000",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts any other requests",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.OTHER.L3_HIT_S.SNOOP_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x200108000",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts any other requests",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.OTHER.L3_HIT_S.SNOOP_NONE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x80108000",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.ANY_SNOOP OCR.PF_L1D_AND_SW.L3_HIT.ANY_SNOOP",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.ANY_SNOOP",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3F803C0400",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.HITM_OTHER_CORE OCR.PF_L1D_AND_SW.L3_HIT.HITM_OTHER_CORE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.HITM_OTHER_CORE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x10003C0400",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x8003C0400",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_NO_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_NO_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x4003C0400",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDED",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDED",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x1003C0400",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_HIT_WITH_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x8007C0400",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_MISS",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x2003C0400",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_NONE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_NONE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x803C0400",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_E.ANY_SNOOP",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.ANY_SNOOP",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3F80080400",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_E.HITM_OTHER_CORE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.HITM_OTHER_CORE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x1000080400",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x800080400",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x400080400",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_E.NO_SNOOP_NEEDED",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.NO_SNOOP_NEEDED",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x100080400",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.SNOOP_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x200080400",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.SNOOP_NONE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x80080400",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_F.ANY_SNOOP",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.ANY_SNOOP",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3F80200400",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_F.HITM_OTHER_CORE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.HITM_OTHER_CORE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x1000200400",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x800200400",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x400200400",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_F.NO_SNOOP_NEEDED",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.NO_SNOOP_NEEDED",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x100200400",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.SNOOP_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x200200400",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.SNOOP_NONE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x80200400",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_M.ANY_SNOOP",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.ANY_SNOOP",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3F80040400",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_M.HITM_OTHER_CORE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.HITM_OTHER_CORE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x1000040400",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x800040400",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x400040400",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_M.NO_SNOOP_NEEDED",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.NO_SNOOP_NEEDED",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x100040400",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.SNOOP_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x200040400",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.SNOOP_NONE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x80040400",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_S.ANY_SNOOP",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.ANY_SNOOP",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3F80100400",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_S.HITM_OTHER_CORE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.HITM_OTHER_CORE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x1000100400",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x800100400",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x400100400",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_S.NO_SNOOP_NEEDED",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.NO_SNOOP_NEEDED",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x100100400",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.SNOOP_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x200100400",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.SNOOP_NONE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x80100400",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP OCR.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3F803C0010",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.PF_L2_DATA_RD.L3_HIT.HITM_OTHER_CORE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.HITM_OTHER_CORE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x10003C0010",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x8003C0010",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x4003C0010",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x1003C0010",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x8007C0010",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_MISS",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x2003C0010",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_NONE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_NONE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x803C0010",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_E.ANY_SNOOP",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.ANY_SNOOP",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3F80080010",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_E.HITM_OTHER_CORE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.HITM_OTHER_CORE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x1000080010",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x800080010",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x400080010",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x100080010",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.SNOOP_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x200080010",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.SNOOP_NONE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x80080010",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_F.ANY_SNOOP",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.ANY_SNOOP",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3F80200010",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_F.HITM_OTHER_CORE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.HITM_OTHER_CORE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x1000200010",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x800200010",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x400200010",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x100200010",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.SNOOP_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x200200010",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.SNOOP_NONE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x80200010",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_M.ANY_SNOOP",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.ANY_SNOOP",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3F80040010",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_M.HITM_OTHER_CORE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.HITM_OTHER_CORE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x1000040010",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x800040010",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x400040010",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x100040010",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.SNOOP_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x200040010",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.SNOOP_NONE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x80040010",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_S.ANY_SNOOP",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.ANY_SNOOP",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3F80100010",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_S.HITM_OTHER_CORE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.HITM_OTHER_CORE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x1000100010",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x800100010",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x400100010",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x100100010",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.SNOOP_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x200100010",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.SNOOP_NONE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x80100010",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.ANY_SNOOP OCR.PF_L2_RFO.L3_HIT.ANY_SNOOP",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L2_RFO.L3_HIT.ANY_SNOOP",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3F803C0020",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x10003C0020",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x8003C0020",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x4003C0020",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x1003C0020",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L2_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x8007C0020",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.SNOOP_MISS",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L2_RFO.L3_HIT.SNOOP_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x2003C0020",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.SNOOP_NONE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L2_RFO.L3_HIT.SNOOP_NONE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x803C0020",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_E.ANY_SNOOP",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L2_RFO.L3_HIT_E.ANY_SNOOP",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3F80080020",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_E.HITM_OTHER_CORE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L2_RFO.L3_HIT_E.HITM_OTHER_CORE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x1000080020",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x800080020",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x400080020",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_E.NO_SNOOP_NEEDED",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L2_RFO.L3_HIT_E.NO_SNOOP_NEEDED",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x100080020",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L2_RFO.L3_HIT_E.SNOOP_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x200080020",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L2_RFO.L3_HIT_E.SNOOP_NONE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x80080020",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_F.ANY_SNOOP",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L2_RFO.L3_HIT_F.ANY_SNOOP",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3F80200020",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_F.HITM_OTHER_CORE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L2_RFO.L3_HIT_F.HITM_OTHER_CORE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x1000200020",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x800200020",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x400200020",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_F.NO_SNOOP_NEEDED",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L2_RFO.L3_HIT_F.NO_SNOOP_NEEDED",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x100200020",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L2_RFO.L3_HIT_F.SNOOP_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x200200020",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L2_RFO.L3_HIT_F.SNOOP_NONE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x80200020",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_M.ANY_SNOOP",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L2_RFO.L3_HIT_M.ANY_SNOOP",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3F80040020",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_M.HITM_OTHER_CORE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L2_RFO.L3_HIT_M.HITM_OTHER_CORE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x1000040020",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x800040020",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x400040020",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_M.NO_SNOOP_NEEDED",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L2_RFO.L3_HIT_M.NO_SNOOP_NEEDED",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x100040020",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L2_RFO.L3_HIT_M.SNOOP_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x200040020",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L2_RFO.L3_HIT_M.SNOOP_NONE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x80040020",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_S.ANY_SNOOP",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L2_RFO.L3_HIT_S.ANY_SNOOP",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3F80100020",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_S.HITM_OTHER_CORE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L2_RFO.L3_HIT_S.HITM_OTHER_CORE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x1000100020",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x800100020",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x400100020",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_S.NO_SNOOP_NEEDED",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L2_RFO.L3_HIT_S.NO_SNOOP_NEEDED",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x100100020",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L2_RFO.L3_HIT_S.SNOOP_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x200100020",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L2_RFO.L3_HIT_S.SNOOP_NONE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x80100020",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP OCR.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3F803C0080",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.PF_L3_DATA_RD.L3_HIT.HITM_OTHER_CORE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.HITM_OTHER_CORE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x10003C0080",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x8003C0080",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x4003C0080",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x1003C0080",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x8007C0080",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_MISS",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x2003C0080",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_NONE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_NONE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x803C0080",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_E.ANY_SNOOP",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.ANY_SNOOP",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3F80080080",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_E.HITM_OTHER_CORE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.HITM_OTHER_CORE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x1000080080",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x800080080",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x400080080",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x100080080",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.SNOOP_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x200080080",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.SNOOP_NONE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x80080080",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_F.ANY_SNOOP",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.ANY_SNOOP",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3F80200080",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_F.HITM_OTHER_CORE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.HITM_OTHER_CORE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x1000200080",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x800200080",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x400200080",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x100200080",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.SNOOP_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x200200080",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.SNOOP_NONE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x80200080",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_M.ANY_SNOOP",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.ANY_SNOOP",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3F80040080",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_M.HITM_OTHER_CORE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.HITM_OTHER_CORE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x1000040080",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x800040080",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x400040080",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x100040080",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.SNOOP_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x200040080",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.SNOOP_NONE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x80040080",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_S.ANY_SNOOP",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.ANY_SNOOP",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3F80100080",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_S.HITM_OTHER_CORE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.HITM_OTHER_CORE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x1000100080",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x800100080",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x400100080",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x100100080",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.SNOOP_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x200100080",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.SNOOP_NONE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x80100080",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.ANY_SNOOP OCR.PF_L3_RFO.L3_HIT.ANY_SNOOP",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L3_RFO.L3_HIT.ANY_SNOOP",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3F803C0100",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.HITM_OTHER_CORE OCR.PF_L3_RFO.L3_HIT.HITM_OTHER_CORE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L3_RFO.L3_HIT.HITM_OTHER_CORE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x10003C0100",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x8003C0100",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x4003C0100",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x1003C0100",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L3_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x8007C0100",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.SNOOP_MISS",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L3_RFO.L3_HIT.SNOOP_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x2003C0100",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.SNOOP_NONE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L3_RFO.L3_HIT.SNOOP_NONE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x803C0100",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_E.ANY_SNOOP",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L3_RFO.L3_HIT_E.ANY_SNOOP",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3F80080100",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_E.HITM_OTHER_CORE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L3_RFO.L3_HIT_E.HITM_OTHER_CORE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x1000080100",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x800080100",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x400080100",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_E.NO_SNOOP_NEEDED",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L3_RFO.L3_HIT_E.NO_SNOOP_NEEDED",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x100080100",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L3_RFO.L3_HIT_E.SNOOP_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x200080100",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L3_RFO.L3_HIT_E.SNOOP_NONE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x80080100",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_F.ANY_SNOOP",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L3_RFO.L3_HIT_F.ANY_SNOOP",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3F80200100",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_F.HITM_OTHER_CORE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L3_RFO.L3_HIT_F.HITM_OTHER_CORE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x1000200100",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x800200100",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x400200100",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_F.NO_SNOOP_NEEDED",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L3_RFO.L3_HIT_F.NO_SNOOP_NEEDED",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x100200100",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L3_RFO.L3_HIT_F.SNOOP_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x200200100",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L3_RFO.L3_HIT_F.SNOOP_NONE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x80200100",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_M.ANY_SNOOP",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L3_RFO.L3_HIT_M.ANY_SNOOP",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3F80040100",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_M.HITM_OTHER_CORE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L3_RFO.L3_HIT_M.HITM_OTHER_CORE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x1000040100",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x800040100",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x400040100",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_M.NO_SNOOP_NEEDED",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L3_RFO.L3_HIT_M.NO_SNOOP_NEEDED",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x100040100",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L3_RFO.L3_HIT_M.SNOOP_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x200040100",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L3_RFO.L3_HIT_M.SNOOP_NONE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x80040100",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_S.ANY_SNOOP",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L3_RFO.L3_HIT_S.ANY_SNOOP",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3F80100100",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_S.HITM_OTHER_CORE",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L3_RFO.L3_HIT_S.HITM_OTHER_CORE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x1000100100",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x800100100",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x400100100",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_S.NO_SNOOP_NEEDED",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L3_RFO.L3_HIT_S.NO_SNOOP_NEEDED",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x100100100",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L3_RFO.L3_HIT_S.SNOOP_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x200100100",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PF_L3_RFO.L3_HIT_S.SNOOP_NONE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x80100100",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
{
"BriefDescription": "Demand and prefetch data reads",
"Counter": "0,1,2,3",
@@ -9987,5 +16539,41 @@
"PublicDescription": "Counts the number of cache line split locks sent to the uncore.",
"SampleAfterValue": "100003",
"UMask": "0x10"
+ },
+ {
+ "BriefDescription": "Number of PREFETCHNTA instructions executed.",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3,4,5,6,7",
+ "EventCode": "0x32",
+ "EventName": "SW_PREFETCH_ACCESS.NTA",
+ "SampleAfterValue": "2000003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Number of PREFETCHW instructions executed.",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3,4,5,6,7",
+ "EventCode": "0x32",
+ "EventName": "SW_PREFETCH_ACCESS.PREFETCHW",
+ "SampleAfterValue": "2000003",
+ "UMask": "0x8"
+ },
+ {
+ "BriefDescription": "Number of PREFETCHT0 instructions executed.",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3,4,5,6,7",
+ "EventCode": "0x32",
+ "EventName": "SW_PREFETCH_ACCESS.T0",
+ "SampleAfterValue": "2000003",
+ "UMask": "0x2"
+ },
+ {
+ "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3,4,5,6,7",
+ "EventCode": "0x32",
+ "EventName": "SW_PREFETCH_ACCESS.T1_T2",
+ "SampleAfterValue": "2000003",
+ "UMask": "0x4"
}
]
\ No newline at end of file
diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/other.json b/tools/perf/pmu-events/arch/x86/cascadelakex/other.json
index d8b145a7d303..bb23a91b0127 100644
--- a/tools/perf/pmu-events/arch/x86/cascadelakex/other.json
+++ b/tools/perf/pmu-events/arch/x86/cascadelakex/other.json
@@ -83,8411 +83,1859 @@
"UMask": "0x1"
},
{
- "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP",
+ "BriefDescription": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP",
+ "EventName": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F803C0491",
+ "MSRValue": "0x3F80400491",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE",
+ "BriefDescription": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE",
+ "EventName": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x10003C0491",
+ "MSRValue": "0x80400491",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD",
+ "BriefDescription": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD",
+ "EventName": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x8003C0491",
+ "MSRValue": "0x100400491",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
+ "BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.ANY_SNOOP OCR.ALL_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
+ "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x4003C0491",
+ "MSRValue": "0x3F80020491",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
+ "BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE OCR.ALL_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
+ "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1003C0491",
+ "MSRValue": "0x1000020491",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
+ "BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
+ "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x8007C0491",
+ "MSRValue": "0x800020491",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_MISS OCR.ALL_DATA_RD.L3_HIT.SNOOP_MISS",
+ "BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_MISS",
+ "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x2003C0491",
+ "MSRValue": "0x400020491",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_NONE OCR.ALL_DATA_RD.L3_HIT.SNOOP_NONE",
+ "BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_NONE",
+ "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x803C0491",
+ "MSRValue": "0x100020491",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT_E.ANY_SNOOP",
+ "BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_MISS",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.ANY_SNOOP",
+ "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F80080491",
+ "MSRValue": "0x200020491",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT_E.HITM_OTHER_CORE",
+ "BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.HITM_OTHER_CORE",
+ "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1000080491",
+ "MSRValue": "0x80020491",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD",
+ "BriefDescription": "OCR.ALL_PF_DATA_RD.ANY_RESPONSE have any response type.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD",
+ "EventName": "OCR.ALL_PF_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x800080491",
+ "MSRValue": "0x10490",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
+ "BriefDescription": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
+ "EventName": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x400080491",
+ "MSRValue": "0x3F80400490",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED",
+ "BriefDescription": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED",
+ "EventName": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x100080491",
+ "MSRValue": "0x80400490",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_MISS",
+ "BriefDescription": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_MISS",
+ "EventName": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x200080491",
+ "MSRValue": "0x100400490",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_NONE",
+ "BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.ANY_SNOOP OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_NONE",
+ "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x80080491",
+ "MSRValue": "0x3F80020490",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT_F.ANY_SNOOP",
+ "BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.ANY_SNOOP",
+ "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F80200491",
+ "MSRValue": "0x1000020490",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT_F.HITM_OTHER_CORE",
+ "BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.HITM_OTHER_CORE",
+ "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1000200491",
+ "MSRValue": "0x800020490",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD",
+ "BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD",
+ "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x800200491",
+ "MSRValue": "0x400020490",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
+ "BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
+ "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x400200491",
+ "MSRValue": "0x100020490",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED",
+ "BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_MISS",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED",
+ "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x100200491",
+ "MSRValue": "0x200020490",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_MISS",
+ "BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_MISS",
+ "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x200200491",
+ "MSRValue": "0x80020490",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_NONE",
+ "BriefDescription": "OCR.ALL_PF_RFO.ANY_RESPONSE have any response type.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_NONE",
+ "EventName": "OCR.ALL_PF_RFO.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x80200491",
+ "MSRValue": "0x10120",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT_M.ANY_SNOOP",
+ "BriefDescription": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.ANY_SNOOP",
+ "EventName": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F80040491",
+ "MSRValue": "0x3F80400120",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT_M.HITM_OTHER_CORE",
+ "BriefDescription": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.HITM_OTHER_CORE",
+ "EventName": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1000040491",
+ "MSRValue": "0x80400120",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD",
+ "BriefDescription": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD",
+ "EventName": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x800040491",
+ "MSRValue": "0x100400120",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
+ "BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.ANY_SNOOP OCR.ALL_PF_RFO.SUPPLIER_NONE.ANY_SNOOP",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
+ "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x400040491",
+ "MSRValue": "0x3F80020120",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED",
+ "BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HITM_OTHER_CORE OCR.ALL_PF_RFO.SUPPLIER_NONE.HITM_OTHER_CORE",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED",
+ "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x100040491",
+ "MSRValue": "0x1000020120",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_MISS",
+ "BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_MISS",
+ "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x200040491",
+ "MSRValue": "0x800020120",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_NONE",
+ "BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_NONE",
+ "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x80040491",
+ "MSRValue": "0x400020120",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT_S.ANY_SNOOP",
+ "BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.ANY_SNOOP",
+ "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F80100491",
+ "MSRValue": "0x100020120",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT_S.HITM_OTHER_CORE",
+ "BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_MISS",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.HITM_OTHER_CORE",
+ "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1000100491",
+ "MSRValue": "0x200020120",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD",
+ "BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NONE",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD",
+ "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x800100491",
+ "MSRValue": "0x80020120",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
+ "BriefDescription": "OCR.ALL_READS.ANY_RESPONSE have any response type.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
+ "EventName": "OCR.ALL_READS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x400100491",
+ "MSRValue": "0x107F7",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED",
+ "BriefDescription": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_READS.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED",
+ "EventName": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x100100491",
+ "MSRValue": "0x3F804007F7",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_MISS",
+ "BriefDescription": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_MISS",
+ "EventName": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x200100491",
+ "MSRValue": "0x804007F7",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_NONE",
+ "BriefDescription": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_NONE",
+ "EventName": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x80100491",
+ "MSRValue": "0x1004007F7",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
+ "BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.ANY_SNOOP OCR.ALL_READS.SUPPLIER_NONE.ANY_SNOOP",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
+ "EventName": "OCR.ALL_READS.SUPPLIER_NONE.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F80400491",
+ "MSRValue": "0x3F800207F7",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
+ "BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.HITM_OTHER_CORE OCR.ALL_READS.SUPPLIER_NONE.HITM_OTHER_CORE",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
+ "EventName": "OCR.ALL_READS.SUPPLIER_NONE.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x80400491",
+ "MSRValue": "0x10000207F7",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
+ "BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_FWD OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
+ "EventName": "OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x100400491",
+ "MSRValue": "0x8000207F7",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.ANY_SNOOP OCR.ALL_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
+ "BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
+ "EventName": "OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F80020491",
+ "MSRValue": "0x4000207F7",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE OCR.ALL_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE",
+ "BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.NO_SNOOP_NEEDED OCR.ALL_READS.SUPPLIER_NONE.NO_SNOOP_NEEDED",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE",
+ "EventName": "OCR.ALL_READS.SUPPLIER_NONE.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1000020491",
+ "MSRValue": "0x1000207F7",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
+ "BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.SNOOP_MISS",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
+ "EventName": "OCR.ALL_READS.SUPPLIER_NONE.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x800020491",
+ "MSRValue": "0x2000207F7",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
+ "BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.SNOOP_NONE",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
+ "EventName": "OCR.ALL_READS.SUPPLIER_NONE.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x400020491",
+ "MSRValue": "0x800207F7",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED",
+ "BriefDescription": "OCR.ALL_RFO.ANY_RESPONSE have any response type.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED",
+ "EventName": "OCR.ALL_RFO.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x100020491",
+ "MSRValue": "0x10122",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_MISS",
+ "BriefDescription": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_MISS",
+ "EventName": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x200020491",
+ "MSRValue": "0x3F80400122",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",
+ "BriefDescription": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",
+ "EventName": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x80020491",
+ "MSRValue": "0x80400122",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "OCR.ALL_PF_DATA_RD.ANY_RESPONSE have any response type.",
+ "BriefDescription": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_DATA_RD.ANY_RESPONSE",
+ "EventName": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x10490",
+ "MSRValue": "0x100400122",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP",
+ "BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.ANY_SNOOP OCR.ALL_RFO.SUPPLIER_NONE.ANY_SNOOP",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP",
+ "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F803C0490",
+ "MSRValue": "0x3F80020122",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE",
+ "BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.HITM_OTHER_CORE OCR.ALL_RFO.SUPPLIER_NONE.HITM_OTHER_CORE",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE",
+ "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x10003C0490",
+ "MSRValue": "0x1000020122",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD",
+ "BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD",
+ "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x8003C0490",
+ "MSRValue": "0x800020122",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
+ "BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
+ "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x4003C0490",
+ "MSRValue": "0x400020122",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
+ "BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED OCR.ALL_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
+ "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1003C0490",
+ "MSRValue": "0x100020122",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
+ "BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_MISS",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
+ "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x8007C0490",
+ "MSRValue": "0x200020122",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS",
+ "BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_NONE",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS",
+ "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x2003C0490",
+ "MSRValue": "0x80020122",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE",
+ "BriefDescription": "Counts all demand code reads have any response type.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE",
+ "EventName": "OCR.DEMAND_CODE_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x803C0490",
+ "MSRValue": "0x10004",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT_E.ANY_SNOOP",
+ "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.ANY_SNOOP",
+ "EventName": "OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F80080490",
+ "MSRValue": "0x3F80400004",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT_E.HITM_OTHER_CORE",
+ "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HITM_OTHER_CORE",
+ "EventName": "OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1000080490",
+ "MSRValue": "0x80400004",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD",
+ "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD",
+ "EventName": "OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x800080490",
+ "MSRValue": "0x100400004",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
+ "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.SUPPLIER_NONE.ANY_SNOOP",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
+ "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x400080490",
+ "MSRValue": "0x3F80020004",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED",
+ "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HITM_OTHER_CORE",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED",
+ "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x100080490",
+ "MSRValue": "0x1000020004",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_MISS",
+ "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_MISS",
+ "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x200080490",
+ "MSRValue": "0x800020004",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_NONE",
+ "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_NONE",
+ "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x80080490",
+ "MSRValue": "0x400020004",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT_F.ANY_SNOOP",
+ "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.ANY_SNOOP",
+ "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F80200490",
+ "MSRValue": "0x100020004",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT_F.HITM_OTHER_CORE",
+ "BriefDescription": "Counts all demand code reads",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HITM_OTHER_CORE",
+ "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1000200490",
+ "MSRValue": "0x200020004",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD",
+ "BriefDescription": "Counts all demand code reads",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD",
+ "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x800200490",
+ "MSRValue": "0x80020004",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
+ "BriefDescription": "Counts demand data reads have any response type.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
+ "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x400200490",
+ "MSRValue": "0x10001",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED",
+ "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED",
+ "EventName": "OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x100200490",
+ "MSRValue": "0x3F80400001",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_MISS",
+ "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_MISS",
+ "EventName": "OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x200200490",
+ "MSRValue": "0x80400001",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_NONE",
+ "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_NONE",
+ "EventName": "OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x80200490",
+ "MSRValue": "0x100400001",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT_M.ANY_SNOOP",
+ "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.ANY_SNOOP",
+ "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F80040490",
+ "MSRValue": "0x3F80020001",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT_M.HITM_OTHER_CORE",
+ "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HITM_OTHER_CORE",
+ "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1000040490",
+ "MSRValue": "0x1000020001",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD",
+ "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD",
+ "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x800040490",
+ "MSRValue": "0x800020001",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
+ "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
+ "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x400040490",
+ "MSRValue": "0x400020001",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED",
+ "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED",
+ "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x100040490",
+ "MSRValue": "0x100020001",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_MISS",
+ "BriefDescription": "Counts demand data reads",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_MISS",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x200040490",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_NONE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x80040490",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT_S.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.ANY_SNOOP",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F80100490",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT_S.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HITM_OTHER_CORE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1000100490",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x800100490",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x400100490",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x100100490",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_MISS",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x200100490",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_NONE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x80100490",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F80400490",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x80400490",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x100400490",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.ANY_SNOOP OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F80020490",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1000020490",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x800020490",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x400020490",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x100020490",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_MISS",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x200020490",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x80020490",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_PF_RFO.ANY_RESPONSE have any response type.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_RFO.ANY_RESPONSE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x10120",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F803C0120",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x10003C0120",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x8003C0120",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x4003C0120",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1003C0120",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x8007C0120",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_MISS OCR.ALL_PF_RFO.L3_HIT.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_MISS",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x2003C0120",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_NONE OCR.ALL_PF_RFO.L3_HIT.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_NONE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x803C0120",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT_E.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.ANY_SNOOP",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F80080120",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT_E.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.HITM_OTHER_CORE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1000080120",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x800080120",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x400080120",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT_E.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.NO_SNOOP_NEEDED",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x100080120",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_MISS",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x200080120",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_NONE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x80080120",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT_F.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.ANY_SNOOP",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F80200120",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT_F.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.HITM_OTHER_CORE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1000200120",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x800200120",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x400200120",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT_F.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.NO_SNOOP_NEEDED",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x100200120",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_MISS",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x200200120",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_NONE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x80200120",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT_M.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.ANY_SNOOP",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F80040120",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT_M.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.HITM_OTHER_CORE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1000040120",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x800040120",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x400040120",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT_M.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.NO_SNOOP_NEEDED",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x100040120",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_MISS",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x200040120",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_NONE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x80040120",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT_S.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.ANY_SNOOP",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F80100120",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT_S.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.HITM_OTHER_CORE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1000100120",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x800100120",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x400100120",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT_S.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.NO_SNOOP_NEEDED",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x100100120",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_MISS",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x200100120",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_NONE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x80100120",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F80400120",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x80400120",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x100400120",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.ANY_SNOOP OCR.ALL_PF_RFO.SUPPLIER_NONE.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.ANY_SNOOP",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F80020120",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HITM_OTHER_CORE OCR.ALL_PF_RFO.SUPPLIER_NONE.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HITM_OTHER_CORE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1000020120",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x800020120",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x400020120",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x100020120",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_MISS",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x200020120",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NONE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x80020120",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_READS.ANY_RESPONSE have any response type.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_READS.ANY_RESPONSE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x107F7",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_READS.L3_HIT.ANY_SNOOP OCR.ALL_READS.L3_HIT.ANY_SNOOP OCR.ALL_READS.L3_HIT.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_READS.L3_HIT.ANY_SNOOP",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F803C07F7",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x10003C07F7",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x8003C07F7",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x4003C07F7",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1003C07F7",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_READS.L3_HIT.SNOOP_HIT_WITH_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_READS.L3_HIT.SNOOP_HIT_WITH_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x8007C07F7",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_READS.L3_HIT.SNOOP_MISS OCR.ALL_READS.L3_HIT.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_READS.L3_HIT.SNOOP_MISS",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x2003C07F7",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_READS.L3_HIT.SNOOP_NONE OCR.ALL_READS.L3_HIT.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_READS.L3_HIT.SNOOP_NONE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x803C07F7",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_READS.L3_HIT_E.ANY_SNOOP OCR.ALL_READS.L3_HIT_E.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_READS.L3_HIT_E.ANY_SNOOP",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F800807F7",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_READS.L3_HIT_E.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT_E.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_READS.L3_HIT_E.HITM_OTHER_CORE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x10000807F7",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x8000807F7",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x4000807F7",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_READS.L3_HIT_E.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT_E.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_READS.L3_HIT_E.NO_SNOOP_NEEDED",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1000807F7",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_READS.L3_HIT_E.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_READS.L3_HIT_E.SNOOP_MISS",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x2000807F7",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_READS.L3_HIT_E.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_READS.L3_HIT_E.SNOOP_NONE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x800807F7",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_READS.L3_HIT_F.ANY_SNOOP OCR.ALL_READS.L3_HIT_F.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_READS.L3_HIT_F.ANY_SNOOP",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F802007F7",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_READS.L3_HIT_F.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT_F.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_READS.L3_HIT_F.HITM_OTHER_CORE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x10002007F7",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x8002007F7",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x4002007F7",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_READS.L3_HIT_F.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT_F.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_READS.L3_HIT_F.NO_SNOOP_NEEDED",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1002007F7",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_READS.L3_HIT_F.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_READS.L3_HIT_F.SNOOP_MISS",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x2002007F7",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_READS.L3_HIT_F.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_READS.L3_HIT_F.SNOOP_NONE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x802007F7",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_READS.L3_HIT_M.ANY_SNOOP OCR.ALL_READS.L3_HIT_M.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_READS.L3_HIT_M.ANY_SNOOP",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F800407F7",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_READS.L3_HIT_M.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT_M.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_READS.L3_HIT_M.HITM_OTHER_CORE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x10000407F7",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x8000407F7",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x4000407F7",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_READS.L3_HIT_M.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT_M.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_READS.L3_HIT_M.NO_SNOOP_NEEDED",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1000407F7",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_READS.L3_HIT_M.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_READS.L3_HIT_M.SNOOP_MISS",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x2000407F7",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_READS.L3_HIT_M.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_READS.L3_HIT_M.SNOOP_NONE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x800407F7",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_READS.L3_HIT_S.ANY_SNOOP OCR.ALL_READS.L3_HIT_S.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_READS.L3_HIT_S.ANY_SNOOP",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F801007F7",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_READS.L3_HIT_S.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT_S.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_READS.L3_HIT_S.HITM_OTHER_CORE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x10001007F7",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x8001007F7",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x4001007F7",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_READS.L3_HIT_S.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT_S.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_READS.L3_HIT_S.NO_SNOOP_NEEDED",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1001007F7",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_READS.L3_HIT_S.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_READS.L3_HIT_S.SNOOP_MISS",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x2001007F7",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_READS.L3_HIT_S.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_READS.L3_HIT_S.SNOOP_NONE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x801007F7",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_READS.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F804007F7",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x804007F7",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1004007F7",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.ANY_SNOOP OCR.ALL_READS.SUPPLIER_NONE.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_READS.SUPPLIER_NONE.ANY_SNOOP",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F800207F7",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.HITM_OTHER_CORE OCR.ALL_READS.SUPPLIER_NONE.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_READS.SUPPLIER_NONE.HITM_OTHER_CORE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x10000207F7",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_FWD OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x8000207F7",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x4000207F7",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.NO_SNOOP_NEEDED OCR.ALL_READS.SUPPLIER_NONE.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_READS.SUPPLIER_NONE.NO_SNOOP_NEEDED",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1000207F7",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_READS.SUPPLIER_NONE.SNOOP_MISS",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x2000207F7",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_READS.SUPPLIER_NONE.SNOOP_NONE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x800207F7",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_RFO.ANY_RESPONSE have any response type.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_RFO.ANY_RESPONSE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x10122",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_RFO.L3_HIT.ANY_SNOOP OCR.ALL_RFO.L3_HIT.ANY_SNOOP OCR.ALL_RFO.L3_HIT.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_RFO.L3_HIT.ANY_SNOOP",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F803C0122",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x10003C0122",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x8003C0122",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x4003C0122",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1003C0122",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x8007C0122",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_RFO.L3_HIT.SNOOP_MISS OCR.ALL_RFO.L3_HIT.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_RFO.L3_HIT.SNOOP_MISS",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x2003C0122",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_RFO.L3_HIT.SNOOP_NONE OCR.ALL_RFO.L3_HIT.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_RFO.L3_HIT.SNOOP_NONE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x803C0122",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.ANY_SNOOP OCR.ALL_RFO.L3_HIT_E.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_RFO.L3_HIT_E.ANY_SNOOP",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F80080122",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT_E.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_RFO.L3_HIT_E.HITM_OTHER_CORE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1000080122",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x800080122",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x400080122",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT_E.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_RFO.L3_HIT_E.NO_SNOOP_NEEDED",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x100080122",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_RFO.L3_HIT_E.SNOOP_MISS",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x200080122",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_RFO.L3_HIT_E.SNOOP_NONE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x80080122",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.ANY_SNOOP OCR.ALL_RFO.L3_HIT_F.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_RFO.L3_HIT_F.ANY_SNOOP",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F80200122",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT_F.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_RFO.L3_HIT_F.HITM_OTHER_CORE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1000200122",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x800200122",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x400200122",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT_F.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_RFO.L3_HIT_F.NO_SNOOP_NEEDED",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x100200122",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_RFO.L3_HIT_F.SNOOP_MISS",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x200200122",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_RFO.L3_HIT_F.SNOOP_NONE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x80200122",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.ANY_SNOOP OCR.ALL_RFO.L3_HIT_M.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_RFO.L3_HIT_M.ANY_SNOOP",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F80040122",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT_M.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_RFO.L3_HIT_M.HITM_OTHER_CORE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1000040122",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x800040122",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x400040122",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT_M.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_RFO.L3_HIT_M.NO_SNOOP_NEEDED",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x100040122",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_RFO.L3_HIT_M.SNOOP_MISS",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x200040122",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_RFO.L3_HIT_M.SNOOP_NONE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x80040122",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.ANY_SNOOP OCR.ALL_RFO.L3_HIT_S.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_RFO.L3_HIT_S.ANY_SNOOP",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F80100122",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT_S.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_RFO.L3_HIT_S.HITM_OTHER_CORE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1000100122",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x800100122",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x400100122",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT_S.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_RFO.L3_HIT_S.NO_SNOOP_NEEDED",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x100100122",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_RFO.L3_HIT_S.SNOOP_MISS",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x200100122",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_RFO.L3_HIT_S.SNOOP_NONE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x80100122",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F80400122",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x80400122",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x100400122",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.ANY_SNOOP OCR.ALL_RFO.SUPPLIER_NONE.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.ANY_SNOOP",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F80020122",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.HITM_OTHER_CORE OCR.ALL_RFO.SUPPLIER_NONE.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.HITM_OTHER_CORE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1000020122",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x800020122",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x400020122",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED OCR.ALL_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x100020122",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_MISS",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x200020122",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_NONE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x80020122",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand code reads have any response type.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_CODE_RD.ANY_RESPONSE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x10004",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP OCR.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F803C0004",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE OCR.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x10003C0004",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x8003C0004",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x4003C0004",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDED OCR.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDED",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1003C0004",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x8007C0004",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x2003C0004",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NONE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x803C0004",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_E.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.ANY_SNOOP",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F80080004",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_E.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.HITM_OTHER_CORE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1000080004",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x800080004",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x400080004",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_E.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.NO_SNOOP_NEEDED",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x100080004",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.SNOOP_MISS",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x200080004",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NONE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x80080004",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_F.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.ANY_SNOOP",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F80200004",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_F.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.HITM_OTHER_CORE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1000200004",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x800200004",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x400200004",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_F.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.NO_SNOOP_NEEDED",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x100200004",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.SNOOP_MISS",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x200200004",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.SNOOP_NONE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x80200004",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_M.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.ANY_SNOOP",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F80040004",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_M.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.HITM_OTHER_CORE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1000040004",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x800040004",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x400040004",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_M.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.NO_SNOOP_NEEDED",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x100040004",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.SNOOP_MISS",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x200040004",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NONE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x80040004",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_S.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.ANY_SNOOP",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F80100004",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_S.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.HITM_OTHER_CORE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1000100004",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x800100004",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x400100004",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_S.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.NO_SNOOP_NEEDED",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x100100004",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.SNOOP_MISS",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x200100004",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NONE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x80100004",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F80400004",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x80400004",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x100400004",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.SUPPLIER_NONE.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.ANY_SNOOP",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F80020004",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HITM_OTHER_CORE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1000020004",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x800020004",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x400020004",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x100020004",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_MISS",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x200020004",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NONE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x80020004",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts demand data reads have any response type.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x10001",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP OCR.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F803C0001",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x10003C0001",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x8003C0001",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x4003C0001",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1003C0001",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x8007C0001",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x2003C0001",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NONE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x803C0001",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_E.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.ANY_SNOOP",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F80080001",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_E.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.HITM_OTHER_CORE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1000080001",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x800080001",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x400080001",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x100080001",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.SNOOP_MISS",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x200080001",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NONE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x80080001",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_F.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.ANY_SNOOP",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F80200001",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_F.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.HITM_OTHER_CORE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1000200001",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x800200001",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x400200001",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x100200001",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.SNOOP_MISS",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x200200001",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.SNOOP_NONE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x80200001",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_M.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.ANY_SNOOP",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F80040001",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_M.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.HITM_OTHER_CORE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1000040001",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x800040001",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x400040001",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x100040001",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.SNOOP_MISS",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x200040001",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.SNOOP_NONE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x80040001",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_S.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.ANY_SNOOP",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F80100001",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_S.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.HITM_OTHER_CORE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1000100001",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x800100001",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x400100001",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x100100001",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.SNOOP_MISS",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x200100001",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.SNOOP_NONE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x80100001",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F80400001",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x80400001",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x100400001",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F80020001",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1000020001",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x800020001",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x400020001",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x100020001",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_MISS",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x200020001",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x80020001",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand data writes (RFOs) have any response type.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x10002",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.ANY_SNOOP OCR.DEMAND_RFO.L3_HIT.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_RFO.L3_HIT.ANY_SNOOP",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F803C0002",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x10003C0002",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x8003C0002",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x4003C0002",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1003C0002",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x8007C0002",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x2003C0002",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_NONE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x803C0002",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_E.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_RFO.L3_HIT_E.ANY_SNOOP",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F80080002",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_E.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_RFO.L3_HIT_E.HITM_OTHER_CORE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1000080002",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x800080002",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x400080002",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_E.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_RFO.L3_HIT_E.NO_SNOOP_NEEDED",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x100080002",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_RFO.L3_HIT_E.SNOOP_MISS",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x200080002",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_RFO.L3_HIT_E.SNOOP_NONE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x80080002",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_F.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_RFO.L3_HIT_F.ANY_SNOOP",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F80200002",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_F.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_RFO.L3_HIT_F.HITM_OTHER_CORE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1000200002",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x800200002",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x400200002",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_F.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_RFO.L3_HIT_F.NO_SNOOP_NEEDED",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x100200002",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_RFO.L3_HIT_F.SNOOP_MISS",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x200200002",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_RFO.L3_HIT_F.SNOOP_NONE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x80200002",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_M.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_RFO.L3_HIT_M.ANY_SNOOP",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F80040002",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_M.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_RFO.L3_HIT_M.HITM_OTHER_CORE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1000040002",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x800040002",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x400040002",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_M.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_RFO.L3_HIT_M.NO_SNOOP_NEEDED",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x100040002",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_RFO.L3_HIT_M.SNOOP_MISS",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x200040002",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_RFO.L3_HIT_M.SNOOP_NONE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x80040002",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_S.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_RFO.L3_HIT_S.ANY_SNOOP",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F80100002",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_S.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_RFO.L3_HIT_S.HITM_OTHER_CORE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1000100002",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x800100002",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x400100002",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_S.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_RFO.L3_HIT_S.NO_SNOOP_NEEDED",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x100100002",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_RFO.L3_HIT_S.SNOOP_MISS",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x200100002",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_RFO.L3_HIT_S.SNOOP_NONE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x80100002",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F80400002",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x80400002",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x100400002",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.SUPPLIER_NONE.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.ANY_SNOOP",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F80020002",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.SUPPLIER_NONE.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.HITM_OTHER_CORE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1000020002",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x800020002",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x400020002",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x100020002",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.SNOOP_MISS",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x200020002",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.SNOOP_NONE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x80020002",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts any other requests have any response type.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.OTHER.ANY_RESPONSE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x18000",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.ANY_SNOOP OCR.OTHER.L3_HIT.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.OTHER.L3_HIT.ANY_SNOOP",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F803C8000",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.HITM_OTHER_CORE OCR.OTHER.L3_HIT.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.OTHER.L3_HIT.HITM_OTHER_CORE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x10003C8000",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.HIT_OTHER_CORE_FWD OCR.OTHER.L3_HIT.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.OTHER.L3_HIT.HIT_OTHER_CORE_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x8003C8000",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.OTHER.L3_HIT.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.OTHER.L3_HIT.HIT_OTHER_CORE_NO_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x4003C8000",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.NO_SNOOP_NEEDED OCR.OTHER.L3_HIT.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.OTHER.L3_HIT.NO_SNOOP_NEEDED",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1003C8000",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.OTHER.L3_HIT.SNOOP_HIT_WITH_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x8007C8000",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.OTHER.L3_HIT.SNOOP_MISS",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x2003C8000",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.OTHER.L3_HIT.SNOOP_NONE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x803C8000",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_E.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.OTHER.L3_HIT_E.ANY_SNOOP",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F80088000",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_E.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.OTHER.L3_HIT_E.HITM_OTHER_CORE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1000088000",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x800088000",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x400088000",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_E.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.OTHER.L3_HIT_E.NO_SNOOP_NEEDED",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x100088000",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.OTHER.L3_HIT_E.SNOOP_MISS",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x200088000",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.OTHER.L3_HIT_E.SNOOP_NONE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x80088000",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_F.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.OTHER.L3_HIT_F.ANY_SNOOP",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F80208000",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_F.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.OTHER.L3_HIT_F.HITM_OTHER_CORE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1000208000",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x800208000",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x400208000",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_F.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.OTHER.L3_HIT_F.NO_SNOOP_NEEDED",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x100208000",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.OTHER.L3_HIT_F.SNOOP_MISS",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x200208000",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.OTHER.L3_HIT_F.SNOOP_NONE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x80208000",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_M.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.OTHER.L3_HIT_M.ANY_SNOOP",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F80048000",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_M.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.OTHER.L3_HIT_M.HITM_OTHER_CORE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1000048000",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x800048000",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x400048000",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_M.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.OTHER.L3_HIT_M.NO_SNOOP_NEEDED",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x100048000",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.OTHER.L3_HIT_M.SNOOP_MISS",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x200048000",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.OTHER.L3_HIT_M.SNOOP_NONE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x80048000",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_S.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.OTHER.L3_HIT_S.ANY_SNOOP",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F80108000",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_S.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.OTHER.L3_HIT_S.HITM_OTHER_CORE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1000108000",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x800108000",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x400108000",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_S.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.OTHER.L3_HIT_S.NO_SNOOP_NEEDED",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x100108000",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.OTHER.L3_HIT_S.SNOOP_MISS",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x200108000",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.OTHER.L3_HIT_S.SNOOP_NONE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x80108000",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts any other requests OCR.OTHER.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.OTHER.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F80408000",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts any other requests OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x80408000",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts any other requests OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x100408000",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts any other requests OCR.OTHER.SUPPLIER_NONE.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.OTHER.SUPPLIER_NONE.ANY_SNOOP",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F80028000",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts any other requests OCR.OTHER.SUPPLIER_NONE.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.OTHER.SUPPLIER_NONE.HITM_OTHER_CORE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1000028000",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts any other requests OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x800028000",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts any other requests OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x400028000",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts any other requests OCR.OTHER.SUPPLIER_NONE.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.OTHER.SUPPLIER_NONE.NO_SNOOP_NEEDED",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x100028000",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.OTHER.SUPPLIER_NONE.SNOOP_MISS",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x200028000",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.OTHER.SUPPLIER_NONE.SNOOP_NONE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x80028000",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests have any response type.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L1D_AND_SW.ANY_RESPONSE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x10400",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.ANY_SNOOP OCR.PF_L1D_AND_SW.L3_HIT.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.ANY_SNOOP",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F803C0400",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.HITM_OTHER_CORE OCR.PF_L1D_AND_SW.L3_HIT.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.HITM_OTHER_CORE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x10003C0400",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x8003C0400",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_NO_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x4003C0400",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDED",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1003C0400",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_HIT_WITH_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x8007C0400",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_MISS",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x2003C0400",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_NONE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x803C0400",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_E.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.ANY_SNOOP",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F80080400",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_E.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.HITM_OTHER_CORE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1000080400",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x800080400",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x400080400",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_E.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.NO_SNOOP_NEEDED",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x100080400",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.SNOOP_MISS",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x200080400",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.SNOOP_NONE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x80080400",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_F.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.ANY_SNOOP",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F80200400",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_F.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.HITM_OTHER_CORE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1000200400",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x800200400",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x400200400",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_F.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.NO_SNOOP_NEEDED",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x100200400",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.SNOOP_MISS",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x200200400",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.SNOOP_NONE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x80200400",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_M.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.ANY_SNOOP",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F80040400",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_M.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.HITM_OTHER_CORE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1000040400",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x800040400",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x400040400",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_M.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.NO_SNOOP_NEEDED",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x100040400",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.SNOOP_MISS",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x200040400",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.SNOOP_NONE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x80040400",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_S.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.ANY_SNOOP",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F80100400",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_S.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.HITM_OTHER_CORE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1000100400",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x800100400",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x400100400",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_S.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.NO_SNOOP_NEEDED",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x100100400",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.SNOOP_MISS",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x200100400",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.SNOOP_NONE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x80100400",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F80400400",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x80400400",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x100400400",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.SUPPLIER_NONE.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.ANY_SNOOP",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F80020400",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HITM_OTHER_CORE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1000020400",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x800020400",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x400020400",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.SUPPLIER_NONE.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.NO_SNOOP_NEEDED",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x100020400",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.SNOOP_MISS",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x200020400",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.SNOOP_NONE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x80020400",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts prefetch (that bring data to L2) data reads have any response type.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_DATA_RD.ANY_RESPONSE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x10010",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP OCR.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F803C0010",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.PF_L2_DATA_RD.L3_HIT.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.HITM_OTHER_CORE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x10003C0010",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x8003C0010",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x4003C0010",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1003C0010",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x8007C0010",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_MISS",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x2003C0010",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_NONE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x803C0010",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_E.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.ANY_SNOOP",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F80080010",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_E.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.HITM_OTHER_CORE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1000080010",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x800080010",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x400080010",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x100080010",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.SNOOP_MISS",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x200080010",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.SNOOP_NONE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x80080010",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_F.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.ANY_SNOOP",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F80200010",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_F.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.HITM_OTHER_CORE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1000200010",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x800200010",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x400200010",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x100200010",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.SNOOP_MISS",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x200200010",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.SNOOP_NONE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x80200010",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_M.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.ANY_SNOOP",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F80040010",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_M.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.HITM_OTHER_CORE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1000040010",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x800040010",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x400040010",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x100040010",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.SNOOP_MISS",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x200040010",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.SNOOP_NONE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x80040010",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_S.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.ANY_SNOOP",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F80100010",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_S.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.HITM_OTHER_CORE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1000100010",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x800100010",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x400100010",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x100100010",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.SNOOP_MISS",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x200100010",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.SNOOP_NONE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x80100010",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F80400010",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x80400010",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x100400010",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F80020010",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1000020010",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x800020010",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x400020010",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x100020010",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_MISS",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x200020010",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x80020010",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs have any response type.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_RFO.ANY_RESPONSE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x10020",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.ANY_SNOOP OCR.PF_L2_RFO.L3_HIT.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_RFO.L3_HIT.ANY_SNOOP",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F803C0020",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x10003C0020",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x8003C0020",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x4003C0020",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1003C0020",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x8007C0020",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_RFO.L3_HIT.SNOOP_MISS",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x2003C0020",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_RFO.L3_HIT.SNOOP_NONE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x803C0020",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_E.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_RFO.L3_HIT_E.ANY_SNOOP",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F80080020",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_E.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_RFO.L3_HIT_E.HITM_OTHER_CORE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1000080020",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x800080020",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x400080020",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_E.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_RFO.L3_HIT_E.NO_SNOOP_NEEDED",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x100080020",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_RFO.L3_HIT_E.SNOOP_MISS",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x200080020",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_RFO.L3_HIT_E.SNOOP_NONE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x80080020",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_F.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_RFO.L3_HIT_F.ANY_SNOOP",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F80200020",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_F.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_RFO.L3_HIT_F.HITM_OTHER_CORE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1000200020",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x800200020",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x400200020",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_F.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_RFO.L3_HIT_F.NO_SNOOP_NEEDED",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x100200020",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_RFO.L3_HIT_F.SNOOP_MISS",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x200200020",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_RFO.L3_HIT_F.SNOOP_NONE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x80200020",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_M.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_RFO.L3_HIT_M.ANY_SNOOP",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F80040020",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_M.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_RFO.L3_HIT_M.HITM_OTHER_CORE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1000040020",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x800040020",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x400040020",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_M.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_RFO.L3_HIT_M.NO_SNOOP_NEEDED",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x100040020",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_RFO.L3_HIT_M.SNOOP_MISS",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x200040020",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_RFO.L3_HIT_M.SNOOP_NONE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x80040020",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_S.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_RFO.L3_HIT_S.ANY_SNOOP",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F80100020",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_S.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_RFO.L3_HIT_S.HITM_OTHER_CORE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1000100020",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x800100020",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x400100020",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_S.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_RFO.L3_HIT_S.NO_SNOOP_NEEDED",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x100100020",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_RFO.L3_HIT_S.SNOOP_MISS",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x200100020",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_RFO.L3_HIT_S.SNOOP_NONE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x80100020",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F80400020",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x80400020",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x100400020",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.SUPPLIER_NONE.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.ANY_SNOOP",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F80020020",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.SUPPLIER_NONE.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.HITM_OTHER_CORE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1000020020",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x800020020",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x400020020",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x100020020",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.SNOOP_MISS",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x200020020",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.SNOOP_NONE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x80020020",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads have any response type.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L3_DATA_RD.ANY_RESPONSE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x10080",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP OCR.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F803C0080",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.PF_L3_DATA_RD.L3_HIT.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.HITM_OTHER_CORE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x10003C0080",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x8003C0080",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x4003C0080",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1003C0080",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x8007C0080",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_MISS",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x2003C0080",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_NONE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x803C0080",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_E.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.ANY_SNOOP",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F80080080",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_E.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.HITM_OTHER_CORE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1000080080",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x800080080",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x400080080",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x100080080",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.SNOOP_MISS",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x200080080",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.SNOOP_NONE",
+ "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x80080080",
+ "MSRValue": "0x200020001",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_F.ANY_SNOOP",
+ "BriefDescription": "Counts demand data reads",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.ANY_SNOOP",
+ "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F80200080",
+ "MSRValue": "0x80020001",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_F.HITM_OTHER_CORE",
+ "BriefDescription": "Counts all demand data writes (RFOs) have any response type.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.HITM_OTHER_CORE",
+ "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1000200080",
+ "MSRValue": "0x10002",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD",
+ "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD",
+ "EventName": "OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x800200080",
+ "MSRValue": "0x3F80400002",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
+ "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
+ "EventName": "OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x400200080",
+ "MSRValue": "0x80400002",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED",
+ "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED",
+ "EventName": "OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x100200080",
+ "MSRValue": "0x100400002",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
+ "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.SUPPLIER_NONE.ANY_SNOOP",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.SNOOP_MISS",
+ "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x200200080",
+ "MSRValue": "0x3F80020002",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
+ "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.SUPPLIER_NONE.HITM_OTHER_CORE",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.SNOOP_NONE",
+ "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x80200080",
+ "MSRValue": "0x1000020002",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_M.ANY_SNOOP",
+ "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.ANY_SNOOP",
+ "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F80040080",
+ "MSRValue": "0x800020002",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_M.HITM_OTHER_CORE",
+ "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.HITM_OTHER_CORE",
+ "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1000040080",
+ "MSRValue": "0x400020002",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD",
+ "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD",
+ "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x800040080",
+ "MSRValue": "0x100020002",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
+ "BriefDescription": "Counts all demand data writes (RFOs)",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
+ "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x400040080",
+ "MSRValue": "0x200020002",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED",
+ "BriefDescription": "Counts all demand data writes (RFOs)",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED",
+ "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x100040080",
+ "MSRValue": "0x80020002",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
+ "BriefDescription": "Counts any other requests have any response type.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.SNOOP_MISS",
+ "EventName": "OCR.OTHER.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x200040080",
+ "MSRValue": "0x18000",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
+ "BriefDescription": "Counts any other requests OCR.OTHER.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.SNOOP_NONE",
+ "EventName": "OCR.OTHER.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x80040080",
+ "MSRValue": "0x3F80408000",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_S.ANY_SNOOP",
+ "BriefDescription": "Counts any other requests OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.ANY_SNOOP",
+ "EventName": "OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F80100080",
+ "MSRValue": "0x80408000",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_S.HITM_OTHER_CORE",
+ "BriefDescription": "Counts any other requests OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.HITM_OTHER_CORE",
+ "EventName": "OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1000100080",
+ "MSRValue": "0x100408000",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD",
+ "BriefDescription": "Counts any other requests OCR.OTHER.SUPPLIER_NONE.ANY_SNOOP",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD",
+ "EventName": "OCR.OTHER.SUPPLIER_NONE.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x800100080",
+ "MSRValue": "0x3F80028000",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
+ "BriefDescription": "Counts any other requests OCR.OTHER.SUPPLIER_NONE.HITM_OTHER_CORE",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
+ "EventName": "OCR.OTHER.SUPPLIER_NONE.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x400100080",
+ "MSRValue": "0x1000028000",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED",
+ "BriefDescription": "Counts any other requests OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED",
+ "EventName": "OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x100100080",
+ "MSRValue": "0x800028000",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
+ "BriefDescription": "Counts any other requests OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.SNOOP_MISS",
+ "EventName": "OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x200100080",
+ "MSRValue": "0x400028000",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
+ "BriefDescription": "Counts any other requests OCR.OTHER.SUPPLIER_NONE.NO_SNOOP_NEEDED",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.SNOOP_NONE",
+ "EventName": "OCR.OTHER.SUPPLIER_NONE.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x80100080",
+ "MSRValue": "0x100028000",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
+ "BriefDescription": "Counts any other requests",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
+ "EventName": "OCR.OTHER.SUPPLIER_NONE.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F80400080",
+ "MSRValue": "0x200028000",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
+ "BriefDescription": "Counts any other requests",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
+ "EventName": "OCR.OTHER.SUPPLIER_NONE.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x80400080",
+ "MSRValue": "0x80028000",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
+ "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests have any response type.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
+ "EventName": "OCR.PF_L1D_AND_SW.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x100400080",
+ "MSRValue": "0x10400",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
+ "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
+ "EventName": "OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F80020080",
+ "MSRValue": "0x3F80400400",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE",
+ "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE",
+ "EventName": "OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1000020080",
+ "MSRValue": "0x80400400",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
+ "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
+ "EventName": "OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x800020080",
+ "MSRValue": "0x100400400",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
+ "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.SUPPLIER_NONE.ANY_SNOOP",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
+ "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x400020080",
+ "MSRValue": "0x3F80020400",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED",
+ "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HITM_OTHER_CORE",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED",
+ "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x100020080",
+ "MSRValue": "0x1000020400",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
+ "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_MISS",
+ "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x200020080",
+ "MSRValue": "0x800020400",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
+ "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",
+ "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x80020080",
+ "MSRValue": "0x400020400",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs have any response type.",
+ "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.SUPPLIER_NONE.NO_SNOOP_NEEDED",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L3_RFO.ANY_RESPONSE",
+ "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x10100",
+ "MSRValue": "0x100020400",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.ANY_SNOOP OCR.PF_L3_RFO.L3_HIT.ANY_SNOOP",
+ "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L3_RFO.L3_HIT.ANY_SNOOP",
+ "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F803C0100",
+ "MSRValue": "0x200020400",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.HITM_OTHER_CORE OCR.PF_L3_RFO.L3_HIT.HITM_OTHER_CORE",
+ "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L3_RFO.L3_HIT.HITM_OTHER_CORE",
+ "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x10003C0100",
+ "MSRValue": "0x80020400",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_FWD",
+ "BriefDescription": "Counts prefetch (that bring data to L2) data reads have any response type.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_FWD",
+ "EventName": "OCR.PF_L2_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x8003C0100",
+ "MSRValue": "0x10010",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
+ "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
+ "EventName": "OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x4003C0100",
+ "MSRValue": "0x3F80400010",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED",
+ "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED",
+ "EventName": "OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1003C0100",
+ "MSRValue": "0x80400010",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
+ "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L3_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
+ "EventName": "OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x8007C0100",
+ "MSRValue": "0x100400010",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.SNOOP_MISS",
+ "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L3_RFO.L3_HIT.SNOOP_MISS",
+ "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x2003C0100",
+ "MSRValue": "0x3F80020010",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.SNOOP_NONE",
+ "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L3_RFO.L3_HIT.SNOOP_NONE",
+ "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x803C0100",
+ "MSRValue": "0x1000020010",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_E.ANY_SNOOP",
+ "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L3_RFO.L3_HIT_E.ANY_SNOOP",
+ "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F80080100",
+ "MSRValue": "0x800020010",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_E.HITM_OTHER_CORE",
+ "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L3_RFO.L3_HIT_E.HITM_OTHER_CORE",
+ "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1000080100",
+ "MSRValue": "0x400020010",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD",
+ "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD",
+ "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x800080100",
+ "MSRValue": "0x100020010",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
+ "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
+ "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x400080100",
+ "MSRValue": "0x200020010",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_E.NO_SNOOP_NEEDED",
+ "BriefDescription": "Counts prefetch (that bring data to L2) data reads",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L3_RFO.L3_HIT_E.NO_SNOOP_NEEDED",
+ "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x100080100",
+ "MSRValue": "0x80020010",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
+ "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs have any response type.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L3_RFO.L3_HIT_E.SNOOP_MISS",
+ "EventName": "OCR.PF_L2_RFO.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x200080100",
+ "MSRValue": "0x10020",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
+ "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L3_RFO.L3_HIT_E.SNOOP_NONE",
+ "EventName": "OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x80080100",
+ "MSRValue": "0x3F80400020",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_F.ANY_SNOOP",
+ "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L3_RFO.L3_HIT_F.ANY_SNOOP",
+ "EventName": "OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F80200100",
+ "MSRValue": "0x80400020",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_F.HITM_OTHER_CORE",
+ "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L3_RFO.L3_HIT_F.HITM_OTHER_CORE",
+ "EventName": "OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1000200100",
+ "MSRValue": "0x100400020",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD",
+ "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.SUPPLIER_NONE.ANY_SNOOP",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD",
+ "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x800200100",
+ "MSRValue": "0x3F80020020",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
+ "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.SUPPLIER_NONE.HITM_OTHER_CORE",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
+ "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x400200100",
+ "MSRValue": "0x1000020020",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_F.NO_SNOOP_NEEDED",
+ "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L3_RFO.L3_HIT_F.NO_SNOOP_NEEDED",
+ "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x100200100",
+ "MSRValue": "0x800020020",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
+ "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L3_RFO.L3_HIT_F.SNOOP_MISS",
+ "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x200200100",
+ "MSRValue": "0x400020020",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
+ "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L3_RFO.L3_HIT_F.SNOOP_NONE",
+ "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x80200100",
+ "MSRValue": "0x100020020",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_M.ANY_SNOOP",
+ "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L3_RFO.L3_HIT_M.ANY_SNOOP",
+ "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F80040100",
+ "MSRValue": "0x200020020",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_M.HITM_OTHER_CORE",
+ "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L3_RFO.L3_HIT_M.HITM_OTHER_CORE",
+ "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1000040100",
+ "MSRValue": "0x80020020",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD",
+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads have any response type.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD",
+ "EventName": "OCR.PF_L3_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x800040100",
+ "MSRValue": "0x10080",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
+ "EventName": "OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x400040100",
+ "MSRValue": "0x3F80400080",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_M.NO_SNOOP_NEEDED",
+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L3_RFO.L3_HIT_M.NO_SNOOP_NEEDED",
+ "EventName": "OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x100040100",
+ "MSRValue": "0x80400080",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L3_RFO.L3_HIT_M.SNOOP_MISS",
+ "EventName": "OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x200040100",
+ "MSRValue": "0x100400080",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L3_RFO.L3_HIT_M.SNOOP_NONE",
+ "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x80040100",
+ "MSRValue": "0x3F80020080",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_S.ANY_SNOOP",
+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L3_RFO.L3_HIT_S.ANY_SNOOP",
+ "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F80100100",
+ "MSRValue": "0x1000020080",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_S.HITM_OTHER_CORE",
+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L3_RFO.L3_HIT_S.HITM_OTHER_CORE",
+ "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1000100100",
+ "MSRValue": "0x800020080",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD",
+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD",
+ "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x800100100",
+ "MSRValue": "0x400020080",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
+ "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x400100100",
+ "MSRValue": "0x100020080",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_S.NO_SNOOP_NEEDED",
+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L3_RFO.L3_HIT_S.NO_SNOOP_NEEDED",
+ "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x100100100",
+ "MSRValue": "0x200020080",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L3_RFO.L3_HIT_S.SNOOP_MISS",
+ "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x200100100",
+ "MSRValue": "0x80020080",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs have any response type.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PF_L3_RFO.L3_HIT_S.SNOOP_NONE",
+ "EventName": "OCR.PF_L3_RFO.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x80100100",
+ "MSRValue": "0x10100",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
@@ -8622,41 +2070,5 @@
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
- },
- {
- "BriefDescription": "Number of PREFETCHNTA instructions executed.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
- "EventCode": "0x32",
- "EventName": "SW_PREFETCH_ACCESS.NTA",
- "SampleAfterValue": "2000003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Number of PREFETCHW instructions executed.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
- "EventCode": "0x32",
- "EventName": "SW_PREFETCH_ACCESS.PREFETCHW",
- "SampleAfterValue": "2000003",
- "UMask": "0x8"
- },
- {
- "BriefDescription": "Number of PREFETCHT0 instructions executed.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
- "EventCode": "0x32",
- "EventName": "SW_PREFETCH_ACCESS.T0",
- "SampleAfterValue": "2000003",
- "UMask": "0x2"
- },
- {
- "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
- "EventCode": "0x32",
- "EventName": "SW_PREFETCH_ACCESS.T1_T2",
- "SampleAfterValue": "2000003",
- "UMask": "0x4"
}
]
\ No newline at end of file
--
2.35.1.894.gb6a874cedc-goog
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 2/8] perf vendor events: Update events for Elkhartlake 2022-03-17 18:28 [PATCH 1/8] perf vendor events: Update events for CascadelakeX Ian Rogers @ 2022-03-17 18:28 ` Ian Rogers 2022-03-18 9:12 ` Xing Zhengjun 2022-03-17 18:28 ` [PATCH 3/8] perf vendor events: Update events for Icelake Ian Rogers ` (7 subsequent siblings) 8 siblings, 1 reply; 18+ messages in thread From: Ian Rogers @ 2022-03-17 18:28 UTC (permalink / raw) To: Kan Liang, Zhengjun Xing, Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo, Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim, Maxime Coquelin, Alexandre Torgue, Andi Kleen, James Clark, John Garry, linux-kernel, linux-perf-users Cc: Stephane Eranian, Ian Rogers The change: https://github.com/intel/event-converter-for-linux-perf/commit/fc680410402e394eed6a1ebd909c9f649d3ed3ef moved certain "other" type of events in to the pipeline topic. Update the perf json files for this change. Signed-off-by: Ian Rogers <irogers@google.com> --- .../arch/x86/elkhartlake/other.json | 241 ------------------ .../arch/x86/elkhartlake/pipeline.json | 241 ++++++++++++++++++ 2 files changed, 241 insertions(+), 241 deletions(-) diff --git a/tools/perf/pmu-events/arch/x86/elkhartlake/other.json b/tools/perf/pmu-events/arch/x86/elkhartlake/other.json index 627691404155..de55b199ba79 100644 --- a/tools/perf/pmu-events/arch/x86/elkhartlake/other.json +++ b/tools/perf/pmu-events/arch/x86/elkhartlake/other.json @@ -179,246 +179,5 @@ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" - }, - { - "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x73", - "EventName": "TOPDOWN_BAD_SPECULATION.ALL", - "PDIR_COUNTER": "na", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window including relevant microcode flows and while uops are not yet available in the instruction queue (IQ). Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear.", - "SampleAfterValue": "1000003", - "UMask": "0x6" - }, - { - "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to fast nukes such as memory ordering and memory disambiguation machine clears.", - "Counter": "0,1,2,3", - "EventCode": "0x73", - "EventName": "TOPDOWN_BAD_SPECULATION.FASTNUKE", - "PDIR_COUNTER": "na", - "PEBScounters": "0,1,2,3", - "SampleAfterValue": "1000003", - "UMask": "0x2" - }, - { - "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation.", - "Counter": "0,1,2,3", - "EventCode": "0x73", - "EventName": "TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS", - "PDIR_COUNTER": "na", - "PEBScounters": "0,1,2,3", - "SampleAfterValue": "1000003", - "UMask": "0x2" - }, - { - "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to branch mispredicts.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x73", - "EventName": "TOPDOWN_BAD_SPECULATION.MISPREDICT", - "PDIR_COUNTER": "na", - "PEBScounters": "0,1,2,3", - "SampleAfterValue": "1000003", - "UMask": "0x4" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event TOPDOWN_BAD_SPECULATION.FASTNUKE", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x73", - "EventName": "TOPDOWN_BAD_SPECULATION.MONUKE", - "PDIR_COUNTER": "na", - "PEBScounters": "0,1,2,3", - "SampleAfterValue": "1000003", - "UMask": "0x2" - }, - { - "BriefDescription": "Counts the total number of issue slots every cycle that were not consumed by the backend due to backend stalls.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x74", - "EventName": "TOPDOWN_BE_BOUND.ALL", - "PDIR_COUNTER": "na", - "PEBScounters": "0,1,2,3", - "SampleAfterValue": "1000003" - }, - { - "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to certain allocation restrictions.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x74", - "EventName": "TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS", - "PDIR_COUNTER": "na", - "PEBScounters": "0,1,2,3", - "SampleAfterValue": "1000003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to memory reservation stalls in which a scheduler is not able to accept uops.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x74", - "EventName": "TOPDOWN_BE_BOUND.MEM_SCHEDULER", - "PDIR_COUNTER": "na", - "PEBScounters": "0,1,2,3", - "SampleAfterValue": "1000003", - "UMask": "0x2" - }, - { - "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to IEC or FPC RAT stalls, which can be due to FIQ or IEC reservation stalls in which the integer, floating point or SIMD scheduler is not able to accept uops.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x74", - "EventName": "TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER", - "PDIR_COUNTER": "na", - "PEBScounters": "0,1,2,3", - "SampleAfterValue": "1000003", - "UMask": "0x8" - }, - { - "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to the physical register file unable to accept an entry (marble stalls).", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x74", - "EventName": "TOPDOWN_BE_BOUND.REGISTER", - "PDIR_COUNTER": "na", - "PEBScounters": "0,1,2,3", - "SampleAfterValue": "1000003", - "UMask": "0x20" - }, - { - "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to the reorder buffer being full (ROB stalls).", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x74", - "EventName": "TOPDOWN_BE_BOUND.REORDER_BUFFER", - "PDIR_COUNTER": "na", - "PEBScounters": "0,1,2,3", - "SampleAfterValue": "1000003", - "UMask": "0x40" - }, - { - "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to scoreboards from the instruction queue (IQ), jump execution unit (JEU), or microcode sequencer (MS).", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x74", - "EventName": "TOPDOWN_BE_BOUND.SERIALIZATION", - "PDIR_COUNTER": "na", - "PEBScounters": "0,1,2,3", - "SampleAfterValue": "1000003", - "UMask": "0x10" - }, - { - "BriefDescription": "This event is deprecated.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x74", - "EventName": "TOPDOWN_BE_BOUND.STORE_BUFFER", - "PDIR_COUNTER": "na", - "PEBScounters": "0,1,2,3", - "SampleAfterValue": "1000003", - "UMask": "0x4" - }, - { - "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to frontend stalls.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x71", - "EventName": "TOPDOWN_FE_BOUND.ALL", - "PDIR_COUNTER": "na", - "PEBScounters": "0,1,2,3", - "SampleAfterValue": "1000003" - }, - { - "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BACLEARS.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x71", - "EventName": "TOPDOWN_FE_BOUND.BRANCH_DETECT", - "PDIR_COUNTER": "na", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.", - "SampleAfterValue": "1000003", - "UMask": "0x2" - }, - { - "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BTCLEARS.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x71", - "EventName": "TOPDOWN_FE_BOUND.BRANCH_RESTEER", - "PDIR_COUNTER": "na", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BTCLEARS, which occurs when the Branch Target Buffer (BTB) predicts a taken branch.", - "SampleAfterValue": "1000003", - "UMask": "0x40" - }, - { - "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to the microcode sequencer (MS).", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x71", - "EventName": "TOPDOWN_FE_BOUND.CISC", - "PDIR_COUNTER": "na", - "PEBScounters": "0,1,2,3", - "SampleAfterValue": "1000003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to decode stalls.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x71", - "EventName": "TOPDOWN_FE_BOUND.DECODE", - "PDIR_COUNTER": "na", - "PEBScounters": "0,1,2,3", - "SampleAfterValue": "1000003", - "UMask": "0x8" - }, - { - "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to ITLB misses.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x71", - "EventName": "TOPDOWN_FE_BOUND.ITLB", - "PDIR_COUNTER": "na", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to Instruction Table Lookaside Buffer (ITLB) misses.", - "SampleAfterValue": "1000003", - "UMask": "0x10" - }, - { - "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to other common frontend stalls not categorized.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x71", - "EventName": "TOPDOWN_FE_BOUND.OTHER", - "PDIR_COUNTER": "na", - "PEBScounters": "0,1,2,3", - "SampleAfterValue": "1000003", - "UMask": "0x80" - }, - { - "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to wrong predecodes.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x71", - "EventName": "TOPDOWN_FE_BOUND.PREDECODE", - "PDIR_COUNTER": "na", - "PEBScounters": "0,1,2,3", - "SampleAfterValue": "1000003", - "UMask": "0x4" - }, - { - "BriefDescription": "Counts the total number of consumed retirement slots.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xc2", - "EventName": "TOPDOWN_RETIRING.ALL", - "PEBS": "1", - "PEBScounters": "0,1,2,3", - "SampleAfterValue": "1000003" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/elkhartlake/pipeline.json b/tools/perf/pmu-events/arch/x86/elkhartlake/pipeline.json index 41e5dfad8f51..31816c6543a8 100644 --- a/tools/perf/pmu-events/arch/x86/elkhartlake/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/elkhartlake/pipeline.json @@ -262,6 +262,247 @@ "PEBScounters": "0,1,2,3", "SampleAfterValue": "20003" }, + { + "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x73", + "EventName": "TOPDOWN_BAD_SPECULATION.ALL", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window including relevant microcode flows and while uops are not yet available in the instruction queue (IQ). Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear.", + "SampleAfterValue": "1000003", + "UMask": "0x6" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to fast nukes such as memory ordering and memory disambiguation machine clears.", + "Counter": "0,1,2,3", + "EventCode": "0x73", + "EventName": "TOPDOWN_BAD_SPECULATION.FASTNUKE", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation.", + "Counter": "0,1,2,3", + "EventCode": "0x73", + "EventName": "TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to branch mispredicts.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x73", + "EventName": "TOPDOWN_BAD_SPECULATION.MISPREDICT", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x4" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event TOPDOWN_BAD_SPECULATION.FASTNUKE", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x73", + "EventName": "TOPDOWN_BAD_SPECULATION.MONUKE", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts the total number of issue slots every cycle that were not consumed by the backend due to backend stalls.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x74", + "EventName": "TOPDOWN_BE_BOUND.ALL", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to certain allocation restrictions.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x74", + "EventName": "TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to memory reservation stalls in which a scheduler is not able to accept uops.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x74", + "EventName": "TOPDOWN_BE_BOUND.MEM_SCHEDULER", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to IEC or FPC RAT stalls, which can be due to FIQ or IEC reservation stalls in which the integer, floating point or SIMD scheduler is not able to accept uops.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x74", + "EventName": "TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to the physical register file unable to accept an entry (marble stalls).", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x74", + "EventName": "TOPDOWN_BE_BOUND.REGISTER", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x20" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to the reorder buffer being full (ROB stalls).", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x74", + "EventName": "TOPDOWN_BE_BOUND.REORDER_BUFFER", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x40" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to scoreboards from the instruction queue (IQ), jump execution unit (JEU), or microcode sequencer (MS).", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x74", + "EventName": "TOPDOWN_BE_BOUND.SERIALIZATION", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x10" + }, + { + "BriefDescription": "This event is deprecated.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x74", + "EventName": "TOPDOWN_BE_BOUND.STORE_BUFFER", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to frontend stalls.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x71", + "EventName": "TOPDOWN_FE_BOUND.ALL", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BACLEARS.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x71", + "EventName": "TOPDOWN_FE_BOUND.BRANCH_DETECT", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.", + "SampleAfterValue": "1000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BTCLEARS.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x71", + "EventName": "TOPDOWN_FE_BOUND.BRANCH_RESTEER", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BTCLEARS, which occurs when the Branch Target Buffer (BTB) predicts a taken branch.", + "SampleAfterValue": "1000003", + "UMask": "0x40" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to the microcode sequencer (MS).", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x71", + "EventName": "TOPDOWN_FE_BOUND.CISC", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to decode stalls.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x71", + "EventName": "TOPDOWN_FE_BOUND.DECODE", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to ITLB misses.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x71", + "EventName": "TOPDOWN_FE_BOUND.ITLB", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to Instruction Table Lookaside Buffer (ITLB) misses.", + "SampleAfterValue": "1000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to other common frontend stalls not categorized.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x71", + "EventName": "TOPDOWN_FE_BOUND.OTHER", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x80" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to wrong predecodes.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x71", + "EventName": "TOPDOWN_FE_BOUND.PREDECODE", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Counts the total number of consumed retirement slots.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xc2", + "EventName": "TOPDOWN_RETIRING.ALL", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003" + }, { "BriefDescription": "Counts the number of uops that are from complex flows issued by the micro-sequencer (MS).", "CollectPEBSRecord": "2", -- 2.35.1.894.gb6a874cedc-goog ^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PATCH 2/8] perf vendor events: Update events for Elkhartlake 2022-03-17 18:28 ` [PATCH 2/8] perf vendor events: Update events for Elkhartlake Ian Rogers @ 2022-03-18 9:12 ` Xing Zhengjun 0 siblings, 0 replies; 18+ messages in thread From: Xing Zhengjun @ 2022-03-18 9:12 UTC (permalink / raw) To: Ian Rogers, Kan Liang, Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo, Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim, Maxime Coquelin, Alexandre Torgue, Andi Kleen, James Clark, John Garry, linux-kernel, linux-perf-users Cc: Stephane Eranian On 3/18/2022 2:28 AM, Ian Rogers wrote: > The change: > https://github.com/intel/event-converter-for-linux-perf/commit/fc680410402e394eed6a1ebd909c9f649d3ed3ef > moved certain "other" type of events in to the pipeline topic. Update the > perf json files for this change. > > Signed-off-by: Ian Rogers <irogers@google.com> Reviewed-by: Zhengjun Xing <zhengjun.xing@linux.intel.com> > --- > .../arch/x86/elkhartlake/other.json | 241 ------------------ > .../arch/x86/elkhartlake/pipeline.json | 241 ++++++++++++++++++ > 2 files changed, 241 insertions(+), 241 deletions(-) > > diff --git a/tools/perf/pmu-events/arch/x86/elkhartlake/other.json b/tools/perf/pmu-events/arch/x86/elkhartlake/other.json > index 627691404155..de55b199ba79 100644 > --- a/tools/perf/pmu-events/arch/x86/elkhartlake/other.json > +++ b/tools/perf/pmu-events/arch/x86/elkhartlake/other.json > @@ -179,246 +179,5 @@ > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0x73", > - "EventName": "TOPDOWN_BAD_SPECULATION.ALL", > - "PDIR_COUNTER": "na", > - "PEBScounters": "0,1,2,3", > - "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window including relevant microcode flows and while uops are not yet available in the instruction queue (IQ). Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear.", > - "SampleAfterValue": "1000003", > - "UMask": "0x6" > - }, > - { > - "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to fast nukes such as memory ordering and memory disambiguation machine clears.", > - "Counter": "0,1,2,3", > - "EventCode": "0x73", > - "EventName": "TOPDOWN_BAD_SPECULATION.FASTNUKE", > - "PDIR_COUNTER": "na", > - "PEBScounters": "0,1,2,3", > - "SampleAfterValue": "1000003", > - "UMask": "0x2" > - }, > - { > - "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation.", > - "Counter": "0,1,2,3", > - "EventCode": "0x73", > - "EventName": "TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS", > - "PDIR_COUNTER": "na", > - "PEBScounters": "0,1,2,3", > - "SampleAfterValue": "1000003", > - "UMask": "0x2" > - }, > - { > - "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to branch mispredicts.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0x73", > - "EventName": "TOPDOWN_BAD_SPECULATION.MISPREDICT", > - "PDIR_COUNTER": "na", > - "PEBScounters": "0,1,2,3", > - "SampleAfterValue": "1000003", > - "UMask": "0x4" > - }, > - { > - "BriefDescription": "This event is deprecated. Refer to new event TOPDOWN_BAD_SPECULATION.FASTNUKE", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0x73", > - "EventName": "TOPDOWN_BAD_SPECULATION.MONUKE", > - "PDIR_COUNTER": "na", > - "PEBScounters": "0,1,2,3", > - "SampleAfterValue": "1000003", > - "UMask": "0x2" > - }, > - { > - "BriefDescription": "Counts the total number of issue slots every cycle that were not consumed by the backend due to backend stalls.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0x74", > - "EventName": "TOPDOWN_BE_BOUND.ALL", > - "PDIR_COUNTER": "na", > - "PEBScounters": "0,1,2,3", > - "SampleAfterValue": "1000003" > - }, > - { > - "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to certain allocation restrictions.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0x74", > - "EventName": "TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS", > - "PDIR_COUNTER": "na", > - "PEBScounters": "0,1,2,3", > - "SampleAfterValue": "1000003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to memory reservation stalls in which a scheduler is not able to accept uops.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0x74", > - "EventName": "TOPDOWN_BE_BOUND.MEM_SCHEDULER", > - "PDIR_COUNTER": "na", > - "PEBScounters": "0,1,2,3", > - "SampleAfterValue": "1000003", > - "UMask": "0x2" > - }, > - { > - "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to IEC or FPC RAT stalls, which can be due to FIQ or IEC reservation stalls in which the integer, floating point or SIMD scheduler is not able to accept uops.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0x74", > - "EventName": "TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER", > - "PDIR_COUNTER": "na", > - "PEBScounters": "0,1,2,3", > - "SampleAfterValue": "1000003", > - "UMask": "0x8" > - }, > - { > - "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to the physical register file unable to accept an entry (marble stalls).", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0x74", > - "EventName": "TOPDOWN_BE_BOUND.REGISTER", > - "PDIR_COUNTER": "na", > - "PEBScounters": "0,1,2,3", > - "SampleAfterValue": "1000003", > - "UMask": "0x20" > - }, > - { > - "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to the reorder buffer being full (ROB stalls).", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0x74", > - "EventName": "TOPDOWN_BE_BOUND.REORDER_BUFFER", > - "PDIR_COUNTER": "na", > - "PEBScounters": "0,1,2,3", > - "SampleAfterValue": "1000003", > - "UMask": "0x40" > - }, > - { > - "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to scoreboards from the instruction queue (IQ), jump execution unit (JEU), or microcode sequencer (MS).", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0x74", > - "EventName": "TOPDOWN_BE_BOUND.SERIALIZATION", > - "PDIR_COUNTER": "na", > - "PEBScounters": "0,1,2,3", > - "SampleAfterValue": "1000003", > - "UMask": "0x10" > - }, > - { > - "BriefDescription": "This event is deprecated.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0x74", > - "EventName": "TOPDOWN_BE_BOUND.STORE_BUFFER", > - "PDIR_COUNTER": "na", > - "PEBScounters": "0,1,2,3", > - "SampleAfterValue": "1000003", > - "UMask": "0x4" > - }, > - { > - "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to frontend stalls.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0x71", > - "EventName": "TOPDOWN_FE_BOUND.ALL", > - "PDIR_COUNTER": "na", > - "PEBScounters": "0,1,2,3", > - "SampleAfterValue": "1000003" > - }, > - { > - "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BACLEARS.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0x71", > - "EventName": "TOPDOWN_FE_BOUND.BRANCH_DETECT", > - "PDIR_COUNTER": "na", > - "PEBScounters": "0,1,2,3", > - "PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.", > - "SampleAfterValue": "1000003", > - "UMask": "0x2" > - }, > - { > - "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BTCLEARS.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0x71", > - "EventName": "TOPDOWN_FE_BOUND.BRANCH_RESTEER", > - "PDIR_COUNTER": "na", > - "PEBScounters": "0,1,2,3", > - "PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BTCLEARS, which occurs when the Branch Target Buffer (BTB) predicts a taken branch.", > - "SampleAfterValue": "1000003", > - "UMask": "0x40" > - }, > - { > - "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to the microcode sequencer (MS).", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0x71", > - "EventName": "TOPDOWN_FE_BOUND.CISC", > - "PDIR_COUNTER": "na", > - "PEBScounters": "0,1,2,3", > - "SampleAfterValue": "1000003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to decode stalls.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0x71", > - "EventName": "TOPDOWN_FE_BOUND.DECODE", > - "PDIR_COUNTER": "na", > - "PEBScounters": "0,1,2,3", > - "SampleAfterValue": "1000003", > - "UMask": "0x8" > - }, > - { > - "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to ITLB misses.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0x71", > - "EventName": "TOPDOWN_FE_BOUND.ITLB", > - "PDIR_COUNTER": "na", > - "PEBScounters": "0,1,2,3", > - "PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to Instruction Table Lookaside Buffer (ITLB) misses.", > - "SampleAfterValue": "1000003", > - "UMask": "0x10" > - }, > - { > - "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to other common frontend stalls not categorized.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0x71", > - "EventName": "TOPDOWN_FE_BOUND.OTHER", > - "PDIR_COUNTER": "na", > - "PEBScounters": "0,1,2,3", > - "SampleAfterValue": "1000003", > - "UMask": "0x80" > - }, > - { > - "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to wrong predecodes.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0x71", > - "EventName": "TOPDOWN_FE_BOUND.PREDECODE", > - "PDIR_COUNTER": "na", > - "PEBScounters": "0,1,2,3", > - "SampleAfterValue": "1000003", > - "UMask": "0x4" > - }, > - { > - "BriefDescription": "Counts the total number of consumed retirement slots.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0xc2", > - "EventName": "TOPDOWN_RETIRING.ALL", > - "PEBS": "1", > - "PEBScounters": "0,1,2,3", > - "SampleAfterValue": "1000003" > } > ] > \ No newline at end of file > diff --git a/tools/perf/pmu-events/arch/x86/elkhartlake/pipeline.json b/tools/perf/pmu-events/arch/x86/elkhartlake/pipeline.json > index 41e5dfad8f51..31816c6543a8 100644 > --- a/tools/perf/pmu-events/arch/x86/elkhartlake/pipeline.json > +++ b/tools/perf/pmu-events/arch/x86/elkhartlake/pipeline.json > @@ -262,6 +262,247 @@ > "PEBScounters": "0,1,2,3", > "SampleAfterValue": "20003" > }, > + { > + "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0x73", > + "EventName": "TOPDOWN_BAD_SPECULATION.ALL", > + "PDIR_COUNTER": "na", > + "PEBScounters": "0,1,2,3", > + "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window including relevant microcode flows and while uops are not yet available in the instruction queue (IQ). Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear.", > + "SampleAfterValue": "1000003", > + "UMask": "0x6" > + }, > + { > + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to fast nukes such as memory ordering and memory disambiguation machine clears.", > + "Counter": "0,1,2,3", > + "EventCode": "0x73", > + "EventName": "TOPDOWN_BAD_SPECULATION.FASTNUKE", > + "PDIR_COUNTER": "na", > + "PEBScounters": "0,1,2,3", > + "SampleAfterValue": "1000003", > + "UMask": "0x2" > + }, > + { > + "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation.", > + "Counter": "0,1,2,3", > + "EventCode": "0x73", > + "EventName": "TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS", > + "PDIR_COUNTER": "na", > + "PEBScounters": "0,1,2,3", > + "SampleAfterValue": "1000003", > + "UMask": "0x2" > + }, > + { > + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to branch mispredicts.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0x73", > + "EventName": "TOPDOWN_BAD_SPECULATION.MISPREDICT", > + "PDIR_COUNTER": "na", > + "PEBScounters": "0,1,2,3", > + "SampleAfterValue": "1000003", > + "UMask": "0x4" > + }, > + { > + "BriefDescription": "This event is deprecated. Refer to new event TOPDOWN_BAD_SPECULATION.FASTNUKE", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0x73", > + "EventName": "TOPDOWN_BAD_SPECULATION.MONUKE", > + "PDIR_COUNTER": "na", > + "PEBScounters": "0,1,2,3", > + "SampleAfterValue": "1000003", > + "UMask": "0x2" > + }, > + { > + "BriefDescription": "Counts the total number of issue slots every cycle that were not consumed by the backend due to backend stalls.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0x74", > + "EventName": "TOPDOWN_BE_BOUND.ALL", > + "PDIR_COUNTER": "na", > + "PEBScounters": "0,1,2,3", > + "SampleAfterValue": "1000003" > + }, > + { > + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to certain allocation restrictions.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0x74", > + "EventName": "TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS", > + "PDIR_COUNTER": "na", > + "PEBScounters": "0,1,2,3", > + "SampleAfterValue": "1000003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to memory reservation stalls in which a scheduler is not able to accept uops.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0x74", > + "EventName": "TOPDOWN_BE_BOUND.MEM_SCHEDULER", > + "PDIR_COUNTER": "na", > + "PEBScounters": "0,1,2,3", > + "SampleAfterValue": "1000003", > + "UMask": "0x2" > + }, > + { > + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to IEC or FPC RAT stalls, which can be due to FIQ or IEC reservation stalls in which the integer, floating point or SIMD scheduler is not able to accept uops.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0x74", > + "EventName": "TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER", > + "PDIR_COUNTER": "na", > + "PEBScounters": "0,1,2,3", > + "SampleAfterValue": "1000003", > + "UMask": "0x8" > + }, > + { > + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to the physical register file unable to accept an entry (marble stalls).", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0x74", > + "EventName": "TOPDOWN_BE_BOUND.REGISTER", > + "PDIR_COUNTER": "na", > + "PEBScounters": "0,1,2,3", > + "SampleAfterValue": "1000003", > + "UMask": "0x20" > + }, > + { > + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to the reorder buffer being full (ROB stalls).", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0x74", > + "EventName": "TOPDOWN_BE_BOUND.REORDER_BUFFER", > + "PDIR_COUNTER": "na", > + "PEBScounters": "0,1,2,3", > + "SampleAfterValue": "1000003", > + "UMask": "0x40" > + }, > + { > + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to scoreboards from the instruction queue (IQ), jump execution unit (JEU), or microcode sequencer (MS).", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0x74", > + "EventName": "TOPDOWN_BE_BOUND.SERIALIZATION", > + "PDIR_COUNTER": "na", > + "PEBScounters": "0,1,2,3", > + "SampleAfterValue": "1000003", > + "UMask": "0x10" > + }, > + { > + "BriefDescription": "This event is deprecated.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0x74", > + "EventName": "TOPDOWN_BE_BOUND.STORE_BUFFER", > + "PDIR_COUNTER": "na", > + "PEBScounters": "0,1,2,3", > + "SampleAfterValue": "1000003", > + "UMask": "0x4" > + }, > + { > + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to frontend stalls.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0x71", > + "EventName": "TOPDOWN_FE_BOUND.ALL", > + "PDIR_COUNTER": "na", > + "PEBScounters": "0,1,2,3", > + "SampleAfterValue": "1000003" > + }, > + { > + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BACLEARS.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0x71", > + "EventName": "TOPDOWN_FE_BOUND.BRANCH_DETECT", > + "PDIR_COUNTER": "na", > + "PEBScounters": "0,1,2,3", > + "PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.", > + "SampleAfterValue": "1000003", > + "UMask": "0x2" > + }, > + { > + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BTCLEARS.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0x71", > + "EventName": "TOPDOWN_FE_BOUND.BRANCH_RESTEER", > + "PDIR_COUNTER": "na", > + "PEBScounters": "0,1,2,3", > + "PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BTCLEARS, which occurs when the Branch Target Buffer (BTB) predicts a taken branch.", > + "SampleAfterValue": "1000003", > + "UMask": "0x40" > + }, > + { > + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to the microcode sequencer (MS).", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0x71", > + "EventName": "TOPDOWN_FE_BOUND.CISC", > + "PDIR_COUNTER": "na", > + "PEBScounters": "0,1,2,3", > + "SampleAfterValue": "1000003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to decode stalls.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0x71", > + "EventName": "TOPDOWN_FE_BOUND.DECODE", > + "PDIR_COUNTER": "na", > + "PEBScounters": "0,1,2,3", > + "SampleAfterValue": "1000003", > + "UMask": "0x8" > + }, > + { > + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to ITLB misses.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0x71", > + "EventName": "TOPDOWN_FE_BOUND.ITLB", > + "PDIR_COUNTER": "na", > + "PEBScounters": "0,1,2,3", > + "PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to Instruction Table Lookaside Buffer (ITLB) misses.", > + "SampleAfterValue": "1000003", > + "UMask": "0x10" > + }, > + { > + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to other common frontend stalls not categorized.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0x71", > + "EventName": "TOPDOWN_FE_BOUND.OTHER", > + "PDIR_COUNTER": "na", > + "PEBScounters": "0,1,2,3", > + "SampleAfterValue": "1000003", > + "UMask": "0x80" > + }, > + { > + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to wrong predecodes.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0x71", > + "EventName": "TOPDOWN_FE_BOUND.PREDECODE", > + "PDIR_COUNTER": "na", > + "PEBScounters": "0,1,2,3", > + "SampleAfterValue": "1000003", > + "UMask": "0x4" > + }, > + { > + "BriefDescription": "Counts the total number of consumed retirement slots.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0xc2", > + "EventName": "TOPDOWN_RETIRING.ALL", > + "PEBS": "1", > + "PEBScounters": "0,1,2,3", > + "SampleAfterValue": "1000003" > + }, > { > "BriefDescription": "Counts the number of uops that are from complex flows issued by the micro-sequencer (MS).", > "CollectPEBSRecord": "2", -- Zhengjun Xing ^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 3/8] perf vendor events: Update events for Icelake 2022-03-17 18:28 [PATCH 1/8] perf vendor events: Update events for CascadelakeX Ian Rogers 2022-03-17 18:28 ` [PATCH 2/8] perf vendor events: Update events for Elkhartlake Ian Rogers @ 2022-03-17 18:28 ` Ian Rogers 2022-03-18 9:15 ` Xing Zhengjun 2022-03-17 18:28 ` [PATCH 4/8] perf vendor events: Update events for IcelakeX Ian Rogers ` (6 subsequent siblings) 8 siblings, 1 reply; 18+ messages in thread From: Ian Rogers @ 2022-03-17 18:28 UTC (permalink / raw) To: Kan Liang, Zhengjun Xing, Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo, Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim, Maxime Coquelin, Alexandre Torgue, Andi Kleen, James Clark, John Garry, linux-kernel, linux-perf-users Cc: Stephane Eranian, Ian Rogers The change: https://github.com/intel/event-converter-for-linux-perf/commit/fc680410402e394eed6a1ebd909c9f649d3ed3ef moved certain "other" type of events in to the cache and pipeline topic. Update the perf json files for this change. Signed-off-by: Ian Rogers <irogers@google.com> --- .../pmu-events/arch/x86/icelake/cache.json | 633 +++++++++++++++ .../pmu-events/arch/x86/icelake/other.json | 752 +----------------- .../pmu-events/arch/x86/icelake/pipeline.json | 47 ++ 3 files changed, 716 insertions(+), 716 deletions(-) diff --git a/tools/perf/pmu-events/arch/x86/icelake/cache.json b/tools/perf/pmu-events/arch/x86/icelake/cache.json index 96dcd387c70e..375ce490833c 100644 --- a/tools/perf/pmu-events/arch/x86/icelake/cache.json +++ b/tools/perf/pmu-events/arch/x86/icelake/cache.json @@ -553,6 +553,591 @@ "SampleAfterValue": "50021", "UMask": "0x20" }, + { + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was sent or not.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.ANY", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FC03C0004", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0004", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003C0004", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003C0004", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003C0004", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was sent.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_SENT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1E003C0004", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop was sent or not.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.ANY", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FC03C0001", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0001", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003C0001", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003C0001", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003C0001", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop was sent.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_SENT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1E003C0001", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was sent or not.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_RFO.L3_HIT.ANY", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FC03C0002", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0002", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003C0002", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003C0002", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003C0002", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was sent.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_SENT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1E003C0002", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit a cacheline in the L3 where a snoop was sent or not.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT.ANY", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FC03C0400", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003C0400", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003C0400", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent or not.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.ANY", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FC03C0010", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0010", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003C0010", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003C0010", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003C0010", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_SENT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1E003C0010", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent or not.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.HWPF_L2_RFO.L3_HIT.ANY", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FC03C0020", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0020", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003C0020", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003C0020", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003C0020", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_SENT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1E003C0020", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts hardware prefetches to the L3 only that hit a cacheline in the L3 where a snoop was sent or not.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.HWPF_L3.L3_HIT.ANY", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FC03C2380", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.OTHER.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003C8000", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.OTHER.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003C8000", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.OTHER.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003C8000", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop was sent.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.OTHER.L3_HIT.SNOOP_SENT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1E003C8000", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts streaming stores that hit a cacheline in the L3 where a snoop was sent or not.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.STREAMING_WR.L3_HIT.ANY", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FC03C0800", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, { "BriefDescription": "Demand and prefetch data reads", "CollectPEBSRecord": "2", @@ -674,5 +1259,53 @@ "SampleAfterValue": "100003", "Speculative": "1", "UMask": "0x4" + }, + { + "BriefDescription": "Number of PREFETCHNTA instructions executed.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "SW_PREFETCH_ACCESS.NTA", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of PREFETCHNTA instructions executed.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of PREFETCHW instructions executed.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "SW_PREFETCH_ACCESS.PREFETCHW", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of PREFETCHW instructions executed.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x8" + }, + { + "BriefDescription": "Number of PREFETCHT0 instructions executed.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "SW_PREFETCH_ACCESS.T0", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of PREFETCHT0 instructions executed.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x2" + }, + { + "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "SW_PREFETCH_ACCESS.T1_T2", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of PREFETCHT1 or PREFETCHT2 instructions executed.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x4" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/icelake/other.json b/tools/perf/pmu-events/arch/x86/icelake/other.json index 10e8582774ce..08f6321025e8 100644 --- a/tools/perf/pmu-events/arch/x86/icelake/other.json +++ b/tools/perf/pmu-events/arch/x86/icelake/other.json @@ -78,418 +78,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was sent or not.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.ANY", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FC03C0004", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x10003C0004", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x4003C0004", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x2003C0004", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1003C0004", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was sent.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_SENT", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1E003C0004", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that DRAM supplied the request.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_CODE_RD.LOCAL_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x184000004", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads that have any type of response.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x10001", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads that DRAM supplied the request.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_DATA_RD.DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x184000001", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop was sent or not.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.ANY", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FC03C0001", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x10003C0001", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x4003C0001", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x2003C0001", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1003C0001", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop was sent.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_SENT", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1E003C0001", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads that DRAM supplied the request.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_DATA_RD.LOCAL_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x184000001", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x10002", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that DRAM supplied the request.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_RFO.DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x184000002", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was sent or not.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_RFO.L3_HIT.ANY", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FC03C0002", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x10003C0002", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x4003C0002", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x2003C0002", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1003C0002", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was sent.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_SENT", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1E003C0002", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that DRAM supplied the request.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_RFO.LOCAL_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x184000002", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that have any type of response.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L1D_AND_SWPF.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x10400", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that DRAM supplied the request.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L1D_AND_SWPF.DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x184000400", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit a cacheline in the L3 where a snoop was sent or not.", + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that DRAM supplied the request.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT.ANY", + "EventName": "OCR.DEMAND_CODE_RD.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FC03C0400", + "MSRValue": "0x184000004", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", @@ -498,13 +93,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.", + "BriefDescription": "Counts demand data reads that have any type of response.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT.SNOOP_MISS", + "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x2003C0400", + "MSRValue": "0x10001", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", @@ -513,13 +108,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.", + "BriefDescription": "Counts demand data reads that DRAM supplied the request.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT.SNOOP_NOT_NEEDED", + "EventName": "OCR.DEMAND_DATA_RD.DRAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1003C0400", + "MSRValue": "0x184000001", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", @@ -528,13 +123,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that DRAM supplied the request.", + "BriefDescription": "Counts demand data reads that DRAM supplied the request.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L1D_AND_SWPF.LOCAL_DRAM", + "EventName": "OCR.DEMAND_DATA_RD.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x184000400", + "MSRValue": "0x184000001", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", @@ -543,13 +138,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that have any type of response.", + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L2_DATA_RD.ANY_RESPONSE", + "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x10010", + "MSRValue": "0x10002", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", @@ -558,13 +153,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that DRAM supplied the request.", + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that DRAM supplied the request.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L2_DATA_RD.DRAM", + "EventName": "OCR.DEMAND_RFO.DRAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x184000010", + "MSRValue": "0x184000002", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", @@ -573,13 +168,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent or not.", + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that DRAM supplied the request.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.ANY", + "EventName": "OCR.DEMAND_RFO.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FC03C0010", + "MSRValue": "0x184000002", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", @@ -588,13 +183,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.", + "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that have any type of response.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HITM", + "EventName": "OCR.HWPF_L1D_AND_SWPF.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x10003C0010", + "MSRValue": "0x10400", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", @@ -603,13 +198,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.", + "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that DRAM supplied the request.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", + "EventName": "OCR.HWPF_L1D_AND_SWPF.DRAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x4003C0010", + "MSRValue": "0x184000400", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", @@ -618,13 +213,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.", + "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that DRAM supplied the request.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_MISS", + "EventName": "OCR.HWPF_L1D_AND_SWPF.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x2003C0010", + "MSRValue": "0x184000400", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", @@ -633,13 +228,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.", + "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that have any type of response.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED", + "EventName": "OCR.HWPF_L2_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1003C0010", + "MSRValue": "0x10010", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", @@ -648,13 +243,13 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent.", + "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that DRAM supplied the request.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_SENT", + "EventName": "OCR.HWPF_L2_DATA_RD.DRAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1E003C0010", + "MSRValue": "0x184000010", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", @@ -707,96 +302,6 @@ "Speculative": "1", "UMask": "0x1" }, - { - "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent or not.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L2_RFO.L3_HIT.ANY", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FC03C0020", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HITM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x10003C0020", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x4003C0020", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x2003C0020", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1003C0020", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_SENT", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1E003C0020", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, { "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that DRAM supplied the request.", "CollectPEBSRecord": "2", @@ -812,21 +317,6 @@ "Speculative": "1", "UMask": "0x1" }, - { - "BriefDescription": "Counts hardware prefetches to the L3 only that hit a cacheline in the L3 where a snoop was sent or not.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L3.L3_HIT.ANY", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FC03C2380", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, { "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that have any type of response.", "CollectPEBSRecord": "2", @@ -857,66 +347,6 @@ "Speculative": "1", "UMask": "0x1" }, - { - "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.OTHER.L3_HIT.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x4003C8000", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.OTHER.L3_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x2003C8000", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.OTHER.L3_HIT.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1003C8000", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop was sent.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.OTHER.L3_HIT.SNOOP_SENT", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1E003C8000", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, { "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that DRAM supplied the request.", "CollectPEBSRecord": "2", @@ -962,21 +392,6 @@ "Speculative": "1", "UMask": "0x1" }, - { - "BriefDescription": "Counts streaming stores that hit a cacheline in the L3 where a snoop was sent or not.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.STREAMING_WR.L3_HIT.ANY", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FC03C0800", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, { "BriefDescription": "Counts streaming stores that DRAM supplied the request.", "CollectPEBSRecord": "2", @@ -991,100 +406,5 @@ "SampleAfterValue": "100003", "Speculative": "1", "UMask": "0x1" - }, - { - "BriefDescription": "Number of PREFETCHNTA instructions executed.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x32", - "EventName": "SW_PREFETCH_ACCESS.NTA", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of PREFETCHNTA instructions executed.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Number of PREFETCHW instructions executed.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x32", - "EventName": "SW_PREFETCH_ACCESS.PREFETCHW", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of PREFETCHW instructions executed.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x8" - }, - { - "BriefDescription": "Number of PREFETCHT0 instructions executed.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x32", - "EventName": "SW_PREFETCH_ACCESS.T0", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of PREFETCHT0 instructions executed.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x2" - }, - { - "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x32", - "EventName": "SW_PREFETCH_ACCESS.T1_T2", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of PREFETCHT1 or PREFETCHT2 instructions executed.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x4" - }, - { - "BriefDescription": "TMA slots where no uops were being issued due to lack of back-end resources.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xa4", - "EventName": "TOPDOWN.BACKEND_BOUND_SLOTS", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of Top-down Microarchitecture Analysis (TMA) method's slots where no micro-operations were being issued from front-end to back-end of the machine due to lack of back-end resources.", - "SampleAfterValue": "10000003", - "Speculative": "1", - "UMask": "0x2" - }, - { - "BriefDescription": "TMA slots wasted due to incorrect speculation by branch mispredictions", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xa4", - "EventName": "TOPDOWN.BR_MISPREDICT_SLOTS", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Number of TMA slots that were wasted due to incorrect speculation by branch mispredictions. This event estimates number of operations that were issued but not retired from the specualtive path as well as the out-of-order engine recovery past a branch misprediction.", - "SampleAfterValue": "10000003", - "Speculative": "1", - "UMask": "0x8" - }, - { - "BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - architectural event", - "CollectPEBSRecord": "2", - "Counter": "Fixed counter 3", - "EventName": "TOPDOWN.SLOTS", - "PEBScounters": "35", - "PublicDescription": "Number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TMA). The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core. Software can use this event as the denominator for the top-level metrics of the TMA method. This architectural event is counted on a designated fixed counter (Fixed Counter 3).", - "SampleAfterValue": "10000003", - "Speculative": "1", - "UMask": "0x4" - }, - { - "BriefDescription": "TMA slots available for an unhalted logical processor. General counter - architectural event", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xa4", - "EventName": "TOPDOWN.SLOTS_P", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core.", - "SampleAfterValue": "10000003", - "Speculative": "1", - "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/icelake/pipeline.json b/tools/perf/pmu-events/arch/x86/icelake/pipeline.json index 2b305bdc8cfc..573ac7ac8879 100644 --- a/tools/perf/pmu-events/arch/x86/icelake/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/icelake/pipeline.json @@ -730,6 +730,53 @@ "Speculative": "1", "UMask": "0x1" }, + { + "BriefDescription": "TMA slots where no uops were being issued due to lack of back-end resources.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xa4", + "EventName": "TOPDOWN.BACKEND_BOUND_SLOTS", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts the number of Top-down Microarchitecture Analysis (TMA) method's slots where no micro-operations were being issued from front-end to back-end of the machine due to lack of back-end resources.", + "SampleAfterValue": "10000003", + "Speculative": "1", + "UMask": "0x2" + }, + { + "BriefDescription": "TMA slots wasted due to incorrect speculation by branch mispredictions", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xa4", + "EventName": "TOPDOWN.BR_MISPREDICT_SLOTS", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Number of TMA slots that were wasted due to incorrect speculation by branch mispredictions. This event estimates number of operations that were issued but not retired from the specualtive path as well as the out-of-order engine recovery past a branch misprediction.", + "SampleAfterValue": "10000003", + "Speculative": "1", + "UMask": "0x8" + }, + { + "BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - architectural event", + "CollectPEBSRecord": "2", + "Counter": "Fixed counter 3", + "EventName": "TOPDOWN.SLOTS", + "PEBScounters": "35", + "PublicDescription": "Number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TMA). The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core. Software can use this event as the denominator for the top-level metrics of the TMA method. This architectural event is counted on a designated fixed counter (Fixed Counter 3).", + "SampleAfterValue": "10000003", + "Speculative": "1", + "UMask": "0x4" + }, + { + "BriefDescription": "TMA slots available for an unhalted logical processor. General counter - architectural event", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xa4", + "EventName": "TOPDOWN.SLOTS_P", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core.", + "SampleAfterValue": "10000003", + "Speculative": "1", + "UMask": "0x1" + }, { "BriefDescription": "Number of uops decoded out of instructions exclusively fetched by decoder 0", "CollectPEBSRecord": "2", -- 2.35.1.894.gb6a874cedc-goog ^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PATCH 3/8] perf vendor events: Update events for Icelake 2022-03-17 18:28 ` [PATCH 3/8] perf vendor events: Update events for Icelake Ian Rogers @ 2022-03-18 9:15 ` Xing Zhengjun 0 siblings, 0 replies; 18+ messages in thread From: Xing Zhengjun @ 2022-03-18 9:15 UTC (permalink / raw) To: Ian Rogers, Kan Liang, Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo, Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim, Maxime Coquelin, Alexandre Torgue, Andi Kleen, James Clark, John Garry, linux-kernel, linux-perf-users Cc: Stephane Eranian On 3/18/2022 2:28 AM, Ian Rogers wrote: > The change: > https://github.com/intel/event-converter-for-linux-perf/commit/fc680410402e394eed6a1ebd909c9f649d3ed3ef > moved certain "other" type of events in to the cache and pipeline topic. > Update the perf json files for this change. > > Signed-off-by: Ian Rogers <irogers@google.com> Reviewed-by: Zhengjun Xing <zhengjun.xing@linux.intel.com> > --- > .../pmu-events/arch/x86/icelake/cache.json | 633 +++++++++++++++ > .../pmu-events/arch/x86/icelake/other.json | 752 +----------------- > .../pmu-events/arch/x86/icelake/pipeline.json | 47 ++ > 3 files changed, 716 insertions(+), 716 deletions(-) > > diff --git a/tools/perf/pmu-events/arch/x86/icelake/cache.json b/tools/perf/pmu-events/arch/x86/icelake/cache.json > index 96dcd387c70e..375ce490833c 100644 > --- a/tools/perf/pmu-events/arch/x86/icelake/cache.json > +++ b/tools/perf/pmu-events/arch/x86/icelake/cache.json > @@ -553,6 +553,591 @@ > "SampleAfterValue": "50021", > "UMask": "0x20" > }, > + { > + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was sent or not.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.ANY", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3FC03C0004", > + "Offcore": "1", > + "PEBScounters": "0,1,2,3", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "Speculative": "1", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x10003C0004", > + "Offcore": "1", > + "PEBScounters": "0,1,2,3", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "Speculative": "1", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x4003C0004", > + "Offcore": "1", > + "PEBScounters": "0,1,2,3", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "Speculative": "1", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x2003C0004", > + "Offcore": "1", > + "PEBScounters": "0,1,2,3", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "Speculative": "1", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1003C0004", > + "Offcore": "1", > + "PEBScounters": "0,1,2,3", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "Speculative": "1", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was sent.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_SENT", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1E003C0004", > + "Offcore": "1", > + "PEBScounters": "0,1,2,3", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "Speculative": "1", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop was sent or not.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.ANY", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3FC03C0001", > + "Offcore": "1", > + "PEBScounters": "0,1,2,3", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "Speculative": "1", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x10003C0001", > + "Offcore": "1", > + "PEBScounters": "0,1,2,3", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "Speculative": "1", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x4003C0001", > + "Offcore": "1", > + "PEBScounters": "0,1,2,3", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "Speculative": "1", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x2003C0001", > + "Offcore": "1", > + "PEBScounters": "0,1,2,3", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "Speculative": "1", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1003C0001", > + "Offcore": "1", > + "PEBScounters": "0,1,2,3", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "Speculative": "1", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop was sent.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_SENT", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1E003C0001", > + "Offcore": "1", > + "PEBScounters": "0,1,2,3", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "Speculative": "1", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was sent or not.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_RFO.L3_HIT.ANY", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3FC03C0002", > + "Offcore": "1", > + "PEBScounters": "0,1,2,3", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "Speculative": "1", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x10003C0002", > + "Offcore": "1", > + "PEBScounters": "0,1,2,3", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "Speculative": "1", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x4003C0002", > + "Offcore": "1", > + "PEBScounters": "0,1,2,3", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "Speculative": "1", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x2003C0002", > + "Offcore": "1", > + "PEBScounters": "0,1,2,3", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "Speculative": "1", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_NOT_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1003C0002", > + "Offcore": "1", > + "PEBScounters": "0,1,2,3", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "Speculative": "1", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was sent.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_SENT", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1E003C0002", > + "Offcore": "1", > + "PEBScounters": "0,1,2,3", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "Speculative": "1", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit a cacheline in the L3 where a snoop was sent or not.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT.ANY", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3FC03C0400", > + "Offcore": "1", > + "PEBScounters": "0,1,2,3", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "Speculative": "1", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x2003C0400", > + "Offcore": "1", > + "PEBScounters": "0,1,2,3", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "Speculative": "1", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT.SNOOP_NOT_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1003C0400", > + "Offcore": "1", > + "PEBScounters": "0,1,2,3", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "Speculative": "1", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent or not.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.ANY", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3FC03C0010", > + "Offcore": "1", > + "PEBScounters": "0,1,2,3", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "Speculative": "1", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HITM", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x10003C0010", > + "Offcore": "1", > + "PEBScounters": "0,1,2,3", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "Speculative": "1", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x4003C0010", > + "Offcore": "1", > + "PEBScounters": "0,1,2,3", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "Speculative": "1", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x2003C0010", > + "Offcore": "1", > + "PEBScounters": "0,1,2,3", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "Speculative": "1", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1003C0010", > + "Offcore": "1", > + "PEBScounters": "0,1,2,3", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "Speculative": "1", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_SENT", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1E003C0010", > + "Offcore": "1", > + "PEBScounters": "0,1,2,3", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "Speculative": "1", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent or not.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.HWPF_L2_RFO.L3_HIT.ANY", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3FC03C0020", > + "Offcore": "1", > + "PEBScounters": "0,1,2,3", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "Speculative": "1", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HITM", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x10003C0020", > + "Offcore": "1", > + "PEBScounters": "0,1,2,3", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "Speculative": "1", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HIT_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x4003C0020", > + "Offcore": "1", > + "PEBScounters": "0,1,2,3", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "Speculative": "1", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x2003C0020", > + "Offcore": "1", > + "PEBScounters": "0,1,2,3", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "Speculative": "1", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_NOT_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1003C0020", > + "Offcore": "1", > + "PEBScounters": "0,1,2,3", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "Speculative": "1", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_SENT", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1E003C0020", > + "Offcore": "1", > + "PEBScounters": "0,1,2,3", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "Speculative": "1", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts hardware prefetches to the L3 only that hit a cacheline in the L3 where a snoop was sent or not.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.HWPF_L3.L3_HIT.ANY", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3FC03C2380", > + "Offcore": "1", > + "PEBScounters": "0,1,2,3", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "Speculative": "1", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.OTHER.L3_HIT.SNOOP_HIT_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x4003C8000", > + "Offcore": "1", > + "PEBScounters": "0,1,2,3", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "Speculative": "1", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.OTHER.L3_HIT.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x2003C8000", > + "Offcore": "1", > + "PEBScounters": "0,1,2,3", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "Speculative": "1", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.OTHER.L3_HIT.SNOOP_NOT_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1003C8000", > + "Offcore": "1", > + "PEBScounters": "0,1,2,3", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "Speculative": "1", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop was sent.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.OTHER.L3_HIT.SNOOP_SENT", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1E003C8000", > + "Offcore": "1", > + "PEBScounters": "0,1,2,3", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "Speculative": "1", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts streaming stores that hit a cacheline in the L3 where a snoop was sent or not.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.STREAMING_WR.L3_HIT.ANY", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3FC03C0800", > + "Offcore": "1", > + "PEBScounters": "0,1,2,3", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "Speculative": "1", > + "UMask": "0x1" > + }, > { > "BriefDescription": "Demand and prefetch data reads", > "CollectPEBSRecord": "2", > @@ -674,5 +1259,53 @@ > "SampleAfterValue": "100003", > "Speculative": "1", > "UMask": "0x4" > + }, > + { > + "BriefDescription": "Number of PREFETCHNTA instructions executed.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0x32", > + "EventName": "SW_PREFETCH_ACCESS.NTA", > + "PEBScounters": "0,1,2,3", > + "PublicDescription": "Counts the number of PREFETCHNTA instructions executed.", > + "SampleAfterValue": "100003", > + "Speculative": "1", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Number of PREFETCHW instructions executed.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0x32", > + "EventName": "SW_PREFETCH_ACCESS.PREFETCHW", > + "PEBScounters": "0,1,2,3", > + "PublicDescription": "Counts the number of PREFETCHW instructions executed.", > + "SampleAfterValue": "100003", > + "Speculative": "1", > + "UMask": "0x8" > + }, > + { > + "BriefDescription": "Number of PREFETCHT0 instructions executed.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0x32", > + "EventName": "SW_PREFETCH_ACCESS.T0", > + "PEBScounters": "0,1,2,3", > + "PublicDescription": "Counts the number of PREFETCHT0 instructions executed.", > + "SampleAfterValue": "100003", > + "Speculative": "1", > + "UMask": "0x2" > + }, > + { > + "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0x32", > + "EventName": "SW_PREFETCH_ACCESS.T1_T2", > + "PEBScounters": "0,1,2,3", > + "PublicDescription": "Counts the number of PREFETCHT1 or PREFETCHT2 instructions executed.", > + "SampleAfterValue": "100003", > + "Speculative": "1", > + "UMask": "0x4" > } > ] > \ No newline at end of file > diff --git a/tools/perf/pmu-events/arch/x86/icelake/other.json b/tools/perf/pmu-events/arch/x86/icelake/other.json > index 10e8582774ce..08f6321025e8 100644 > --- a/tools/perf/pmu-events/arch/x86/icelake/other.json > +++ b/tools/perf/pmu-events/arch/x86/icelake/other.json > @@ -78,418 +78,13 @@ > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was sent or not.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.ANY", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3FC03C0004", > - "Offcore": "1", > - "PEBScounters": "0,1,2,3", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "Speculative": "1", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10003C0004", > - "Offcore": "1", > - "PEBScounters": "0,1,2,3", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "Speculative": "1", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x4003C0004", > - "Offcore": "1", > - "PEBScounters": "0,1,2,3", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "Speculative": "1", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x2003C0004", > - "Offcore": "1", > - "PEBScounters": "0,1,2,3", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "Speculative": "1", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1003C0004", > - "Offcore": "1", > - "PEBScounters": "0,1,2,3", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "Speculative": "1", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was sent.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_SENT", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1E003C0004", > - "Offcore": "1", > - "PEBScounters": "0,1,2,3", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "Speculative": "1", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that DRAM supplied the request.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.LOCAL_DRAM", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x184000004", > - "Offcore": "1", > - "PEBScounters": "0,1,2,3", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "Speculative": "1", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads that have any type of response.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10001", > - "Offcore": "1", > - "PEBScounters": "0,1,2,3", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "Speculative": "1", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads that DRAM supplied the request.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.DRAM", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x184000001", > - "Offcore": "1", > - "PEBScounters": "0,1,2,3", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "Speculative": "1", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop was sent or not.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.ANY", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3FC03C0001", > - "Offcore": "1", > - "PEBScounters": "0,1,2,3", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "Speculative": "1", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10003C0001", > - "Offcore": "1", > - "PEBScounters": "0,1,2,3", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "Speculative": "1", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x4003C0001", > - "Offcore": "1", > - "PEBScounters": "0,1,2,3", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "Speculative": "1", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x2003C0001", > - "Offcore": "1", > - "PEBScounters": "0,1,2,3", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "Speculative": "1", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1003C0001", > - "Offcore": "1", > - "PEBScounters": "0,1,2,3", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "Speculative": "1", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop was sent.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_SENT", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1E003C0001", > - "Offcore": "1", > - "PEBScounters": "0,1,2,3", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "Speculative": "1", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads that DRAM supplied the request.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.LOCAL_DRAM", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x184000001", > - "Offcore": "1", > - "PEBScounters": "0,1,2,3", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "Speculative": "1", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10002", > - "Offcore": "1", > - "PEBScounters": "0,1,2,3", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "Speculative": "1", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that DRAM supplied the request.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.DRAM", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x184000002", > - "Offcore": "1", > - "PEBScounters": "0,1,2,3", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "Speculative": "1", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was sent or not.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.L3_HIT.ANY", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3FC03C0002", > - "Offcore": "1", > - "PEBScounters": "0,1,2,3", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "Speculative": "1", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10003C0002", > - "Offcore": "1", > - "PEBScounters": "0,1,2,3", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "Speculative": "1", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x4003C0002", > - "Offcore": "1", > - "PEBScounters": "0,1,2,3", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "Speculative": "1", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x2003C0002", > - "Offcore": "1", > - "PEBScounters": "0,1,2,3", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "Speculative": "1", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_NOT_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1003C0002", > - "Offcore": "1", > - "PEBScounters": "0,1,2,3", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "Speculative": "1", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was sent.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_SENT", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1E003C0002", > - "Offcore": "1", > - "PEBScounters": "0,1,2,3", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "Speculative": "1", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that DRAM supplied the request.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.LOCAL_DRAM", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x184000002", > - "Offcore": "1", > - "PEBScounters": "0,1,2,3", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "Speculative": "1", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that have any type of response.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.HWPF_L1D_AND_SWPF.ANY_RESPONSE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10400", > - "Offcore": "1", > - "PEBScounters": "0,1,2,3", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "Speculative": "1", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that DRAM supplied the request.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.HWPF_L1D_AND_SWPF.DRAM", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x184000400", > - "Offcore": "1", > - "PEBScounters": "0,1,2,3", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "Speculative": "1", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit a cacheline in the L3 where a snoop was sent or not.", > + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that DRAM supplied the request.", > "CollectPEBSRecord": "2", > "Counter": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT.ANY", > + "EventName": "OCR.DEMAND_CODE_RD.LOCAL_DRAM", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3FC03C0400", > + "MSRValue": "0x184000004", > "Offcore": "1", > "PEBScounters": "0,1,2,3", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > @@ -498,13 +93,13 @@ > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.", > + "BriefDescription": "Counts demand data reads that have any type of response.", > "CollectPEBSRecord": "2", > "Counter": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT.SNOOP_MISS", > + "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x2003C0400", > + "MSRValue": "0x10001", > "Offcore": "1", > "PEBScounters": "0,1,2,3", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > @@ -513,13 +108,13 @@ > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.", > + "BriefDescription": "Counts demand data reads that DRAM supplied the request.", > "CollectPEBSRecord": "2", > "Counter": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT.SNOOP_NOT_NEEDED", > + "EventName": "OCR.DEMAND_DATA_RD.DRAM", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1003C0400", > + "MSRValue": "0x184000001", > "Offcore": "1", > "PEBScounters": "0,1,2,3", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > @@ -528,13 +123,13 @@ > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that DRAM supplied the request.", > + "BriefDescription": "Counts demand data reads that DRAM supplied the request.", > "CollectPEBSRecord": "2", > "Counter": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.HWPF_L1D_AND_SWPF.LOCAL_DRAM", > + "EventName": "OCR.DEMAND_DATA_RD.LOCAL_DRAM", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x184000400", > + "MSRValue": "0x184000001", > "Offcore": "1", > "PEBScounters": "0,1,2,3", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > @@ -543,13 +138,13 @@ > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that have any type of response.", > + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.", > "CollectPEBSRecord": "2", > "Counter": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.HWPF_L2_DATA_RD.ANY_RESPONSE", > + "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10010", > + "MSRValue": "0x10002", > "Offcore": "1", > "PEBScounters": "0,1,2,3", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > @@ -558,13 +153,13 @@ > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that DRAM supplied the request.", > + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that DRAM supplied the request.", > "CollectPEBSRecord": "2", > "Counter": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.HWPF_L2_DATA_RD.DRAM", > + "EventName": "OCR.DEMAND_RFO.DRAM", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x184000010", > + "MSRValue": "0x184000002", > "Offcore": "1", > "PEBScounters": "0,1,2,3", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > @@ -573,13 +168,13 @@ > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent or not.", > + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that DRAM supplied the request.", > "CollectPEBSRecord": "2", > "Counter": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.ANY", > + "EventName": "OCR.DEMAND_RFO.LOCAL_DRAM", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3FC03C0010", > + "MSRValue": "0x184000002", > "Offcore": "1", > "PEBScounters": "0,1,2,3", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > @@ -588,13 +183,13 @@ > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.", > + "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that have any type of response.", > "CollectPEBSRecord": "2", > "Counter": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HITM", > + "EventName": "OCR.HWPF_L1D_AND_SWPF.ANY_RESPONSE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10003C0010", > + "MSRValue": "0x10400", > "Offcore": "1", > "PEBScounters": "0,1,2,3", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > @@ -603,13 +198,13 @@ > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.", > + "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that DRAM supplied the request.", > "CollectPEBSRecord": "2", > "Counter": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", > + "EventName": "OCR.HWPF_L1D_AND_SWPF.DRAM", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x4003C0010", > + "MSRValue": "0x184000400", > "Offcore": "1", > "PEBScounters": "0,1,2,3", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > @@ -618,13 +213,13 @@ > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.", > + "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that DRAM supplied the request.", > "CollectPEBSRecord": "2", > "Counter": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_MISS", > + "EventName": "OCR.HWPF_L1D_AND_SWPF.LOCAL_DRAM", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x2003C0010", > + "MSRValue": "0x184000400", > "Offcore": "1", > "PEBScounters": "0,1,2,3", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > @@ -633,13 +228,13 @@ > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.", > + "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that have any type of response.", > "CollectPEBSRecord": "2", > "Counter": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED", > + "EventName": "OCR.HWPF_L2_DATA_RD.ANY_RESPONSE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1003C0010", > + "MSRValue": "0x10010", > "Offcore": "1", > "PEBScounters": "0,1,2,3", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > @@ -648,13 +243,13 @@ > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent.", > + "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that DRAM supplied the request.", > "CollectPEBSRecord": "2", > "Counter": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_SENT", > + "EventName": "OCR.HWPF_L2_DATA_RD.DRAM", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1E003C0010", > + "MSRValue": "0x184000010", > "Offcore": "1", > "PEBScounters": "0,1,2,3", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > @@ -707,96 +302,6 @@ > "Speculative": "1", > "UMask": "0x1" > }, > - { > - "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent or not.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.HWPF_L2_RFO.L3_HIT.ANY", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3FC03C0020", > - "Offcore": "1", > - "PEBScounters": "0,1,2,3", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "Speculative": "1", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HITM", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10003C0020", > - "Offcore": "1", > - "PEBScounters": "0,1,2,3", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "Speculative": "1", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HIT_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x4003C0020", > - "Offcore": "1", > - "PEBScounters": "0,1,2,3", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "Speculative": "1", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x2003C0020", > - "Offcore": "1", > - "PEBScounters": "0,1,2,3", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "Speculative": "1", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_NOT_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1003C0020", > - "Offcore": "1", > - "PEBScounters": "0,1,2,3", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "Speculative": "1", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_SENT", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1E003C0020", > - "Offcore": "1", > - "PEBScounters": "0,1,2,3", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "Speculative": "1", > - "UMask": "0x1" > - }, > { > "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that DRAM supplied the request.", > "CollectPEBSRecord": "2", > @@ -812,21 +317,6 @@ > "Speculative": "1", > "UMask": "0x1" > }, > - { > - "BriefDescription": "Counts hardware prefetches to the L3 only that hit a cacheline in the L3 where a snoop was sent or not.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.HWPF_L3.L3_HIT.ANY", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3FC03C2380", > - "Offcore": "1", > - "PEBScounters": "0,1,2,3", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "Speculative": "1", > - "UMask": "0x1" > - }, > { > "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that have any type of response.", > "CollectPEBSRecord": "2", > @@ -857,66 +347,6 @@ > "Speculative": "1", > "UMask": "0x1" > }, > - { > - "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.L3_HIT.SNOOP_HIT_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x4003C8000", > - "Offcore": "1", > - "PEBScounters": "0,1,2,3", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "Speculative": "1", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.L3_HIT.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x2003C8000", > - "Offcore": "1", > - "PEBScounters": "0,1,2,3", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "Speculative": "1", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.L3_HIT.SNOOP_NOT_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1003C8000", > - "Offcore": "1", > - "PEBScounters": "0,1,2,3", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "Speculative": "1", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop was sent.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.L3_HIT.SNOOP_SENT", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1E003C8000", > - "Offcore": "1", > - "PEBScounters": "0,1,2,3", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "Speculative": "1", > - "UMask": "0x1" > - }, > { > "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that DRAM supplied the request.", > "CollectPEBSRecord": "2", > @@ -962,21 +392,6 @@ > "Speculative": "1", > "UMask": "0x1" > }, > - { > - "BriefDescription": "Counts streaming stores that hit a cacheline in the L3 where a snoop was sent or not.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.STREAMING_WR.L3_HIT.ANY", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3FC03C0800", > - "Offcore": "1", > - "PEBScounters": "0,1,2,3", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "Speculative": "1", > - "UMask": "0x1" > - }, > { > "BriefDescription": "Counts streaming stores that DRAM supplied the request.", > "CollectPEBSRecord": "2", > @@ -991,100 +406,5 @@ > "SampleAfterValue": "100003", > "Speculative": "1", > "UMask": "0x1" > - }, > - { > - "BriefDescription": "Number of PREFETCHNTA instructions executed.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0x32", > - "EventName": "SW_PREFETCH_ACCESS.NTA", > - "PEBScounters": "0,1,2,3", > - "PublicDescription": "Counts the number of PREFETCHNTA instructions executed.", > - "SampleAfterValue": "100003", > - "Speculative": "1", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Number of PREFETCHW instructions executed.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0x32", > - "EventName": "SW_PREFETCH_ACCESS.PREFETCHW", > - "PEBScounters": "0,1,2,3", > - "PublicDescription": "Counts the number of PREFETCHW instructions executed.", > - "SampleAfterValue": "100003", > - "Speculative": "1", > - "UMask": "0x8" > - }, > - { > - "BriefDescription": "Number of PREFETCHT0 instructions executed.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0x32", > - "EventName": "SW_PREFETCH_ACCESS.T0", > - "PEBScounters": "0,1,2,3", > - "PublicDescription": "Counts the number of PREFETCHT0 instructions executed.", > - "SampleAfterValue": "100003", > - "Speculative": "1", > - "UMask": "0x2" > - }, > - { > - "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0x32", > - "EventName": "SW_PREFETCH_ACCESS.T1_T2", > - "PEBScounters": "0,1,2,3", > - "PublicDescription": "Counts the number of PREFETCHT1 or PREFETCHT2 instructions executed.", > - "SampleAfterValue": "100003", > - "Speculative": "1", > - "UMask": "0x4" > - }, > - { > - "BriefDescription": "TMA slots where no uops were being issued due to lack of back-end resources.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3,4,5,6,7", > - "EventCode": "0xa4", > - "EventName": "TOPDOWN.BACKEND_BOUND_SLOTS", > - "PEBScounters": "0,1,2,3,4,5,6,7", > - "PublicDescription": "Counts the number of Top-down Microarchitecture Analysis (TMA) method's slots where no micro-operations were being issued from front-end to back-end of the machine due to lack of back-end resources.", > - "SampleAfterValue": "10000003", > - "Speculative": "1", > - "UMask": "0x2" > - }, > - { > - "BriefDescription": "TMA slots wasted due to incorrect speculation by branch mispredictions", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3,4,5,6,7", > - "EventCode": "0xa4", > - "EventName": "TOPDOWN.BR_MISPREDICT_SLOTS", > - "PEBScounters": "0,1,2,3,4,5,6,7", > - "PublicDescription": "Number of TMA slots that were wasted due to incorrect speculation by branch mispredictions. This event estimates number of operations that were issued but not retired from the specualtive path as well as the out-of-order engine recovery past a branch misprediction.", > - "SampleAfterValue": "10000003", > - "Speculative": "1", > - "UMask": "0x8" > - }, > - { > - "BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - architectural event", > - "CollectPEBSRecord": "2", > - "Counter": "Fixed counter 3", > - "EventName": "TOPDOWN.SLOTS", > - "PEBScounters": "35", > - "PublicDescription": "Number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TMA). The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core. Software can use this event as the denominator for the top-level metrics of the TMA method. This architectural event is counted on a designated fixed counter (Fixed Counter 3).", > - "SampleAfterValue": "10000003", > - "Speculative": "1", > - "UMask": "0x4" > - }, > - { > - "BriefDescription": "TMA slots available for an unhalted logical processor. General counter - architectural event", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3,4,5,6,7", > - "EventCode": "0xa4", > - "EventName": "TOPDOWN.SLOTS_P", > - "PEBScounters": "0,1,2,3,4,5,6,7", > - "PublicDescription": "Counts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core.", > - "SampleAfterValue": "10000003", > - "Speculative": "1", > - "UMask": "0x1" > } > ] > \ No newline at end of file > diff --git a/tools/perf/pmu-events/arch/x86/icelake/pipeline.json b/tools/perf/pmu-events/arch/x86/icelake/pipeline.json > index 2b305bdc8cfc..573ac7ac8879 100644 > --- a/tools/perf/pmu-events/arch/x86/icelake/pipeline.json > +++ b/tools/perf/pmu-events/arch/x86/icelake/pipeline.json > @@ -730,6 +730,53 @@ > "Speculative": "1", > "UMask": "0x1" > }, > + { > + "BriefDescription": "TMA slots where no uops were being issued due to lack of back-end resources.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5,6,7", > + "EventCode": "0xa4", > + "EventName": "TOPDOWN.BACKEND_BOUND_SLOTS", > + "PEBScounters": "0,1,2,3,4,5,6,7", > + "PublicDescription": "Counts the number of Top-down Microarchitecture Analysis (TMA) method's slots where no micro-operations were being issued from front-end to back-end of the machine due to lack of back-end resources.", > + "SampleAfterValue": "10000003", > + "Speculative": "1", > + "UMask": "0x2" > + }, > + { > + "BriefDescription": "TMA slots wasted due to incorrect speculation by branch mispredictions", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5,6,7", > + "EventCode": "0xa4", > + "EventName": "TOPDOWN.BR_MISPREDICT_SLOTS", > + "PEBScounters": "0,1,2,3,4,5,6,7", > + "PublicDescription": "Number of TMA slots that were wasted due to incorrect speculation by branch mispredictions. This event estimates number of operations that were issued but not retired from the specualtive path as well as the out-of-order engine recovery past a branch misprediction.", > + "SampleAfterValue": "10000003", > + "Speculative": "1", > + "UMask": "0x8" > + }, > + { > + "BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - architectural event", > + "CollectPEBSRecord": "2", > + "Counter": "Fixed counter 3", > + "EventName": "TOPDOWN.SLOTS", > + "PEBScounters": "35", > + "PublicDescription": "Number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TMA). The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core. Software can use this event as the denominator for the top-level metrics of the TMA method. This architectural event is counted on a designated fixed counter (Fixed Counter 3).", > + "SampleAfterValue": "10000003", > + "Speculative": "1", > + "UMask": "0x4" > + }, > + { > + "BriefDescription": "TMA slots available for an unhalted logical processor. General counter - architectural event", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5,6,7", > + "EventCode": "0xa4", > + "EventName": "TOPDOWN.SLOTS_P", > + "PEBScounters": "0,1,2,3,4,5,6,7", > + "PublicDescription": "Counts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core.", > + "SampleAfterValue": "10000003", > + "Speculative": "1", > + "UMask": "0x1" > + }, > { > "BriefDescription": "Number of uops decoded out of instructions exclusively fetched by decoder 0", > "CollectPEBSRecord": "2", -- Zhengjun Xing ^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 4/8] perf vendor events: Update events for IcelakeX 2022-03-17 18:28 [PATCH 1/8] perf vendor events: Update events for CascadelakeX Ian Rogers 2022-03-17 18:28 ` [PATCH 2/8] perf vendor events: Update events for Elkhartlake Ian Rogers 2022-03-17 18:28 ` [PATCH 3/8] perf vendor events: Update events for Icelake Ian Rogers @ 2022-03-17 18:28 ` Ian Rogers 2022-03-18 9:19 ` Xing Zhengjun 2022-03-17 18:28 ` [PATCH 5/8] perf vendor events: Update events for Skylake Ian Rogers ` (5 subsequent siblings) 8 siblings, 1 reply; 18+ messages in thread From: Ian Rogers @ 2022-03-17 18:28 UTC (permalink / raw) To: Kan Liang, Zhengjun Xing, Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo, Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim, Maxime Coquelin, Alexandre Torgue, Andi Kleen, James Clark, John Garry, linux-kernel, linux-perf-users Cc: Stephane Eranian, Ian Rogers Move from v1.11 to v1.12. The change: https://github.com/intel/event-converter-for-linux-perf/commit/fc680410402e394eed6a1ebd909c9f649d3ed3ef moved certain "other" type of events in to the cache, memory and pipeline topics. Update the perf json files for this change. Tested: ``` ... 6: Parse event definition strings : Ok ... 91: perf all PMU test : Ok ... ``` Signed-off-by: Ian Rogers <irogers@google.com> --- .../pmu-events/arch/x86/icelakex/cache.json | 252 +++++++++++++++ .../pmu-events/arch/x86/icelakex/memory.json | 26 +- .../pmu-events/arch/x86/icelakex/other.json | 287 ++---------------- .../arch/x86/icelakex/pipeline.json | 35 +++ 4 files changed, 324 insertions(+), 276 deletions(-) diff --git a/tools/perf/pmu-events/arch/x86/icelakex/cache.json b/tools/perf/pmu-events/arch/x86/icelakex/cache.json index 104409fd8647..3c4da0371df9 100644 --- a/tools/perf/pmu-events/arch/x86/icelakex/cache.json +++ b/tools/perf/pmu-events/arch/x86/icelakex/cache.json @@ -657,6 +657,30 @@ "SampleAfterValue": "100003", "UMask": "0x80" }, + { + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit in the L3 or were snooped from another core's caches on the same socket.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C0004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that resulted in a snoop hit a modified line in another core's caches which forwarded the data.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, { "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.", "Counter": "0,1,2,3", @@ -681,6 +705,54 @@ "SampleAfterValue": "100003", "UMask": "0x1" }, + { + "BriefDescription": "Counts demand data reads that hit in the L3 or were snooped from another core's caches on the same socket.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C0001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads that resulted in a snoop hit a modified line in another core's caches which forwarded the data.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads that resulted in a snoop that hit in another core, which did not forward the data.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003C0001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads that resulted in a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8003C0001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, { "BriefDescription": "Counts demand data reads that were supplied by a cache on a remote socket where a snoop hit a modified line in another core's caches which forwarded the data.", "Counter": "0,1,2,3", @@ -729,6 +801,30 @@ "SampleAfterValue": "100003", "UMask": "0x1" }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit in the L3 or were snooped from another core's caches on the same socket.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_RFO.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C0002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that resulted in a snoop hit a modified line in another core's caches which forwarded the data.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, { "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.", "Counter": "0,1,2,3", @@ -753,6 +849,102 @@ "SampleAfterValue": "100003", "UMask": "0x1" }, + { + "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit in the L3 or were snooped from another core's caches on the same socket.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C0400", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts hardware prefetches to the L3 only that hit in the L3 or were snooped from another core's caches on the same socket.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.HWPF_L3.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80082380", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts hardware and software prefetches to all cache levels that hit in the L3 or were snooped from another core's caches on the same socket.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PREFETCHES.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C27F0", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that hit in the L3 or were snooped from another core's caches on the same socket.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.READS_TO_CORE.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F003C0477", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop hit a modified line in another core's caches which forwarded the data.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0477", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop that hit in another core, which did not forward the data.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003C0477", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_WITH_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8003C0477", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop was sent and data was returned (Modified or Not Modified).", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1830000477", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, { "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop hit a modified line in another core's caches which forwarded the data.", "Counter": "0,1,2,3", @@ -801,6 +993,18 @@ "SampleAfterValue": "100003", "UMask": "0x1" }, + { + "BriefDescription": "Counts streaming stores that hit in the L3 or were snooped from another core's caches on the same socket.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.STREAMING_WR.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80080800", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, { "BriefDescription": "Demand and prefetch data reads", "CollectPEBSRecord": "2", @@ -947,5 +1151,53 @@ "SampleAfterValue": "100003", "Speculative": "1", "UMask": "0x4" + }, + { + "BriefDescription": "Number of PREFETCHNTA instructions executed.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "SW_PREFETCH_ACCESS.NTA", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of PREFETCHNTA instructions executed.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of PREFETCHW instructions executed.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "SW_PREFETCH_ACCESS.PREFETCHW", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of PREFETCHW instructions executed.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x8" + }, + { + "BriefDescription": "Number of PREFETCHT0 instructions executed.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "SW_PREFETCH_ACCESS.T0", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of PREFETCHT0 instructions executed.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x2" + }, + { + "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "SW_PREFETCH_ACCESS.T1_T2", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of PREFETCHT1 or PREFETCHT2 instructions executed.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x4" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/icelakex/memory.json b/tools/perf/pmu-events/arch/x86/icelakex/memory.json index 9ebcd442e6d3..c10a1bbc66b1 100644 --- a/tools/perf/pmu-events/arch/x86/icelakex/memory.json +++ b/tools/perf/pmu-events/arch/x86/icelakex/memory.json @@ -169,7 +169,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3F8CC00004", + "MSRValue": "0x3F84400004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -193,7 +193,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3F8CC00001", + "MSRValue": "0x3F84400001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -217,7 +217,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3F0CC00002", + "MSRValue": "0x3F04400002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -241,7 +241,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3F8CC00400", + "MSRValue": "0x3F84400400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -301,7 +301,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3F8CC08000", + "MSRValue": "0x3F84408000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -313,7 +313,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PREFETCHES.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3F8CC027F0", + "MSRValue": "0x3F844027F0", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -337,7 +337,19 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.READS_TO_CORE.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3F0CC00477", + "MSRValue": "0x3F04400477", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that missed the L3 Cache and were supplied by the local socket (DRAM or PMM), whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts PMM or DRAM accesses that are controlled by the close or distant SNC Cluster.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.READS_TO_CORE.L3_MISS_LOCAL_SOCKET", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x70CC00477", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", diff --git a/tools/perf/pmu-events/arch/x86/icelakex/other.json b/tools/perf/pmu-events/arch/x86/icelakex/other.json index 43524f274307..1246b22769da 100644 --- a/tools/perf/pmu-events/arch/x86/icelakex/other.json +++ b/tools/perf/pmu-events/arch/x86/icelakex/other.json @@ -156,31 +156,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit in the L3 or were snooped from another core's caches on the same socket.", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3F803C0004", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that resulted in a snoop hit a modified line in another core's caches which forwarded the data.", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x10003C0004", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that the DRAM attached to this socket supplied the request.", + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.LOCAL_DRAM", @@ -228,55 +204,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts demand data reads that hit in the L3 or were snooped from another core's caches on the same socket.", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3F803C0001", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads that resulted in a snoop hit a modified line in another core's caches which forwarded the data.", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x10003C0001", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads that resulted in a snoop that hit in another core, which did not forward the data.", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x4003C0001", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads that resulted in a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x8003C0001", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads that the DRAM attached to this socket supplied the request.", + "BriefDescription": "Counts demand data reads that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.LOCAL_DRAM", @@ -288,7 +216,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts demand data reads that were supplied by PMM attached to this socket.", + "BriefDescription": "Counts demand data reads that were supplied by PMM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those PMM accesses that are controlled by the close SNC Cluster.", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.LOCAL_PMM", @@ -384,31 +312,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit in the L3 or were snooped from another core's caches on the same socket.", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_RFO.L3_HIT", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3F803C0002", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that resulted in a snoop hit a modified line in another core's caches which forwarded the data.", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x10003C0002", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that the DRAM attached to this socket supplied the request.", + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.LOCAL_DRAM", @@ -420,7 +324,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by PMM attached to this socket.", + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by PMM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those PMM accesses that are controlled by the close SNC Cluster.", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.LOCAL_PMM", @@ -492,19 +396,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit in the L3 or were snooped from another core's caches on the same socket.", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3F803C0400", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that the DRAM attached to this socket supplied the request.", + "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.HWPF_L1D_AND_SWPF.LOCAL_DRAM", @@ -527,18 +419,6 @@ "SampleAfterValue": "100003", "UMask": "0x1" }, - { - "BriefDescription": "Counts hardware prefetches to the L3 only that hit in the L3 or were snooped from another core's caches on the same socket.", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L3.L3_HIT", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x80082380", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, { "BriefDescription": "Counts hardware prefetches to the L3 only that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline was homed in a remote socket.", "Counter": "0,1,2,3", @@ -575,18 +455,6 @@ "SampleAfterValue": "100003", "UMask": "0x1" }, - { - "BriefDescription": "Counts hardware and software prefetches to all cache levels that hit in the L3 or were snooped from another core's caches on the same socket.", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PREFETCHES.L3_HIT", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3F803C27F0", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, { "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that have any type of response.", "Counter": "0,1,2,3", @@ -612,72 +480,48 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that hit in the L3 or were snooped from another core's caches on the same socket.", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.READS_TO_CORE.L3_HIT", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3F003C0477", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop hit a modified line in another core's caches which forwarded the data.", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HITM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x10003C0477", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop that hit in another core, which did not forward the data.", + "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_NO_FWD", + "EventName": "OCR.READS_TO_CORE.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x4003C0477", + "MSRValue": "0x104000477", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.", + "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those PMM accesses that are controlled by the close SNC Cluster.", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_WITH_FWD", + "EventName": "OCR.READS_TO_CORE.LOCAL_PMM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x8003C0477", + "MSRValue": "0x100400477", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that the DRAM attached to this socket supplied the request.", + "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to this socket, whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts DRAM accesses that are controlled by the close or distant SNC Cluster.", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.READS_TO_CORE.LOCAL_DRAM", + "EventName": "OCR.READS_TO_CORE.LOCAL_SOCKET_DRAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x104000477", + "MSRValue": "0x70C000477", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM attached to this socket.", + "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM attached to this socket, whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts PMM accesses that are controlled by the close or distant SNC Cluster.", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.READS_TO_CORE.LOCAL_PMM", + "EventName": "OCR.READS_TO_CORE.LOCAL_SOCKET_PMM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x100400477", + "MSRValue": "0x700C00477", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -754,100 +598,5 @@ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" - }, - { - "BriefDescription": "Counts streaming stores that hit in the L3 or were snooped from another core's caches on the same socket.", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.STREAMING_WR.L3_HIT", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x80080800", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Number of PREFETCHNTA instructions executed.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x32", - "EventName": "SW_PREFETCH_ACCESS.NTA", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of PREFETCHNTA instructions executed.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Number of PREFETCHW instructions executed.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x32", - "EventName": "SW_PREFETCH_ACCESS.PREFETCHW", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of PREFETCHW instructions executed.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x8" - }, - { - "BriefDescription": "Number of PREFETCHT0 instructions executed.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x32", - "EventName": "SW_PREFETCH_ACCESS.T0", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of PREFETCHT0 instructions executed.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x2" - }, - { - "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x32", - "EventName": "SW_PREFETCH_ACCESS.T1_T2", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of PREFETCHT1 or PREFETCHT2 instructions executed.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x4" - }, - { - "BriefDescription": "TMA slots where no uops were being issued due to lack of back-end resources.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xa4", - "EventName": "TOPDOWN.BACKEND_BOUND_SLOTS", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of Top-down Microarchitecture Analysis (TMA) method's slots where no micro-operations were being issued from front-end to back-end of the machine due to lack of back-end resources.", - "SampleAfterValue": "10000003", - "Speculative": "1", - "UMask": "0x2" - }, - { - "BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - architectural event", - "CollectPEBSRecord": "2", - "Counter": "Fixed counter 3", - "EventName": "TOPDOWN.SLOTS", - "PEBScounters": "35", - "PublicDescription": "Number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TMA). The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core. Software can use this event as the denominator for the top-level metrics of the TMA method. This architectural event is counted on a designated fixed counter (Fixed Counter 3).", - "SampleAfterValue": "10000003", - "Speculative": "1", - "UMask": "0x4" - }, - { - "BriefDescription": "TMA slots available for an unhalted logical processor. General counter - architectural event", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xa4", - "EventName": "TOPDOWN.SLOTS_P", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core.", - "SampleAfterValue": "10000003", - "Speculative": "1", - "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/icelakex/pipeline.json b/tools/perf/pmu-events/arch/x86/icelakex/pipeline.json index 9a0b4907cb3a..068a3d46b443 100644 --- a/tools/perf/pmu-events/arch/x86/icelakex/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/icelakex/pipeline.json @@ -728,6 +728,41 @@ "Speculative": "1", "UMask": "0x1" }, + { + "BriefDescription": "TMA slots where no uops were being issued due to lack of back-end resources.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xa4", + "EventName": "TOPDOWN.BACKEND_BOUND_SLOTS", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts the number of Top-down Microarchitecture Analysis (TMA) method's slots where no micro-operations were being issued from front-end to back-end of the machine due to lack of back-end resources.", + "SampleAfterValue": "10000003", + "Speculative": "1", + "UMask": "0x2" + }, + { + "BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - architectural event", + "CollectPEBSRecord": "2", + "Counter": "Fixed counter 3", + "EventName": "TOPDOWN.SLOTS", + "PEBScounters": "35", + "PublicDescription": "Number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TMA). The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core. Software can use this event as the denominator for the top-level metrics of the TMA method. This architectural event is counted on a designated fixed counter (Fixed Counter 3).", + "SampleAfterValue": "10000003", + "Speculative": "1", + "UMask": "0x4" + }, + { + "BriefDescription": "TMA slots available for an unhalted logical processor. General counter - architectural event", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xa4", + "EventName": "TOPDOWN.SLOTS_P", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core.", + "SampleAfterValue": "10000003", + "Speculative": "1", + "UMask": "0x1" + }, { "BriefDescription": "Number of uops decoded out of instructions exclusively fetched by decoder 0", "CollectPEBSRecord": "2", -- 2.35.1.894.gb6a874cedc-goog ^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PATCH 4/8] perf vendor events: Update events for IcelakeX 2022-03-17 18:28 ` [PATCH 4/8] perf vendor events: Update events for IcelakeX Ian Rogers @ 2022-03-18 9:19 ` Xing Zhengjun 0 siblings, 0 replies; 18+ messages in thread From: Xing Zhengjun @ 2022-03-18 9:19 UTC (permalink / raw) To: Ian Rogers, Kan Liang, Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo, Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim, Maxime Coquelin, Alexandre Torgue, Andi Kleen, James Clark, John Garry, linux-kernel, linux-perf-users Cc: Stephane Eranian On 3/18/2022 2:28 AM, Ian Rogers wrote: > Move from v1.11 to v1.12. > The change: > https://github.com/intel/event-converter-for-linux-perf/commit/fc680410402e394eed6a1ebd909c9f649d3ed3ef > moved certain "other" type of events in to the cache, memory and > pipeline topics. Update the perf json files for this change. > > Tested: > ``` > ... > 6: Parse event definition strings : Ok > ... > 91: perf all PMU test : Ok > ... > ``` > > Signed-off-by: Ian Rogers <irogers@google.com> Reviewed-by: Zhengjun Xing <zhengjun.xing@linux.intel.com> > --- > .../pmu-events/arch/x86/icelakex/cache.json | 252 +++++++++++++++ > .../pmu-events/arch/x86/icelakex/memory.json | 26 +- > .../pmu-events/arch/x86/icelakex/other.json | 287 ++---------------- > .../arch/x86/icelakex/pipeline.json | 35 +++ > 4 files changed, 324 insertions(+), 276 deletions(-) > > diff --git a/tools/perf/pmu-events/arch/x86/icelakex/cache.json b/tools/perf/pmu-events/arch/x86/icelakex/cache.json > index 104409fd8647..3c4da0371df9 100644 > --- a/tools/perf/pmu-events/arch/x86/icelakex/cache.json > +++ b/tools/perf/pmu-events/arch/x86/icelakex/cache.json > @@ -657,6 +657,30 @@ > "SampleAfterValue": "100003", > "UMask": "0x80" > }, > + { > + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit in the L3 or were snooped from another core's caches on the same socket.", > + "Counter": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F803C0004", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that resulted in a snoop hit a modified line in another core's caches which forwarded the data.", > + "Counter": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x10003C0004", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > { > "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.", > "Counter": "0,1,2,3", > @@ -681,6 +705,54 @@ > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > + { > + "BriefDescription": "Counts demand data reads that hit in the L3 or were snooped from another core's caches on the same socket.", > + "Counter": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F803C0001", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand data reads that resulted in a snoop hit a modified line in another core's caches which forwarded the data.", > + "Counter": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x10003C0001", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand data reads that resulted in a snoop that hit in another core, which did not forward the data.", > + "Counter": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x4003C0001", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand data reads that resulted in a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.", > + "Counter": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x8003C0001", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > { > "BriefDescription": "Counts demand data reads that were supplied by a cache on a remote socket where a snoop hit a modified line in another core's caches which forwarded the data.", > "Counter": "0,1,2,3", > @@ -729,6 +801,30 @@ > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > + { > + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit in the L3 or were snooped from another core's caches on the same socket.", > + "Counter": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_RFO.L3_HIT", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F803C0002", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that resulted in a snoop hit a modified line in another core's caches which forwarded the data.", > + "Counter": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x10003C0002", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > { > "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.", > "Counter": "0,1,2,3", > @@ -753,6 +849,102 @@ > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > + { > + "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit in the L3 or were snooped from another core's caches on the same socket.", > + "Counter": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F803C0400", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts hardware prefetches to the L3 only that hit in the L3 or were snooped from another core's caches on the same socket.", > + "Counter": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.HWPF_L3.L3_HIT", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80082380", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts hardware and software prefetches to all cache levels that hit in the L3 or were snooped from another core's caches on the same socket.", > + "Counter": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PREFETCHES.L3_HIT", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F803C27F0", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that hit in the L3 or were snooped from another core's caches on the same socket.", > + "Counter": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.READS_TO_CORE.L3_HIT", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F003C0477", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop hit a modified line in another core's caches which forwarded the data.", > + "Counter": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HITM", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x10003C0477", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop that hit in another core, which did not forward the data.", > + "Counter": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x4003C0477", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.", > + "Counter": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_WITH_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x8003C0477", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop was sent and data was returned (Modified or Not Modified).", > + "Counter": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1830000477", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > { > "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop hit a modified line in another core's caches which forwarded the data.", > "Counter": "0,1,2,3", > @@ -801,6 +993,18 @@ > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > + { > + "BriefDescription": "Counts streaming stores that hit in the L3 or were snooped from another core's caches on the same socket.", > + "Counter": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.STREAMING_WR.L3_HIT", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80080800", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > { > "BriefDescription": "Demand and prefetch data reads", > "CollectPEBSRecord": "2", > @@ -947,5 +1151,53 @@ > "SampleAfterValue": "100003", > "Speculative": "1", > "UMask": "0x4" > + }, > + { > + "BriefDescription": "Number of PREFETCHNTA instructions executed.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0x32", > + "EventName": "SW_PREFETCH_ACCESS.NTA", > + "PEBScounters": "0,1,2,3", > + "PublicDescription": "Counts the number of PREFETCHNTA instructions executed.", > + "SampleAfterValue": "100003", > + "Speculative": "1", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Number of PREFETCHW instructions executed.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0x32", > + "EventName": "SW_PREFETCH_ACCESS.PREFETCHW", > + "PEBScounters": "0,1,2,3", > + "PublicDescription": "Counts the number of PREFETCHW instructions executed.", > + "SampleAfterValue": "100003", > + "Speculative": "1", > + "UMask": "0x8" > + }, > + { > + "BriefDescription": "Number of PREFETCHT0 instructions executed.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0x32", > + "EventName": "SW_PREFETCH_ACCESS.T0", > + "PEBScounters": "0,1,2,3", > + "PublicDescription": "Counts the number of PREFETCHT0 instructions executed.", > + "SampleAfterValue": "100003", > + "Speculative": "1", > + "UMask": "0x2" > + }, > + { > + "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0x32", > + "EventName": "SW_PREFETCH_ACCESS.T1_T2", > + "PEBScounters": "0,1,2,3", > + "PublicDescription": "Counts the number of PREFETCHT1 or PREFETCHT2 instructions executed.", > + "SampleAfterValue": "100003", > + "Speculative": "1", > + "UMask": "0x4" > } > ] > \ No newline at end of file > diff --git a/tools/perf/pmu-events/arch/x86/icelakex/memory.json b/tools/perf/pmu-events/arch/x86/icelakex/memory.json > index 9ebcd442e6d3..c10a1bbc66b1 100644 > --- a/tools/perf/pmu-events/arch/x86/icelakex/memory.json > +++ b/tools/perf/pmu-events/arch/x86/icelakex/memory.json > @@ -169,7 +169,7 @@ > "EventCode": "0xB7, 0xBB", > "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F8CC00004", > + "MSRValue": "0x3F84400004", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > @@ -193,7 +193,7 @@ > "EventCode": "0xB7, 0xBB", > "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F8CC00001", > + "MSRValue": "0x3F84400001", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > @@ -217,7 +217,7 @@ > "EventCode": "0xB7, 0xBB", > "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F0CC00002", > + "MSRValue": "0x3F04400002", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > @@ -241,7 +241,7 @@ > "EventCode": "0xB7, 0xBB", > "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_MISS_LOCAL", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F8CC00400", > + "MSRValue": "0x3F84400400", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > @@ -301,7 +301,7 @@ > "EventCode": "0xB7, 0xBB", > "EventName": "OCR.OTHER.L3_MISS_LOCAL", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F8CC08000", > + "MSRValue": "0x3F84408000", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > @@ -313,7 +313,7 @@ > "EventCode": "0xB7, 0xBB", > "EventName": "OCR.PREFETCHES.L3_MISS_LOCAL", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F8CC027F0", > + "MSRValue": "0x3F844027F0", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > @@ -337,7 +337,19 @@ > "EventCode": "0xB7, 0xBB", > "EventName": "OCR.READS_TO_CORE.L3_MISS_LOCAL", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F0CC00477", > + "MSRValue": "0x3F04400477", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that missed the L3 Cache and were supplied by the local socket (DRAM or PMM), whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts PMM or DRAM accesses that are controlled by the close or distant SNC Cluster.", > + "Counter": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.READS_TO_CORE.L3_MISS_LOCAL_SOCKET", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x70CC00477", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > diff --git a/tools/perf/pmu-events/arch/x86/icelakex/other.json b/tools/perf/pmu-events/arch/x86/icelakex/other.json > index 43524f274307..1246b22769da 100644 > --- a/tools/perf/pmu-events/arch/x86/icelakex/other.json > +++ b/tools/perf/pmu-events/arch/x86/icelakex/other.json > @@ -156,31 +156,7 @@ > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit in the L3 or were snooped from another core's caches on the same socket.", > - "Counter": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F803C0004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that resulted in a snoop hit a modified line in another core's caches which forwarded the data.", > - "Counter": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10003C0004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that the DRAM attached to this socket supplied the request.", > + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.", > "Counter": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > "EventName": "OCR.DEMAND_CODE_RD.LOCAL_DRAM", > @@ -228,55 +204,7 @@ > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts demand data reads that hit in the L3 or were snooped from another core's caches on the same socket.", > - "Counter": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F803C0001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads that resulted in a snoop hit a modified line in another core's caches which forwarded the data.", > - "Counter": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10003C0001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads that resulted in a snoop that hit in another core, which did not forward the data.", > - "Counter": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x4003C0001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads that resulted in a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.", > - "Counter": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x8003C0001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads that the DRAM attached to this socket supplied the request.", > + "BriefDescription": "Counts demand data reads that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.", > "Counter": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > "EventName": "OCR.DEMAND_DATA_RD.LOCAL_DRAM", > @@ -288,7 +216,7 @@ > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts demand data reads that were supplied by PMM attached to this socket.", > + "BriefDescription": "Counts demand data reads that were supplied by PMM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those PMM accesses that are controlled by the close SNC Cluster.", > "Counter": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > "EventName": "OCR.DEMAND_DATA_RD.LOCAL_PMM", > @@ -384,31 +312,7 @@ > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit in the L3 or were snooped from another core's caches on the same socket.", > - "Counter": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.L3_HIT", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F803C0002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that resulted in a snoop hit a modified line in another core's caches which forwarded the data.", > - "Counter": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10003C0002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that the DRAM attached to this socket supplied the request.", > + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.", > "Counter": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > "EventName": "OCR.DEMAND_RFO.LOCAL_DRAM", > @@ -420,7 +324,7 @@ > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by PMM attached to this socket.", > + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by PMM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those PMM accesses that are controlled by the close SNC Cluster.", > "Counter": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > "EventName": "OCR.DEMAND_RFO.LOCAL_PMM", > @@ -492,19 +396,7 @@ > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit in the L3 or were snooped from another core's caches on the same socket.", > - "Counter": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F803C0400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that the DRAM attached to this socket supplied the request.", > + "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.", > "Counter": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > "EventName": "OCR.HWPF_L1D_AND_SWPF.LOCAL_DRAM", > @@ -527,18 +419,6 @@ > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > - { > - "BriefDescription": "Counts hardware prefetches to the L3 only that hit in the L3 or were snooped from another core's caches on the same socket.", > - "Counter": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.HWPF_L3.L3_HIT", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80082380", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > { > "BriefDescription": "Counts hardware prefetches to the L3 only that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline was homed in a remote socket.", > "Counter": "0,1,2,3", > @@ -575,18 +455,6 @@ > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > - { > - "BriefDescription": "Counts hardware and software prefetches to all cache levels that hit in the L3 or were snooped from another core's caches on the same socket.", > - "Counter": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PREFETCHES.L3_HIT", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F803C27F0", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > { > "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that have any type of response.", > "Counter": "0,1,2,3", > @@ -612,72 +480,48 @@ > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that hit in the L3 or were snooped from another core's caches on the same socket.", > - "Counter": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.READS_TO_CORE.L3_HIT", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F003C0477", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop hit a modified line in another core's caches which forwarded the data.", > - "Counter": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HITM", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10003C0477", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop that hit in another core, which did not forward the data.", > + "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.", > "Counter": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_NO_FWD", > + "EventName": "OCR.READS_TO_CORE.LOCAL_DRAM", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x4003C0477", > + "MSRValue": "0x104000477", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.", > + "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those PMM accesses that are controlled by the close SNC Cluster.", > "Counter": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_WITH_FWD", > + "EventName": "OCR.READS_TO_CORE.LOCAL_PMM", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x8003C0477", > + "MSRValue": "0x100400477", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that the DRAM attached to this socket supplied the request.", > + "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to this socket, whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts DRAM accesses that are controlled by the close or distant SNC Cluster.", > "Counter": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.READS_TO_CORE.LOCAL_DRAM", > + "EventName": "OCR.READS_TO_CORE.LOCAL_SOCKET_DRAM", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x104000477", > + "MSRValue": "0x70C000477", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM attached to this socket.", > + "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM attached to this socket, whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts PMM accesses that are controlled by the close or distant SNC Cluster.", > "Counter": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.READS_TO_CORE.LOCAL_PMM", > + "EventName": "OCR.READS_TO_CORE.LOCAL_SOCKET_PMM", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100400477", > + "MSRValue": "0x700C00477", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > @@ -754,100 +598,5 @@ > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts streaming stores that hit in the L3 or were snooped from another core's caches on the same socket.", > - "Counter": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.STREAMING_WR.L3_HIT", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80080800", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Number of PREFETCHNTA instructions executed.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0x32", > - "EventName": "SW_PREFETCH_ACCESS.NTA", > - "PEBScounters": "0,1,2,3", > - "PublicDescription": "Counts the number of PREFETCHNTA instructions executed.", > - "SampleAfterValue": "100003", > - "Speculative": "1", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Number of PREFETCHW instructions executed.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0x32", > - "EventName": "SW_PREFETCH_ACCESS.PREFETCHW", > - "PEBScounters": "0,1,2,3", > - "PublicDescription": "Counts the number of PREFETCHW instructions executed.", > - "SampleAfterValue": "100003", > - "Speculative": "1", > - "UMask": "0x8" > - }, > - { > - "BriefDescription": "Number of PREFETCHT0 instructions executed.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0x32", > - "EventName": "SW_PREFETCH_ACCESS.T0", > - "PEBScounters": "0,1,2,3", > - "PublicDescription": "Counts the number of PREFETCHT0 instructions executed.", > - "SampleAfterValue": "100003", > - "Speculative": "1", > - "UMask": "0x2" > - }, > - { > - "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0x32", > - "EventName": "SW_PREFETCH_ACCESS.T1_T2", > - "PEBScounters": "0,1,2,3", > - "PublicDescription": "Counts the number of PREFETCHT1 or PREFETCHT2 instructions executed.", > - "SampleAfterValue": "100003", > - "Speculative": "1", > - "UMask": "0x4" > - }, > - { > - "BriefDescription": "TMA slots where no uops were being issued due to lack of back-end resources.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3,4,5,6,7", > - "EventCode": "0xa4", > - "EventName": "TOPDOWN.BACKEND_BOUND_SLOTS", > - "PEBScounters": "0,1,2,3,4,5,6,7", > - "PublicDescription": "Counts the number of Top-down Microarchitecture Analysis (TMA) method's slots where no micro-operations were being issued from front-end to back-end of the machine due to lack of back-end resources.", > - "SampleAfterValue": "10000003", > - "Speculative": "1", > - "UMask": "0x2" > - }, > - { > - "BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - architectural event", > - "CollectPEBSRecord": "2", > - "Counter": "Fixed counter 3", > - "EventName": "TOPDOWN.SLOTS", > - "PEBScounters": "35", > - "PublicDescription": "Number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TMA). The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core. Software can use this event as the denominator for the top-level metrics of the TMA method. This architectural event is counted on a designated fixed counter (Fixed Counter 3).", > - "SampleAfterValue": "10000003", > - "Speculative": "1", > - "UMask": "0x4" > - }, > - { > - "BriefDescription": "TMA slots available for an unhalted logical processor. General counter - architectural event", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3,4,5,6,7", > - "EventCode": "0xa4", > - "EventName": "TOPDOWN.SLOTS_P", > - "PEBScounters": "0,1,2,3,4,5,6,7", > - "PublicDescription": "Counts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core.", > - "SampleAfterValue": "10000003", > - "Speculative": "1", > - "UMask": "0x1" > } > ] > \ No newline at end of file > diff --git a/tools/perf/pmu-events/arch/x86/icelakex/pipeline.json b/tools/perf/pmu-events/arch/x86/icelakex/pipeline.json > index 9a0b4907cb3a..068a3d46b443 100644 > --- a/tools/perf/pmu-events/arch/x86/icelakex/pipeline.json > +++ b/tools/perf/pmu-events/arch/x86/icelakex/pipeline.json > @@ -728,6 +728,41 @@ > "Speculative": "1", > "UMask": "0x1" > }, > + { > + "BriefDescription": "TMA slots where no uops were being issued due to lack of back-end resources.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5,6,7", > + "EventCode": "0xa4", > + "EventName": "TOPDOWN.BACKEND_BOUND_SLOTS", > + "PEBScounters": "0,1,2,3,4,5,6,7", > + "PublicDescription": "Counts the number of Top-down Microarchitecture Analysis (TMA) method's slots where no micro-operations were being issued from front-end to back-end of the machine due to lack of back-end resources.", > + "SampleAfterValue": "10000003", > + "Speculative": "1", > + "UMask": "0x2" > + }, > + { > + "BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - architectural event", > + "CollectPEBSRecord": "2", > + "Counter": "Fixed counter 3", > + "EventName": "TOPDOWN.SLOTS", > + "PEBScounters": "35", > + "PublicDescription": "Number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TMA). The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core. Software can use this event as the denominator for the top-level metrics of the TMA method. This architectural event is counted on a designated fixed counter (Fixed Counter 3).", > + "SampleAfterValue": "10000003", > + "Speculative": "1", > + "UMask": "0x4" > + }, > + { > + "BriefDescription": "TMA slots available for an unhalted logical processor. General counter - architectural event", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5,6,7", > + "EventCode": "0xa4", > + "EventName": "TOPDOWN.SLOTS_P", > + "PEBScounters": "0,1,2,3,4,5,6,7", > + "PublicDescription": "Counts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core.", > + "SampleAfterValue": "10000003", > + "Speculative": "1", > + "UMask": "0x1" > + }, > { > "BriefDescription": "Number of uops decoded out of instructions exclusively fetched by decoder 0", > "CollectPEBSRecord": "2", -- Zhengjun Xing ^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 5/8] perf vendor events: Update events for Skylake 2022-03-17 18:28 [PATCH 1/8] perf vendor events: Update events for CascadelakeX Ian Rogers ` (2 preceding siblings ...) 2022-03-17 18:28 ` [PATCH 4/8] perf vendor events: Update events for IcelakeX Ian Rogers @ 2022-03-17 18:28 ` Ian Rogers 2022-03-18 9:19 ` Xing Zhengjun 2022-03-17 18:28 ` [PATCH 6/8] perf vendor events: Update events for SkylakeX Ian Rogers ` (4 subsequent siblings) 8 siblings, 1 reply; 18+ messages in thread From: Ian Rogers @ 2022-03-17 18:28 UTC (permalink / raw) To: Kan Liang, Zhengjun Xing, Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo, Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim, Maxime Coquelin, Alexandre Torgue, Andi Kleen, James Clark, John Garry, linux-kernel, linux-perf-users Cc: Stephane Eranian, Ian Rogers The change: https://github.com/intel/event-converter-for-linux-perf/commit/fc680410402e394eed6a1ebd909c9f649d3ed3ef moved certain "other" type of events in to the cache topic. Update the perf json files for this change. Signed-off-by: Ian Rogers <irogers@google.com> --- .../pmu-events/arch/x86/skylake/cache.json | 36 +++++++++++++++++++ .../pmu-events/arch/x86/skylake/other.json | 36 ------------------- 2 files changed, 36 insertions(+), 36 deletions(-) diff --git a/tools/perf/pmu-events/arch/x86/skylake/cache.json b/tools/perf/pmu-events/arch/x86/skylake/cache.json index 529c5e6e117f..c5d9a4ed10d7 100644 --- a/tools/perf/pmu-events/arch/x86/skylake/cache.json +++ b/tools/perf/pmu-events/arch/x86/skylake/cache.json @@ -2937,5 +2937,41 @@ "PublicDescription": "Counts the number of cache line split locks sent to the uncore.", "SampleAfterValue": "100003", "UMask": "0x10" + }, + { + "BriefDescription": "Number of PREFETCHNTA instructions executed.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x32", + "EventName": "SW_PREFETCH_ACCESS.NTA", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of PREFETCHW instructions executed.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x32", + "EventName": "SW_PREFETCH_ACCESS.PREFETCHW", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Number of PREFETCHT0 instructions executed.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x32", + "EventName": "SW_PREFETCH_ACCESS.T0", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x32", + "EventName": "SW_PREFETCH_ACCESS.T1_T2", + "SampleAfterValue": "2000003", + "UMask": "0x4" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/skylake/other.json b/tools/perf/pmu-events/arch/x86/skylake/other.json index 5c0e81f76a5b..4f4839024915 100644 --- a/tools/perf/pmu-events/arch/x86/skylake/other.json +++ b/tools/perf/pmu-events/arch/x86/skylake/other.json @@ -16,41 +16,5 @@ "EventName": "MEMORY_DISAMBIGUATION.HISTORY_RESET", "SampleAfterValue": "2000003", "UMask": "0x1" - }, - { - "BriefDescription": "Number of PREFETCHNTA instructions executed.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x32", - "EventName": "SW_PREFETCH_ACCESS.NTA", - "SampleAfterValue": "2000003", - "UMask": "0x1" - }, - { - "BriefDescription": "Number of PREFETCHW instructions executed.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x32", - "EventName": "SW_PREFETCH_ACCESS.PREFETCHW", - "SampleAfterValue": "2000003", - "UMask": "0x8" - }, - { - "BriefDescription": "Number of PREFETCHT0 instructions executed.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x32", - "EventName": "SW_PREFETCH_ACCESS.T0", - "SampleAfterValue": "2000003", - "UMask": "0x2" - }, - { - "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x32", - "EventName": "SW_PREFETCH_ACCESS.T1_T2", - "SampleAfterValue": "2000003", - "UMask": "0x4" } ] \ No newline at end of file -- 2.35.1.894.gb6a874cedc-goog ^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PATCH 5/8] perf vendor events: Update events for Skylake 2022-03-17 18:28 ` [PATCH 5/8] perf vendor events: Update events for Skylake Ian Rogers @ 2022-03-18 9:19 ` Xing Zhengjun 0 siblings, 0 replies; 18+ messages in thread From: Xing Zhengjun @ 2022-03-18 9:19 UTC (permalink / raw) To: Ian Rogers, Kan Liang, Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo, Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim, Maxime Coquelin, Alexandre Torgue, Andi Kleen, James Clark, John Garry, linux-kernel, linux-perf-users Cc: Stephane Eranian On 3/18/2022 2:28 AM, Ian Rogers wrote: > The change: > https://github.com/intel/event-converter-for-linux-perf/commit/fc680410402e394eed6a1ebd909c9f649d3ed3ef > moved certain "other" type of events in to the cache topic. Update the > perf json files for this change. > > Signed-off-by: Ian Rogers <irogers@google.com> Reviewed-by: Zhengjun Xing <zhengjun.xing@linux.intel.com> > --- > .../pmu-events/arch/x86/skylake/cache.json | 36 +++++++++++++++++++ > .../pmu-events/arch/x86/skylake/other.json | 36 ------------------- > 2 files changed, 36 insertions(+), 36 deletions(-) > > diff --git a/tools/perf/pmu-events/arch/x86/skylake/cache.json b/tools/perf/pmu-events/arch/x86/skylake/cache.json > index 529c5e6e117f..c5d9a4ed10d7 100644 > --- a/tools/perf/pmu-events/arch/x86/skylake/cache.json > +++ b/tools/perf/pmu-events/arch/x86/skylake/cache.json > @@ -2937,5 +2937,41 @@ > "PublicDescription": "Counts the number of cache line split locks sent to the uncore.", > "SampleAfterValue": "100003", > "UMask": "0x10" > + }, > + { > + "BriefDescription": "Number of PREFETCHNTA instructions executed.", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3,4,5,6,7", > + "EventCode": "0x32", > + "EventName": "SW_PREFETCH_ACCESS.NTA", > + "SampleAfterValue": "2000003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Number of PREFETCHW instructions executed.", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3,4,5,6,7", > + "EventCode": "0x32", > + "EventName": "SW_PREFETCH_ACCESS.PREFETCHW", > + "SampleAfterValue": "2000003", > + "UMask": "0x8" > + }, > + { > + "BriefDescription": "Number of PREFETCHT0 instructions executed.", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3,4,5,6,7", > + "EventCode": "0x32", > + "EventName": "SW_PREFETCH_ACCESS.T0", > + "SampleAfterValue": "2000003", > + "UMask": "0x2" > + }, > + { > + "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3,4,5,6,7", > + "EventCode": "0x32", > + "EventName": "SW_PREFETCH_ACCESS.T1_T2", > + "SampleAfterValue": "2000003", > + "UMask": "0x4" > } > ] > \ No newline at end of file > diff --git a/tools/perf/pmu-events/arch/x86/skylake/other.json b/tools/perf/pmu-events/arch/x86/skylake/other.json > index 5c0e81f76a5b..4f4839024915 100644 > --- a/tools/perf/pmu-events/arch/x86/skylake/other.json > +++ b/tools/perf/pmu-events/arch/x86/skylake/other.json > @@ -16,41 +16,5 @@ > "EventName": "MEMORY_DISAMBIGUATION.HISTORY_RESET", > "SampleAfterValue": "2000003", > "UMask": "0x1" > - }, > - { > - "BriefDescription": "Number of PREFETCHNTA instructions executed.", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3,4,5,6,7", > - "EventCode": "0x32", > - "EventName": "SW_PREFETCH_ACCESS.NTA", > - "SampleAfterValue": "2000003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Number of PREFETCHW instructions executed.", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3,4,5,6,7", > - "EventCode": "0x32", > - "EventName": "SW_PREFETCH_ACCESS.PREFETCHW", > - "SampleAfterValue": "2000003", > - "UMask": "0x8" > - }, > - { > - "BriefDescription": "Number of PREFETCHT0 instructions executed.", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3,4,5,6,7", > - "EventCode": "0x32", > - "EventName": "SW_PREFETCH_ACCESS.T0", > - "SampleAfterValue": "2000003", > - "UMask": "0x2" > - }, > - { > - "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3,4,5,6,7", > - "EventCode": "0x32", > - "EventName": "SW_PREFETCH_ACCESS.T1_T2", > - "SampleAfterValue": "2000003", > - "UMask": "0x4" > } > ] > \ No newline at end of file -- Zhengjun Xing ^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 6/8] perf vendor events: Update events for SkylakeX 2022-03-17 18:28 [PATCH 1/8] perf vendor events: Update events for CascadelakeX Ian Rogers ` (3 preceding siblings ...) 2022-03-17 18:28 ` [PATCH 5/8] perf vendor events: Update events for Skylake Ian Rogers @ 2022-03-17 18:28 ` Ian Rogers 2022-03-18 9:21 ` Xing Zhengjun 2022-03-17 18:28 ` [PATCH 7/8] perf vendor events: Update events for Tigerlake Ian Rogers ` (3 subsequent siblings) 8 siblings, 1 reply; 18+ messages in thread From: Ian Rogers @ 2022-03-17 18:28 UTC (permalink / raw) To: Kan Liang, Zhengjun Xing, Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo, Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim, Maxime Coquelin, Alexandre Torgue, Andi Kleen, James Clark, John Garry, linux-kernel, linux-perf-users Cc: Stephane Eranian, Ian Rogers The change: https://github.com/intel/event-converter-for-linux-perf/commit/fc680410402e394eed6a1ebd909c9f649d3ed3ef moved certain "other" type of events in to the cache topic. Update the perf json files for this change. Signed-off-by: Ian Rogers <irogers@google.com> --- .../pmu-events/arch/x86/skylakex/cache.json | 36 +++++++++++++++++++ .../pmu-events/arch/x86/skylakex/other.json | 36 ------------------- 2 files changed, 36 insertions(+), 36 deletions(-) diff --git a/tools/perf/pmu-events/arch/x86/skylakex/cache.json b/tools/perf/pmu-events/arch/x86/skylakex/cache.json index 821d2f2a8f25..6639e18a7068 100644 --- a/tools/perf/pmu-events/arch/x86/skylakex/cache.json +++ b/tools/perf/pmu-events/arch/x86/skylakex/cache.json @@ -1686,5 +1686,41 @@ "PublicDescription": "Counts the number of cache line split locks sent to the uncore.", "SampleAfterValue": "100003", "UMask": "0x10" + }, + { + "BriefDescription": "Number of PREFETCHNTA instructions executed.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x32", + "EventName": "SW_PREFETCH_ACCESS.NTA", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of PREFETCHW instructions executed.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x32", + "EventName": "SW_PREFETCH_ACCESS.PREFETCHW", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Number of PREFETCHT0 instructions executed.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x32", + "EventName": "SW_PREFETCH_ACCESS.T0", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x32", + "EventName": "SW_PREFETCH_ACCESS.T1_T2", + "SampleAfterValue": "2000003", + "UMask": "0x4" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/skylakex/other.json b/tools/perf/pmu-events/arch/x86/skylakex/other.json index 8b344259176f..779654e62d97 100644 --- a/tools/perf/pmu-events/arch/x86/skylakex/other.json +++ b/tools/perf/pmu-events/arch/x86/skylakex/other.json @@ -76,41 +76,5 @@ "EventName": "MEMORY_DISAMBIGUATION.HISTORY_RESET", "SampleAfterValue": "2000003", "UMask": "0x1" - }, - { - "BriefDescription": "Number of PREFETCHNTA instructions executed.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x32", - "EventName": "SW_PREFETCH_ACCESS.NTA", - "SampleAfterValue": "2000003", - "UMask": "0x1" - }, - { - "BriefDescription": "Number of PREFETCHW instructions executed.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x32", - "EventName": "SW_PREFETCH_ACCESS.PREFETCHW", - "SampleAfterValue": "2000003", - "UMask": "0x8" - }, - { - "BriefDescription": "Number of PREFETCHT0 instructions executed.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x32", - "EventName": "SW_PREFETCH_ACCESS.T0", - "SampleAfterValue": "2000003", - "UMask": "0x2" - }, - { - "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x32", - "EventName": "SW_PREFETCH_ACCESS.T1_T2", - "SampleAfterValue": "2000003", - "UMask": "0x4" } ] \ No newline at end of file -- 2.35.1.894.gb6a874cedc-goog ^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PATCH 6/8] perf vendor events: Update events for SkylakeX 2022-03-17 18:28 ` [PATCH 6/8] perf vendor events: Update events for SkylakeX Ian Rogers @ 2022-03-18 9:21 ` Xing Zhengjun 0 siblings, 0 replies; 18+ messages in thread From: Xing Zhengjun @ 2022-03-18 9:21 UTC (permalink / raw) To: Ian Rogers, Kan Liang, Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo, Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim, Maxime Coquelin, Alexandre Torgue, Andi Kleen, James Clark, John Garry, linux-kernel, linux-perf-users Cc: Stephane Eranian On 3/18/2022 2:28 AM, Ian Rogers wrote: > The change: > https://github.com/intel/event-converter-for-linux-perf/commit/fc680410402e394eed6a1ebd909c9f649d3ed3ef > moved certain "other" type of events in to the cache topic. Update the > perf json files for this change. > > Signed-off-by: Ian Rogers <irogers@google.com> Reviewed-by: Zhengjun Xing <zhengjun.xing@linux.intel.com> > --- > .../pmu-events/arch/x86/skylakex/cache.json | 36 +++++++++++++++++++ > .../pmu-events/arch/x86/skylakex/other.json | 36 ------------------- > 2 files changed, 36 insertions(+), 36 deletions(-) > > diff --git a/tools/perf/pmu-events/arch/x86/skylakex/cache.json b/tools/perf/pmu-events/arch/x86/skylakex/cache.json > index 821d2f2a8f25..6639e18a7068 100644 > --- a/tools/perf/pmu-events/arch/x86/skylakex/cache.json > +++ b/tools/perf/pmu-events/arch/x86/skylakex/cache.json > @@ -1686,5 +1686,41 @@ > "PublicDescription": "Counts the number of cache line split locks sent to the uncore.", > "SampleAfterValue": "100003", > "UMask": "0x10" > + }, > + { > + "BriefDescription": "Number of PREFETCHNTA instructions executed.", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3,4,5,6,7", > + "EventCode": "0x32", > + "EventName": "SW_PREFETCH_ACCESS.NTA", > + "SampleAfterValue": "2000003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Number of PREFETCHW instructions executed.", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3,4,5,6,7", > + "EventCode": "0x32", > + "EventName": "SW_PREFETCH_ACCESS.PREFETCHW", > + "SampleAfterValue": "2000003", > + "UMask": "0x8" > + }, > + { > + "BriefDescription": "Number of PREFETCHT0 instructions executed.", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3,4,5,6,7", > + "EventCode": "0x32", > + "EventName": "SW_PREFETCH_ACCESS.T0", > + "SampleAfterValue": "2000003", > + "UMask": "0x2" > + }, > + { > + "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3,4,5,6,7", > + "EventCode": "0x32", > + "EventName": "SW_PREFETCH_ACCESS.T1_T2", > + "SampleAfterValue": "2000003", > + "UMask": "0x4" > } > ] > \ No newline at end of file > diff --git a/tools/perf/pmu-events/arch/x86/skylakex/other.json b/tools/perf/pmu-events/arch/x86/skylakex/other.json > index 8b344259176f..779654e62d97 100644 > --- a/tools/perf/pmu-events/arch/x86/skylakex/other.json > +++ b/tools/perf/pmu-events/arch/x86/skylakex/other.json > @@ -76,41 +76,5 @@ > "EventName": "MEMORY_DISAMBIGUATION.HISTORY_RESET", > "SampleAfterValue": "2000003", > "UMask": "0x1" > - }, > - { > - "BriefDescription": "Number of PREFETCHNTA instructions executed.", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3,4,5,6,7", > - "EventCode": "0x32", > - "EventName": "SW_PREFETCH_ACCESS.NTA", > - "SampleAfterValue": "2000003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Number of PREFETCHW instructions executed.", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3,4,5,6,7", > - "EventCode": "0x32", > - "EventName": "SW_PREFETCH_ACCESS.PREFETCHW", > - "SampleAfterValue": "2000003", > - "UMask": "0x8" > - }, > - { > - "BriefDescription": "Number of PREFETCHT0 instructions executed.", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3,4,5,6,7", > - "EventCode": "0x32", > - "EventName": "SW_PREFETCH_ACCESS.T0", > - "SampleAfterValue": "2000003", > - "UMask": "0x2" > - }, > - { > - "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3,4,5,6,7", > - "EventCode": "0x32", > - "EventName": "SW_PREFETCH_ACCESS.T1_T2", > - "SampleAfterValue": "2000003", > - "UMask": "0x4" > } > ] > \ No newline at end of file -- Zhengjun Xing ^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 7/8] perf vendor events: Update events for Tigerlake 2022-03-17 18:28 [PATCH 1/8] perf vendor events: Update events for CascadelakeX Ian Rogers ` (4 preceding siblings ...) 2022-03-17 18:28 ` [PATCH 6/8] perf vendor events: Update events for SkylakeX Ian Rogers @ 2022-03-17 18:28 ` Ian Rogers 2022-03-18 9:22 ` Xing Zhengjun 2022-03-17 18:28 ` [PATCH 8/8] perf vendor events: Update events for TremontX Ian Rogers ` (2 subsequent siblings) 8 siblings, 1 reply; 18+ messages in thread From: Ian Rogers @ 2022-03-17 18:28 UTC (permalink / raw) To: Kan Liang, Zhengjun Xing, Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo, Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim, Maxime Coquelin, Alexandre Torgue, Andi Kleen, James Clark, John Garry, linux-kernel, linux-perf-users Cc: Stephane Eranian, Ian Rogers The change: https://github.com/intel/event-converter-for-linux-perf/commit/fc680410402e394eed6a1ebd909c9f649d3ed3ef moved certain "other" type of events in to the cache and pipeline topics. Update the perf json files for this change. Signed-off-by: Ian Rogers <irogers@google.com> --- .../pmu-events/arch/x86/tigerlake/cache.json | 86 ++++++++++++ .../pmu-events/arch/x86/tigerlake/other.json | 129 ------------------ .../arch/x86/tigerlake/pipeline.json | 43 ++++++ 3 files changed, 129 insertions(+), 129 deletions(-) diff --git a/tools/perf/pmu-events/arch/x86/tigerlake/cache.json b/tools/perf/pmu-events/arch/x86/tigerlake/cache.json index 543a3298f86f..0569b2c704ca 100644 --- a/tools/perf/pmu-events/arch/x86/tigerlake/cache.json +++ b/tools/perf/pmu-events/arch/x86/tigerlake/cache.json @@ -493,6 +493,48 @@ "SampleAfterValue": "50021", "UMask": "0x20" }, + { + "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0001", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8003C0001", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0002", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, { "BriefDescription": "Demand and prefetch data reads", "CollectPEBSRecord": "2", @@ -627,5 +669,49 @@ "PublicDescription": "Counts the cycles for which the thread is active and the superQ cannot take any more entries.", "SampleAfterValue": "100003", "UMask": "0x4" + }, + { + "BriefDescription": "Number of PREFETCHNTA instructions executed.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "SW_PREFETCH_ACCESS.NTA", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of PREFETCHNTA instructions executed.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of PREFETCHW instructions executed.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "SW_PREFETCH_ACCESS.PREFETCHW", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of PREFETCHW instructions executed.", + "SampleAfterValue": "100003", + "UMask": "0x8" + }, + { + "BriefDescription": "Number of PREFETCHT0 instructions executed.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "SW_PREFETCH_ACCESS.T0", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of PREFETCHT0 instructions executed.", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "SW_PREFETCH_ACCESS.T1_T2", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of PREFETCHT1 or PREFETCHT2 instructions executed.", + "SampleAfterValue": "100003", + "UMask": "0x4" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/tigerlake/other.json b/tools/perf/pmu-events/arch/x86/tigerlake/other.json index b1143fe74246..304cd09fe159 100644 --- a/tools/perf/pmu-events/arch/x86/tigerlake/other.json +++ b/tools/perf/pmu-events/arch/x86/tigerlake/other.json @@ -43,48 +43,6 @@ "SampleAfterValue": "200003", "UMask": "0x20" }, - { - "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x10003C0001", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x8003C0001", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x10003C0002", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, { "BriefDescription": "Counts streaming stores that have any type of response.", "CollectPEBSRecord": "2", @@ -98,92 +56,5 @@ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" - }, - { - "BriefDescription": "Number of PREFETCHNTA instructions executed.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x32", - "EventName": "SW_PREFETCH_ACCESS.NTA", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of PREFETCHNTA instructions executed.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Number of PREFETCHW instructions executed.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x32", - "EventName": "SW_PREFETCH_ACCESS.PREFETCHW", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of PREFETCHW instructions executed.", - "SampleAfterValue": "100003", - "UMask": "0x8" - }, - { - "BriefDescription": "Number of PREFETCHT0 instructions executed.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x32", - "EventName": "SW_PREFETCH_ACCESS.T0", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of PREFETCHT0 instructions executed.", - "SampleAfterValue": "100003", - "UMask": "0x2" - }, - { - "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x32", - "EventName": "SW_PREFETCH_ACCESS.T1_T2", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of PREFETCHT1 or PREFETCHT2 instructions executed.", - "SampleAfterValue": "100003", - "UMask": "0x4" - }, - { - "BriefDescription": "TMA slots where no uops were being issued due to lack of back-end resources.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xa4", - "EventName": "TOPDOWN.BACKEND_BOUND_SLOTS", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of Top-down Microarchitecture Analysis (TMA) method's slots where no micro-operations were being issued from front-end to back-end of the machine due to lack of back-end resources.", - "SampleAfterValue": "10000003", - "UMask": "0x2" - }, - { - "BriefDescription": "TMA slots wasted due to incorrect speculation by branch mispredictions", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xa4", - "EventName": "TOPDOWN.BR_MISPREDICT_SLOTS", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Number of TMA slots that were wasted due to incorrect speculation by branch mispredictions. This event estimates number of operations that were issued but not retired from the specualtive path as well as the out-of-order engine recovery past a branch misprediction.", - "SampleAfterValue": "10000003", - "UMask": "0x8" - }, - { - "BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - architectural event", - "CollectPEBSRecord": "2", - "Counter": "Fixed counter 3", - "EventName": "TOPDOWN.SLOTS", - "PEBScounters": "35", - "PublicDescription": "Number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TMA). The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core. Software can use this event as the denominator for the top-level metrics of the TMA method. This architectural event is counted on a designated fixed counter (Fixed Counter 3).", - "SampleAfterValue": "10000003", - "UMask": "0x4" - }, - { - "BriefDescription": "TMA slots available for an unhalted logical processor. General counter - architectural event", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xa4", - "EventName": "TOPDOWN.SLOTS_P", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core.", - "SampleAfterValue": "10000003", - "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/tigerlake/pipeline.json b/tools/perf/pmu-events/arch/x86/tigerlake/pipeline.json index 4dc3a16e3da4..d436775c80db 100644 --- a/tools/perf/pmu-events/arch/x86/tigerlake/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/tigerlake/pipeline.json @@ -711,6 +711,49 @@ "SampleAfterValue": "100003", "UMask": "0x1" }, + { + "BriefDescription": "TMA slots where no uops were being issued due to lack of back-end resources.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xa4", + "EventName": "TOPDOWN.BACKEND_BOUND_SLOTS", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts the number of Top-down Microarchitecture Analysis (TMA) method's slots where no micro-operations were being issued from front-end to back-end of the machine due to lack of back-end resources.", + "SampleAfterValue": "10000003", + "UMask": "0x2" + }, + { + "BriefDescription": "TMA slots wasted due to incorrect speculation by branch mispredictions", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xa4", + "EventName": "TOPDOWN.BR_MISPREDICT_SLOTS", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Number of TMA slots that were wasted due to incorrect speculation by branch mispredictions. This event estimates number of operations that were issued but not retired from the specualtive path as well as the out-of-order engine recovery past a branch misprediction.", + "SampleAfterValue": "10000003", + "UMask": "0x8" + }, + { + "BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - architectural event", + "CollectPEBSRecord": "2", + "Counter": "Fixed counter 3", + "EventName": "TOPDOWN.SLOTS", + "PEBScounters": "35", + "PublicDescription": "Number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TMA). The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core. Software can use this event as the denominator for the top-level metrics of the TMA method. This architectural event is counted on a designated fixed counter (Fixed Counter 3).", + "SampleAfterValue": "10000003", + "UMask": "0x4" + }, + { + "BriefDescription": "TMA slots available for an unhalted logical processor. General counter - architectural event", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xa4", + "EventName": "TOPDOWN.SLOTS_P", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core.", + "SampleAfterValue": "10000003", + "UMask": "0x1" + }, { "BriefDescription": "Number of uops decoded out of instructions exclusively fetched by decoder 0", "CollectPEBSRecord": "2", -- 2.35.1.894.gb6a874cedc-goog ^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PATCH 7/8] perf vendor events: Update events for Tigerlake 2022-03-17 18:28 ` [PATCH 7/8] perf vendor events: Update events for Tigerlake Ian Rogers @ 2022-03-18 9:22 ` Xing Zhengjun 0 siblings, 0 replies; 18+ messages in thread From: Xing Zhengjun @ 2022-03-18 9:22 UTC (permalink / raw) To: Ian Rogers, Kan Liang, Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo, Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim, Maxime Coquelin, Alexandre Torgue, Andi Kleen, James Clark, John Garry, linux-kernel, linux-perf-users Cc: Stephane Eranian On 3/18/2022 2:28 AM, Ian Rogers wrote: > The change: > https://github.com/intel/event-converter-for-linux-perf/commit/fc680410402e394eed6a1ebd909c9f649d3ed3ef > moved certain "other" type of events in to the cache and pipeline topics. > Update the perf json files for this change. > > Signed-off-by: Ian Rogers <irogers@google.com> Reviewed-by: Zhengjun Xing <zhengjun.xing@linux.intel.com> > --- > .../pmu-events/arch/x86/tigerlake/cache.json | 86 ++++++++++++ > .../pmu-events/arch/x86/tigerlake/other.json | 129 ------------------ > .../arch/x86/tigerlake/pipeline.json | 43 ++++++ > 3 files changed, 129 insertions(+), 129 deletions(-) > > diff --git a/tools/perf/pmu-events/arch/x86/tigerlake/cache.json b/tools/perf/pmu-events/arch/x86/tigerlake/cache.json > index 543a3298f86f..0569b2c704ca 100644 > --- a/tools/perf/pmu-events/arch/x86/tigerlake/cache.json > +++ b/tools/perf/pmu-events/arch/x86/tigerlake/cache.json > @@ -493,6 +493,48 @@ > "SampleAfterValue": "50021", > "UMask": "0x20" > }, > + { > + "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x10003C0001", > + "Offcore": "1", > + "PEBScounters": "0,1,2,3", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x8003C0001", > + "Offcore": "1", > + "PEBScounters": "0,1,2,3", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x10003C0002", > + "Offcore": "1", > + "PEBScounters": "0,1,2,3", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > { > "BriefDescription": "Demand and prefetch data reads", > "CollectPEBSRecord": "2", > @@ -627,5 +669,49 @@ > "PublicDescription": "Counts the cycles for which the thread is active and the superQ cannot take any more entries.", > "SampleAfterValue": "100003", > "UMask": "0x4" > + }, > + { > + "BriefDescription": "Number of PREFETCHNTA instructions executed.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0x32", > + "EventName": "SW_PREFETCH_ACCESS.NTA", > + "PEBScounters": "0,1,2,3", > + "PublicDescription": "Counts the number of PREFETCHNTA instructions executed.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Number of PREFETCHW instructions executed.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0x32", > + "EventName": "SW_PREFETCH_ACCESS.PREFETCHW", > + "PEBScounters": "0,1,2,3", > + "PublicDescription": "Counts the number of PREFETCHW instructions executed.", > + "SampleAfterValue": "100003", > + "UMask": "0x8" > + }, > + { > + "BriefDescription": "Number of PREFETCHT0 instructions executed.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0x32", > + "EventName": "SW_PREFETCH_ACCESS.T0", > + "PEBScounters": "0,1,2,3", > + "PublicDescription": "Counts the number of PREFETCHT0 instructions executed.", > + "SampleAfterValue": "100003", > + "UMask": "0x2" > + }, > + { > + "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0x32", > + "EventName": "SW_PREFETCH_ACCESS.T1_T2", > + "PEBScounters": "0,1,2,3", > + "PublicDescription": "Counts the number of PREFETCHT1 or PREFETCHT2 instructions executed.", > + "SampleAfterValue": "100003", > + "UMask": "0x4" > } > ] > \ No newline at end of file > diff --git a/tools/perf/pmu-events/arch/x86/tigerlake/other.json b/tools/perf/pmu-events/arch/x86/tigerlake/other.json > index b1143fe74246..304cd09fe159 100644 > --- a/tools/perf/pmu-events/arch/x86/tigerlake/other.json > +++ b/tools/perf/pmu-events/arch/x86/tigerlake/other.json > @@ -43,48 +43,6 @@ > "SampleAfterValue": "200003", > "UMask": "0x20" > }, > - { > - "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10003C0001", > - "Offcore": "1", > - "PEBScounters": "0,1,2,3", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x8003C0001", > - "Offcore": "1", > - "PEBScounters": "0,1,2,3", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10003C0002", > - "Offcore": "1", > - "PEBScounters": "0,1,2,3", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > { > "BriefDescription": "Counts streaming stores that have any type of response.", > "CollectPEBSRecord": "2", > @@ -98,92 +56,5 @@ > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > - }, > - { > - "BriefDescription": "Number of PREFETCHNTA instructions executed.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0x32", > - "EventName": "SW_PREFETCH_ACCESS.NTA", > - "PEBScounters": "0,1,2,3", > - "PublicDescription": "Counts the number of PREFETCHNTA instructions executed.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Number of PREFETCHW instructions executed.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0x32", > - "EventName": "SW_PREFETCH_ACCESS.PREFETCHW", > - "PEBScounters": "0,1,2,3", > - "PublicDescription": "Counts the number of PREFETCHW instructions executed.", > - "SampleAfterValue": "100003", > - "UMask": "0x8" > - }, > - { > - "BriefDescription": "Number of PREFETCHT0 instructions executed.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0x32", > - "EventName": "SW_PREFETCH_ACCESS.T0", > - "PEBScounters": "0,1,2,3", > - "PublicDescription": "Counts the number of PREFETCHT0 instructions executed.", > - "SampleAfterValue": "100003", > - "UMask": "0x2" > - }, > - { > - "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0x32", > - "EventName": "SW_PREFETCH_ACCESS.T1_T2", > - "PEBScounters": "0,1,2,3", > - "PublicDescription": "Counts the number of PREFETCHT1 or PREFETCHT2 instructions executed.", > - "SampleAfterValue": "100003", > - "UMask": "0x4" > - }, > - { > - "BriefDescription": "TMA slots where no uops were being issued due to lack of back-end resources.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3,4,5,6,7", > - "EventCode": "0xa4", > - "EventName": "TOPDOWN.BACKEND_BOUND_SLOTS", > - "PEBScounters": "0,1,2,3,4,5,6,7", > - "PublicDescription": "Counts the number of Top-down Microarchitecture Analysis (TMA) method's slots where no micro-operations were being issued from front-end to back-end of the machine due to lack of back-end resources.", > - "SampleAfterValue": "10000003", > - "UMask": "0x2" > - }, > - { > - "BriefDescription": "TMA slots wasted due to incorrect speculation by branch mispredictions", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3,4,5,6,7", > - "EventCode": "0xa4", > - "EventName": "TOPDOWN.BR_MISPREDICT_SLOTS", > - "PEBScounters": "0,1,2,3,4,5,6,7", > - "PublicDescription": "Number of TMA slots that were wasted due to incorrect speculation by branch mispredictions. This event estimates number of operations that were issued but not retired from the specualtive path as well as the out-of-order engine recovery past a branch misprediction.", > - "SampleAfterValue": "10000003", > - "UMask": "0x8" > - }, > - { > - "BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - architectural event", > - "CollectPEBSRecord": "2", > - "Counter": "Fixed counter 3", > - "EventName": "TOPDOWN.SLOTS", > - "PEBScounters": "35", > - "PublicDescription": "Number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TMA). The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core. Software can use this event as the denominator for the top-level metrics of the TMA method. This architectural event is counted on a designated fixed counter (Fixed Counter 3).", > - "SampleAfterValue": "10000003", > - "UMask": "0x4" > - }, > - { > - "BriefDescription": "TMA slots available for an unhalted logical processor. General counter - architectural event", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3,4,5,6,7", > - "EventCode": "0xa4", > - "EventName": "TOPDOWN.SLOTS_P", > - "PEBScounters": "0,1,2,3,4,5,6,7", > - "PublicDescription": "Counts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core.", > - "SampleAfterValue": "10000003", > - "UMask": "0x1" > } > ] > \ No newline at end of file > diff --git a/tools/perf/pmu-events/arch/x86/tigerlake/pipeline.json b/tools/perf/pmu-events/arch/x86/tigerlake/pipeline.json > index 4dc3a16e3da4..d436775c80db 100644 > --- a/tools/perf/pmu-events/arch/x86/tigerlake/pipeline.json > +++ b/tools/perf/pmu-events/arch/x86/tigerlake/pipeline.json > @@ -711,6 +711,49 @@ > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > + { > + "BriefDescription": "TMA slots where no uops were being issued due to lack of back-end resources.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5,6,7", > + "EventCode": "0xa4", > + "EventName": "TOPDOWN.BACKEND_BOUND_SLOTS", > + "PEBScounters": "0,1,2,3,4,5,6,7", > + "PublicDescription": "Counts the number of Top-down Microarchitecture Analysis (TMA) method's slots where no micro-operations were being issued from front-end to back-end of the machine due to lack of back-end resources.", > + "SampleAfterValue": "10000003", > + "UMask": "0x2" > + }, > + { > + "BriefDescription": "TMA slots wasted due to incorrect speculation by branch mispredictions", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5,6,7", > + "EventCode": "0xa4", > + "EventName": "TOPDOWN.BR_MISPREDICT_SLOTS", > + "PEBScounters": "0,1,2,3,4,5,6,7", > + "PublicDescription": "Number of TMA slots that were wasted due to incorrect speculation by branch mispredictions. This event estimates number of operations that were issued but not retired from the specualtive path as well as the out-of-order engine recovery past a branch misprediction.", > + "SampleAfterValue": "10000003", > + "UMask": "0x8" > + }, > + { > + "BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - architectural event", > + "CollectPEBSRecord": "2", > + "Counter": "Fixed counter 3", > + "EventName": "TOPDOWN.SLOTS", > + "PEBScounters": "35", > + "PublicDescription": "Number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TMA). The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core. Software can use this event as the denominator for the top-level metrics of the TMA method. This architectural event is counted on a designated fixed counter (Fixed Counter 3).", > + "SampleAfterValue": "10000003", > + "UMask": "0x4" > + }, > + { > + "BriefDescription": "TMA slots available for an unhalted logical processor. General counter - architectural event", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5,6,7", > + "EventCode": "0xa4", > + "EventName": "TOPDOWN.SLOTS_P", > + "PEBScounters": "0,1,2,3,4,5,6,7", > + "PublicDescription": "Counts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core.", > + "SampleAfterValue": "10000003", > + "UMask": "0x1" > + }, > { > "BriefDescription": "Number of uops decoded out of instructions exclusively fetched by decoder 0", > "CollectPEBSRecord": "2", -- Zhengjun Xing ^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 8/8] perf vendor events: Update events for TremontX 2022-03-17 18:28 [PATCH 1/8] perf vendor events: Update events for CascadelakeX Ian Rogers ` (5 preceding siblings ...) 2022-03-17 18:28 ` [PATCH 7/8] perf vendor events: Update events for Tigerlake Ian Rogers @ 2022-03-17 18:28 ` Ian Rogers 2022-03-18 9:26 ` Xing Zhengjun 2022-03-18 9:09 ` [PATCH 1/8] perf vendor events: Update events for CascadelakeX Xing Zhengjun 2022-03-18 9:14 ` John Garry 8 siblings, 1 reply; 18+ messages in thread From: Ian Rogers @ 2022-03-17 18:28 UTC (permalink / raw) To: Kan Liang, Zhengjun Xing, Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo, Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim, Maxime Coquelin, Alexandre Torgue, Andi Kleen, James Clark, John Garry, linux-kernel, linux-perf-users Cc: Stephane Eranian, Ian Rogers Move from v1.17 to v1.19. The change: https://github.com/intel/event-converter-for-linux-perf/commit/fc680410402e394eed6a1ebd909c9f649d3ed3ef moved certain "other" type of events in to the cache, memory and pipeline topics. Update the perf json files for this change. Signed-off-by: Ian Rogers <irogers@google.com> --- .../pmu-events/arch/x86/tremontx/cache.json | 839 +++++++++- .../arch/x86/tremontx/floating-point.json | 12 + .../pmu-events/arch/x86/tremontx/memory.json | 59 +- .../pmu-events/arch/x86/tremontx/other.json | 1362 ++--------------- .../arch/x86/tremontx/pipeline.json | 320 ++++ .../arch/x86/tremontx/uncore-other.json | 1 + .../arch/x86/tremontx/virtual-memory.json | 11 + 7 files changed, 1329 insertions(+), 1275 deletions(-) diff --git a/tools/perf/pmu-events/arch/x86/tremontx/cache.json b/tools/perf/pmu-events/arch/x86/tremontx/cache.json index 615b516ea021..e142f294b42e 100644 --- a/tools/perf/pmu-events/arch/x86/tremontx/cache.json +++ b/tools/perf/pmu-events/arch/x86/tremontx/cache.json @@ -33,6 +33,53 @@ "PublicDescription": "Counts the number of demand and prefetch transactions that the External Queue (XQ) rejects due to a full or near full condition which likely indicates back pressure from the IDI link. The XQ may reject transactions from the L2Q (non-cacheable requests), BBL (L2 misses) and WOB (L2 write-back victims).", "SampleAfterValue": "200003" }, + { + "BriefDescription": "Counts the total number of L2 Cache accesses. Counts on a per core basis.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_REQUEST.ALL", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the total number of L2 Cache Accesses, includes hits, misses, rejects front door requests for CRd/DRd/RFO/ItoM/L2 Prefetches only. Counts on a per core basis.", + "SampleAfterValue": "200003" + }, + { + "BriefDescription": "Counts the number of L2 Cache accesses that resulted in a hit. Counts on a per core basis.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_REQUEST.HIT", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of L2 Cache accesses that resulted in a hit from a front door request only (does not include rejects or recycles), Counts on a per core basis.", + "SampleAfterValue": "200003", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts the number of L2 Cache accesses that resulted in a miss. Counts on a per core basis.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_REQUEST.MISS", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of L2 Cache accesses that resulted in a miss from a front door request only (does not include rejects or recycles). Counts on a per core basis.", + "SampleAfterValue": "200003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the number of L2 Cache accesses that miss the L2 and get rejected. Counts on a per core basis.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_REQUEST.REJECTS", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of L2 Cache accesses that miss the L2 and get BBL reject short and long rejects (includes those counted in L2_reject_XQ.any). Counts on a per core basis.", + "SampleAfterValue": "200003", + "UMask": "0x4" + }, { "BriefDescription": "Counts the number of cacheable memory requests that miss in the LLC. Counts on a per core basis.", "CollectPEBSRecord": "2", @@ -59,6 +106,7 @@ }, { "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).", + "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "MEM_BOUND_STALLS.IFETCH", @@ -86,7 +134,7 @@ "EventName": "MEM_BOUND_STALLS.IFETCH_L2_HIT", "PDIR_COUNTER": "na", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of cycles a core is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) access which hit in the L2 cache.", + "PublicDescription": "Counts the number of cycles the core is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) access which hit in the L2 cache.", "SampleAfterValue": "200003", "UMask": "0x8" }, @@ -98,7 +146,7 @@ "EventName": "MEM_BOUND_STALLS.IFETCH_LLC_HIT", "PDIR_COUNTER": "na", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of cycles a core is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) access which hit in the Last Level Cache (LLC) or other core with HITE/F/M.", + "PublicDescription": "Counts the number of cycles the core is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) access which hit in the Last Level Cache (LLC) or other core with HITE/F/M.", "SampleAfterValue": "200003", "UMask": "0x10" }, @@ -131,7 +179,6 @@ "EventName": "MEM_BOUND_STALLS.LOAD_L2_HIT", "PDIR_COUNTER": "na", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of cycles a core is stalled due to a demand load which hit in the L2 cache.", "SampleAfterValue": "200003", "UMask": "0x1" }, @@ -143,7 +190,7 @@ "EventName": "MEM_BOUND_STALLS.LOAD_LLC_HIT", "PDIR_COUNTER": "na", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of cycles a core is stalled due to a demand load which hit in the Last Level Cache (LLC) or other core with HITE/F/M.", + "PublicDescription": "Counts the number of cycles the core is stalled due to a demand load which hit in the Last Level Cache (LLC) or other core with HITE/F/M.", "SampleAfterValue": "200003", "UMask": "0x2" }, @@ -241,6 +288,18 @@ "SampleAfterValue": "200003", "UMask": "0x4" }, + { + "BriefDescription": "Counts the number of memory uops retired. A single uop that performs both a load AND a store will be counted as 1, not 2 (e.g. ADD [mem], CONST)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.ALL", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0x83" + }, { "BriefDescription": "Counts the number of load uops retired.", "CollectPEBSRecord": "2", @@ -267,6 +326,18 @@ "SampleAfterValue": "200003", "UMask": "0x82" }, + { + "BriefDescription": "Counts the number of load uops retired that performed one or more locks.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0x21" + }, { "BriefDescription": "Counts the number of memory uops retired that were splits.", "CollectPEBSRecord": "2", @@ -291,6 +362,766 @@ "SampleAfterValue": "200003", "UMask": "0x41" }, + { + "BriefDescription": "Counts the number of retired split store uops.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0x42" + }, + { + "BriefDescription": "Counts all code reads that were supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.ALL_CODE_RD.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1F803C0044", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.ALL_CODE_RD.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0044", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.ALL_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003C0044", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.ALL_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8003C0044", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was sent but the snoop missed.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.ALL_CODE_RD.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003C0044", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all code reads that were supplied by the L3 cache where no snoop was needed to satisfy the request.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.ALL_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003C0044", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts modified writebacks from L1 cache and L2 cache that were supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.COREWB_M.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3001F803C0000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1F803C0004", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0004", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003C0004", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8003C0004", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent but the snoop missed.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003C0004", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where no snoop was needed to satisfy the request.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003C0004", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1F803C0001", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0001", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003C0001", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8003C0001", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where a snoop was sent but the snoop missed.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003C0001", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where no snoop was needed to satisfy the request.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003C0001", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1F803C0001", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HITM", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0001", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_NO_FWD", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003C0001", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8003C0001", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_MISS", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003C0001", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_NOT_NEEDED", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003C0001", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_RFO.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1F803C0002", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0002", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003C0002", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8003C0002", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent but the snoop missed.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003C0002", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where no snoop was needed to satisfy the request.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003C0002", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts streaming stores which modify a full 64 byte cacheline that were supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.FULL_STREAMING_WR.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x801F803C0000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L1 data cache hardware prefetches and software prefetches (except PREFETCHW and PFRFO) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0400", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1F803C0040", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0040", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003C0040", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8003C0040", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent but the snoop missed.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003C0040", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where no snoop was needed to satisfy the request.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003C0040", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1F803C0010", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0010", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003C0010", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8003C0010", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent but the snoop missed.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003C0010", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where no snoop was needed to satisfy the request.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003C0010", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_RFO.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1F803C0020", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0020", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003C0020", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8003C0020", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent but the snoop missed.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003C0020", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where no snoop was needed to satisfy the request.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003C0020", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts modified writebacks from L1 cache that miss the L2 cache that were supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.L1WB_M.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1001F803C0000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts modified writeBacks from L2 cache that miss the L3 cache that were supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.L2WB_M.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2001F803C0000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts streaming stores which modify only part of a 64 byte cacheline that were supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.PARTIAL_STREAMING_WR.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x401F803C0000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.READS_TO_CORE.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1F803C0477", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0477", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003C0477", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_WITH_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8003C0477", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where a snoop was sent but the snoop missed.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003C0477", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where no snoop was needed to satisfy the request.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003C0477", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts streaming stores that were supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.STREAMING_WR.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1F803C0800", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts uncached memory reads that were supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.UC_RD.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x101F803C0000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts uncached memory reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.UC_RD.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1010003C0000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts uncached memory reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.UC_RD.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1004003C0000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts uncached memory reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.UC_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1008003C0000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts uncached memory reads that were supplied by the L3 cache where a snoop was sent but the snoop missed.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.UC_RD.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1002003C0000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts uncached memory reads that were supplied by the L3 cache where no snoop was needed to satisfy the request.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.UC_RD.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1001003C0000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts uncached memory writes that were supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.UC_WR.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x201F803C0000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, { "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to instruction cache misses.", "CollectPEBSRecord": "2", diff --git a/tools/perf/pmu-events/arch/x86/tremontx/floating-point.json b/tools/perf/pmu-events/arch/x86/tremontx/floating-point.json index 2515b9aa6e66..c7780fa54689 100644 --- a/tools/perf/pmu-events/arch/x86/tremontx/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/tremontx/floating-point.json @@ -10,6 +10,18 @@ "SampleAfterValue": "200003", "UMask": "0x2" }, + { + "BriefDescription": "Counts the number of floating point operations retired that required microcode assist.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xc3", + "EventName": "MACHINE_CLEARS.FP_ASSIST", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of floating point operations retired that required microcode assist, which is not a reflection of the number of FP operations, instructions or uops.", + "SampleAfterValue": "20003", + "UMask": "0x4" + }, { "BriefDescription": "Counts the number of floating point divide uops retired (x87 and SSE, including x87 sqrt).", "CollectPEBSRecord": "2", diff --git a/tools/perf/pmu-events/arch/x86/tremontx/memory.json b/tools/perf/pmu-events/arch/x86/tremontx/memory.json index 4486f78035d8..76eaefafdc89 100644 --- a/tools/perf/pmu-events/arch/x86/tremontx/memory.json +++ b/tools/perf/pmu-events/arch/x86/tremontx/memory.json @@ -10,6 +10,28 @@ "SampleAfterValue": "20003", "UMask": "0x2" }, + { + "BriefDescription": "Counts the number of misaligned load uops that are 4K page splits.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "MISALIGN_MEM_REF.LOAD_PAGE_SPLIT", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts the number of misaligned store uops that are 4K page splits.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "MISALIGN_MEM_REF.STORE_PAGE_SPLIT", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0x4" + }, { "BriefDescription": "Counts all code reads that were not supplied by the L3 cache.", "Counter": "0,1,2,3", @@ -18,7 +40,6 @@ "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2184000044", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -30,7 +51,6 @@ "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2184000044", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -42,7 +62,6 @@ "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3002184000000", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -54,7 +73,6 @@ "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3002184000000", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -66,7 +84,6 @@ "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2184000004", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -78,7 +95,6 @@ "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2184000004", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -90,7 +106,6 @@ "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2184000001", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -102,7 +117,6 @@ "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2184000001", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -114,7 +128,6 @@ "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2184000001", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -126,7 +139,6 @@ "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2184000001", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -138,7 +150,6 @@ "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2184000002", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -150,7 +161,6 @@ "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2184000002", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -162,7 +172,6 @@ "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x802184000000", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -174,7 +183,6 @@ "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x802184000000", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -186,7 +194,6 @@ "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2184000040", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -198,7 +205,6 @@ "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2184000040", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -210,7 +216,6 @@ "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2184000010", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -222,7 +227,6 @@ "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2184000010", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -234,7 +238,6 @@ "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2184000020", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -246,7 +249,6 @@ "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2184000020", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -258,7 +260,6 @@ "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1002184000000", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -270,7 +271,6 @@ "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1002184000000", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -282,7 +282,6 @@ "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2002184000000", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -294,7 +293,6 @@ "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2002184000000", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -306,7 +304,6 @@ "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2184008000", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -318,7 +315,6 @@ "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2184008000", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -330,7 +326,6 @@ "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x402184000000", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -342,7 +337,6 @@ "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x402184000000", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -354,7 +348,6 @@ "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2184000470", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -366,7 +359,6 @@ "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2184000477", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -378,7 +370,6 @@ "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2184000477", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -390,7 +381,6 @@ "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2184000800", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -402,7 +392,6 @@ "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x2184000800", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -414,7 +403,6 @@ "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x102184000000", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -426,7 +414,6 @@ "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x102184000000", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -438,7 +425,6 @@ "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x202184000000", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -450,7 +436,6 @@ "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x202184000000", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" } diff --git a/tools/perf/pmu-events/arch/x86/tremontx/other.json b/tools/perf/pmu-events/arch/x86/tremontx/other.json index 522eb795574d..4f20f45a4898 100644 --- a/tools/perf/pmu-events/arch/x86/tremontx/other.json +++ b/tools/perf/pmu-events/arch/x86/tremontx/other.json @@ -152,7 +152,6 @@ "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10044", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -164,79 +163,6 @@ "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x184000044", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all code reads that were supplied by the L3 cache.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.ALL_CODE_RD.L3_HIT", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1F803C0044", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.ALL_CODE_RD.L3_HIT.SNOOP_HITM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x10003C0044", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.ALL_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x4003C0044", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.ALL_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x8003C0044", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was sent but the snoop missed.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.ALL_CODE_RD.L3_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x2003C0044", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all code reads that were supplied by the L3 cache where no snoop was needed to satisfy the request.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.ALL_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1003C0044", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -248,7 +174,6 @@ "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x184000044", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -260,7 +185,6 @@ "MSRIndex": "0x1a6", "MSRValue": "0x8000000000000044", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -272,19 +196,6 @@ "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x3000000010000", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts modified writebacks from L1 cache and L2 cache that were supplied by the L3 cache.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.COREWB_M.L3_HIT", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3001F803C0000", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -296,7 +207,6 @@ "MSRIndex": "0x1a6", "MSRValue": "0x8003000000000000", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -308,7 +218,6 @@ "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10004", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -320,1473 +229,458 @@ "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x184000004", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1F803C0004", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.", + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM.", "Counter": "0,1,2,3", "EventCode": "0XB7", - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM", + "EventName": "OCR.DEMAND_CODE_RD.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x10003C0004", + "MSRValue": "0x184000004", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.", + "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that have any type of response.", "Counter": "0,1,2,3", "EventCode": "0XB7", - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD", + "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x4003C0004", + "MSRValue": "0x10001", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.", + "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by DRAM.", "Counter": "0,1,2,3", "EventCode": "0XB7", - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.DRAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x8003C0004", + "MSRValue": "0x184000001", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent but the snoop missed.", + "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by DRAM.", "Counter": "0,1,2,3", "EventCode": "0XB7", - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS", + "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x2003C0004", + "MSRValue": "0x184000001", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where no snoop was needed to satisfy the request.", + "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency).", "Counter": "0,1,2,3", "EventCode": "0XB7", - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1003C0004", + "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x8000000000000001", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM.", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.ANY_RESPONSE", "Counter": "0,1,2,3", "EventCode": "0XB7", - "EventName": "OCR.DEMAND_CODE_RD.LOCAL_DRAM", + "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x184000004", + "MSRValue": "0x10001", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that have any type of response.", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.DRAM", "Counter": "0,1,2,3", "EventCode": "0XB7", - "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.ANY_RESPONSE", + "EventName": "OCR.DEMAND_DATA_RD.DRAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x10001", + "MSRValue": "0x184000001", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by DRAM.", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.LOCAL_DRAM", "Counter": "0,1,2,3", "EventCode": "0XB7", - "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.DRAM", + "EventName": "OCR.DEMAND_DATA_RD.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x184000001", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache.", + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.OUTSTANDING", "Counter": "0,1,2,3", "EventCode": "0XB7", - "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1F803C0001", + "EventName": "OCR.DEMAND_DATA_RD.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x8000000000000001", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.", + "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.", "Counter": "0,1,2,3", "EventCode": "0XB7", - "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HITM", + "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x10003C0001", + "MSRValue": "0x10002", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.", + "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM.", "Counter": "0,1,2,3", "EventCode": "0XB7", - "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_NO_FWD", + "EventName": "OCR.DEMAND_RFO.DRAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x4003C0001", + "MSRValue": "0x184000002", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.", + "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM.", "Counter": "0,1,2,3", "EventCode": "0XB7", - "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "EventName": "OCR.DEMAND_RFO.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x8003C0001", + "MSRValue": "0x184000002", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where a snoop was sent but the snoop missed.", + "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency).", "Counter": "0,1,2,3", "EventCode": "0XB7", - "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x2003C0001", + "EventName": "OCR.DEMAND_RFO.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x8000000000000002", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where no snoop was needed to satisfy the request.", + "BriefDescription": "Counts streaming stores which modify a full 64 byte cacheline that have any type of response.", "Counter": "0,1,2,3", "EventCode": "0XB7", - "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_NOT_NEEDED", + "EventName": "OCR.FULL_STREAMING_WR.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1003C0001", + "MSRValue": "0x800000010000", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by DRAM.", + "BriefDescription": "Counts L1 data cache hardware prefetches and software prefetches (except PREFETCHW and PFRFO) that have any type of response.", "Counter": "0,1,2,3", "EventCode": "0XB7", - "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.LOCAL_DRAM", + "EventName": "OCR.HWPF_L1D_AND_SWPF.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x184000001", + "MSRValue": "0x10400", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency).", + "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that have any type of response.", "Counter": "0,1,2,3", "EventCode": "0XB7", - "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.OUTSTANDING", - "MSRIndex": "0x1a6", - "MSRValue": "0x8000000000000001", + "EventName": "OCR.HWPF_L2_CODE_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10040", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.ANY_RESPONSE", + "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by DRAM.", "Counter": "0,1,2,3", "EventCode": "0XB7", - "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", + "EventName": "OCR.HWPF_L2_CODE_RD.DRAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x10001", + "MSRValue": "0x184000040", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.DRAM", + "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by DRAM.", "Counter": "0,1,2,3", "EventCode": "0XB7", - "EventName": "OCR.DEMAND_DATA_RD.DRAM", + "EventName": "OCR.HWPF_L2_CODE_RD.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x184000001", + "MSRValue": "0x184000040", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT", + "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency).", "Counter": "0,1,2,3", "EventCode": "0XB7", - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1F803C0001", + "EventName": "OCR.HWPF_L2_CODE_RD.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x8000000000000040", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HITM", + "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that have any type of response.", "Counter": "0,1,2,3", "EventCode": "0XB7", - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", + "EventName": "OCR.HWPF_L2_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x10003C0001", + "MSRValue": "0x10010", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_NO_FWD", + "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by DRAM.", "Counter": "0,1,2,3", "EventCode": "0XB7", - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", + "EventName": "OCR.HWPF_L2_DATA_RD.DRAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x4003C0001", + "MSRValue": "0x184000010", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by DRAM.", "Counter": "0,1,2,3", "EventCode": "0XB7", - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "EventName": "OCR.HWPF_L2_DATA_RD.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x8003C0001", + "MSRValue": "0x184000010", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_MISS", + "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that have any type of response.", "Counter": "0,1,2,3", "EventCode": "0XB7", - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS", + "EventName": "OCR.HWPF_L2_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x2003C0001", + "MSRValue": "0x10020", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_NOT_NEEDED", + "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by DRAM.", "Counter": "0,1,2,3", "EventCode": "0XB7", - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED", + "EventName": "OCR.HWPF_L2_RFO.DRAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1003C0001", + "MSRValue": "0x184000020", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.LOCAL_DRAM", + "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by DRAM.", "Counter": "0,1,2,3", "EventCode": "0XB7", - "EventName": "OCR.DEMAND_DATA_RD.LOCAL_DRAM", + "EventName": "OCR.HWPF_L2_RFO.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x184000001", + "MSRValue": "0x184000020", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.OUTSTANDING", + "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency).", "Counter": "0,1,2,3", "EventCode": "0XB7", - "EventName": "OCR.DEMAND_DATA_RD.OUTSTANDING", + "EventName": "OCR.HWPF_L2_RFO.OUTSTANDING", "MSRIndex": "0x1a6", - "MSRValue": "0x8000000000000001", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x10002", + "MSRValue": "0x8000000000000020", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM.", + "BriefDescription": "Counts modified writebacks from L1 cache that miss the L2 cache that have any type of response.", "Counter": "0,1,2,3", "EventCode": "0XB7", - "EventName": "OCR.DEMAND_RFO.DRAM", + "EventName": "OCR.L1WB_M.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x184000002", + "MSRValue": "0x1000000010000", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache.", + "BriefDescription": "Counts modified writeBacks from L2 cache that miss the L3 cache that have any type of response.", "Counter": "0,1,2,3", "EventCode": "0XB7", - "EventName": "OCR.DEMAND_RFO.L3_HIT", + "EventName": "OCR.L2WB_M.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1F803C0002", + "MSRValue": "0x2000000010000", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.", + "BriefDescription": "Counts miscellaneous requests, such as I/O accesses, that have any type of response.", "Counter": "0,1,2,3", "EventCode": "0XB7", - "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", + "EventName": "OCR.OTHER.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x10003C0002", + "MSRValue": "0x18000", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.", + "BriefDescription": "Counts streaming stores which modify only part of a 64 byte cacheline that have any type of response.", "Counter": "0,1,2,3", "EventCode": "0XB7", - "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_NO_FWD", + "EventName": "OCR.PARTIAL_STREAMING_WR.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x4003C0002", + "MSRValue": "0x400000010000", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.", + "BriefDescription": "Counts all hardware and software prefetches that have any type of response.", "Counter": "0,1,2,3", "EventCode": "0XB7", - "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", + "EventName": "OCR.PREFETCHES.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x8003C0002", + "MSRValue": "0x10470", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent but the snoop missed.", + "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that have any type of response.", "Counter": "0,1,2,3", "EventCode": "0XB7", - "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS", + "EventName": "OCR.READS_TO_CORE.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x2003C0002", + "MSRValue": "0x10477", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where no snoop was needed to satisfy the request.", + "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM.", "Counter": "0,1,2,3", "EventCode": "0XB7", - "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_NOT_NEEDED", + "EventName": "OCR.READS_TO_CORE.DRAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1003C0002", + "MSRValue": "0x184000477", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM.", + "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM.", "Counter": "0,1,2,3", "EventCode": "0XB7", - "EventName": "OCR.DEMAND_RFO.LOCAL_DRAM", + "EventName": "OCR.READS_TO_CORE.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x184000002", + "MSRValue": "0x184000477", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency).", + "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency).", "Counter": "0,1,2,3", "EventCode": "0XB7", - "EventName": "OCR.DEMAND_RFO.OUTSTANDING", + "EventName": "OCR.READS_TO_CORE.OUTSTANDING", "MSRIndex": "0x1a6", - "MSRValue": "0x8000000000000002", + "MSRValue": "0x8000000000000477", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts streaming stores which modify a full 64 byte cacheline that have any type of response.", + "BriefDescription": "Counts streaming stores that have any type of response.", "Counter": "0,1,2,3", "EventCode": "0XB7", - "EventName": "OCR.FULL_STREAMING_WR.ANY_RESPONSE", + "EventName": "OCR.STREAMING_WR.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x800000010000", + "MSRValue": "0x10800", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts streaming stores which modify a full 64 byte cacheline that were supplied by the L3 cache.", + "BriefDescription": "Counts uncached memory reads that have any type of response.", "Counter": "0,1,2,3", "EventCode": "0XB7", - "EventName": "OCR.FULL_STREAMING_WR.L3_HIT", + "EventName": "OCR.UC_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x801F803C0000", + "MSRValue": "0x100000010000", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that have any type of response.", + "BriefDescription": "Counts uncached memory reads that were supplied by DRAM.", "Counter": "0,1,2,3", "EventCode": "0XB7", - "EventName": "OCR.HWPF_L2_CODE_RD.ANY_RESPONSE", + "EventName": "OCR.UC_RD.DRAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x10040", + "MSRValue": "0x100184000000", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by DRAM.", + "BriefDescription": "Counts uncached memory reads that were supplied by DRAM.", "Counter": "0,1,2,3", "EventCode": "0XB7", - "EventName": "OCR.HWPF_L2_CODE_RD.DRAM", + "EventName": "OCR.UC_RD.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x184000040", + "MSRValue": "0x100184000000", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache.", + "BriefDescription": "Counts uncached memory reads that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency).", "Counter": "0,1,2,3", "EventCode": "0XB7", - "EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1F803C0040", + "EventName": "OCR.UC_RD.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x8000100000000000", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.", + "BriefDescription": "Counts uncached memory writes that have any type of response.", "Counter": "0,1,2,3", "EventCode": "0XB7", - "EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_HITM", + "EventName": "OCR.UC_WR.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x10003C0040", + "MSRValue": "0x200000010000", "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" - }, - { - "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x4003C0040", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x8003C0040", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent but the snoop missed.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x2003C0040", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where no snoop was needed to satisfy the request.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1003C0040", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by DRAM.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.HWPF_L2_CODE_RD.LOCAL_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x184000040", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency).", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.HWPF_L2_CODE_RD.OUTSTANDING", - "MSRIndex": "0x1a6", - "MSRValue": "0x8000000000000040", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that have any type of response.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.HWPF_L2_DATA_RD.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x10010", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by DRAM.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.HWPF_L2_DATA_RD.DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x184000010", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1F803C0010", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HITM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x10003C0010", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x4003C0010", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x8003C0010", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent but the snoop missed.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x2003C0010", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where no snoop was needed to satisfy the request.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1003C0010", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by DRAM.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.HWPF_L2_DATA_RD.LOCAL_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x184000010", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that have any type of response.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.HWPF_L2_RFO.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x10020", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by DRAM.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.HWPF_L2_RFO.DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x184000020", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.HWPF_L2_RFO.L3_HIT", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1F803C0020", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HITM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x10003C0020", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x4003C0020", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x8003C0020", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent but the snoop missed.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x2003C0020", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where no snoop was needed to satisfy the request.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1003C0020", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by DRAM.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.HWPF_L2_RFO.LOCAL_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x184000020", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency).", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.HWPF_L2_RFO.OUTSTANDING", - "MSRIndex": "0x1a6", - "MSRValue": "0x8000000000000020", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts modified writebacks from L1 cache that miss the L2 cache that have any type of response.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.L1WB_M.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000000010000", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts modified writebacks from L1 cache that miss the L2 cache that were supplied by the L3 cache.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.L1WB_M.L3_HIT", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1001F803C0000", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts modified writeBacks from L2 cache that miss the L3 cache that have any type of response.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.L2WB_M.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x2000000010000", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts modified writeBacks from L2 cache that miss the L3 cache that were supplied by the L3 cache.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.L2WB_M.L3_HIT", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x2001F803C0000", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts miscellaneous requests, such as I/O accesses, that have any type of response.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.OTHER.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x18000", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts streaming stores which modify only part of a 64 byte cacheline that have any type of response.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.PARTIAL_STREAMING_WR.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x400000010000", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts streaming stores which modify only part of a 64 byte cacheline that were supplied by the L3 cache.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.PARTIAL_STREAMING_WR.L3_HIT", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x401F803C0000", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all hardware and software prefetches that have any type of response.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.PREFETCHES.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x10470", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that have any type of response.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.READS_TO_CORE.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x10477", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.READS_TO_CORE.DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x184000477", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.READS_TO_CORE.L3_HIT", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1F803C0477", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HITM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x10003C0477", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x4003C0477", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_WITH_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x8003C0477", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where a snoop was sent but the snoop missed.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x2003C0477", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where no snoop was needed to satisfy the request.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1003C0477", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.READS_TO_CORE.LOCAL_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x184000477", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency).", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.READS_TO_CORE.OUTSTANDING", - "MSRIndex": "0x1a6", - "MSRValue": "0x8000000000000477", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts streaming stores that have any type of response.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.STREAMING_WR.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x10800", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts streaming stores that were supplied by the L3 cache.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.STREAMING_WR.L3_HIT", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1F803C0800", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts uncached memory reads that have any type of response.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.UC_RD.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x100000010000", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts uncached memory reads that were supplied by DRAM.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.UC_RD.DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x100184000000", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts uncached memory reads that were supplied by the L3 cache.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.UC_RD.L3_HIT", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x101F803C0000", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts uncached memory reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.UC_RD.L3_HIT.SNOOP_HITM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1010003C0000", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts uncached memory reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.UC_RD.L3_HIT.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1004003C0000", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts uncached memory reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.UC_RD.L3_HIT.SNOOP_HIT_WITH_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1008003C0000", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts uncached memory reads that were supplied by the L3 cache where a snoop was sent but the snoop missed.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.UC_RD.L3_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1002003C0000", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts uncached memory reads that were supplied by the L3 cache where no snoop was needed to satisfy the request.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.UC_RD.L3_HIT.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1001003C0000", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts uncached memory reads that were supplied by DRAM.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.UC_RD.LOCAL_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x100184000000", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts uncached memory reads that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency).", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.UC_RD.OUTSTANDING", - "MSRIndex": "0x1a6", - "MSRValue": "0x8000100000000000", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts uncached memory writes that have any type of response.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.UC_WR.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x200000010000", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts uncached memory writes that were supplied by the L3 cache.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.UC_WR.L3_HIT", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x201F803C0000", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x73", - "EventName": "TOPDOWN_BAD_SPECULATION.ALL", - "PDIR_COUNTER": "na", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window including relevant microcode flows and while uops are not yet available in the instruction queue (IQ) even if an FE_bound event occurs during this period. Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear.", - "SampleAfterValue": "1000003", - "UMask": "0x6" - }, - { - "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to fast nukes such as memory ordering and memory disambiguation machine clears.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x73", - "EventName": "TOPDOWN_BAD_SPECULATION.FASTNUKE", - "PDIR_COUNTER": "na", - "PEBScounters": "0,1,2,3", - "SampleAfterValue": "1000003", - "UMask": "0x2" - }, - { - "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x73", - "EventName": "TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS", - "PDIR_COUNTER": "na", - "PEBScounters": "0,1,2,3", - "SampleAfterValue": "1000003", - "UMask": "0x2" - }, - { - "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to branch mispredicts.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x73", - "EventName": "TOPDOWN_BAD_SPECULATION.MISPREDICT", - "PDIR_COUNTER": "na", - "PEBScounters": "0,1,2,3", - "SampleAfterValue": "1000003", - "UMask": "0x4" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event TOPDOWN_BAD_SPECULATION.FASTNUKE", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x73", - "EventName": "TOPDOWN_BAD_SPECULATION.MONUKE", - "PDIR_COUNTER": "na", - "PEBScounters": "0,1,2,3", - "SampleAfterValue": "1000003", - "UMask": "0x2" - }, - { - "BriefDescription": "Counts the total number of issue slots every cycle that were not consumed by the backend due to backend stalls.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x74", - "EventName": "TOPDOWN_BE_BOUND.ALL", - "PDIR_COUNTER": "na", - "PEBScounters": "0,1,2,3", - "SampleAfterValue": "1000003" - }, - { - "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to certain allocation restrictions.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x74", - "EventName": "TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS", - "PDIR_COUNTER": "na", - "PEBScounters": "0,1,2,3", - "SampleAfterValue": "1000003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to memory reservation stalls in which a scheduler is not able to accept uops.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x74", - "EventName": "TOPDOWN_BE_BOUND.MEM_SCHEDULER", - "PDIR_COUNTER": "na", - "PEBScounters": "0,1,2,3", - "SampleAfterValue": "1000003", - "UMask": "0x2" - }, - { - "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to IEC or FPC RAT stalls, which can be due to FIQ or IEC reservation stalls in which the integer, floating point or SIMD scheduler is not able to accept uops.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x74", - "EventName": "TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER", - "PDIR_COUNTER": "na", - "PEBScounters": "0,1,2,3", - "SampleAfterValue": "1000003", - "UMask": "0x8" - }, - { - "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to the physical register file unable to accept an entry (marble stalls).", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x74", - "EventName": "TOPDOWN_BE_BOUND.REGISTER", - "PDIR_COUNTER": "na", - "PEBScounters": "0,1,2,3", - "SampleAfterValue": "1000003", - "UMask": "0x20" - }, - { - "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to the reorder buffer being full (ROB stalls).", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x74", - "EventName": "TOPDOWN_BE_BOUND.REORDER_BUFFER", - "PDIR_COUNTER": "na", - "PEBScounters": "0,1,2,3", - "SampleAfterValue": "1000003", - "UMask": "0x40" - }, - { - "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to scoreboards from the instruction queue (IQ), jump execution unit (JEU), or microcode sequencer (MS).", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x74", - "EventName": "TOPDOWN_BE_BOUND.SERIALIZATION", - "PDIR_COUNTER": "na", - "PEBScounters": "0,1,2,3", - "SampleAfterValue": "1000003", - "UMask": "0x10" - }, - { - "BriefDescription": "This event is deprecated.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x74", - "EventName": "TOPDOWN_BE_BOUND.STORE_BUFFER", - "PDIR_COUNTER": "na", - "PEBScounters": "0,1,2,3", - "SampleAfterValue": "1000003", - "UMask": "0x4" - }, - { - "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to frontend stalls.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x71", - "EventName": "TOPDOWN_FE_BOUND.ALL", - "PDIR_COUNTER": "na", - "PEBScounters": "0,1,2,3", - "SampleAfterValue": "1000003" - }, - { - "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BACLEARS.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x71", - "EventName": "TOPDOWN_FE_BOUND.BRANCH_DETECT", - "PDIR_COUNTER": "na", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.", - "SampleAfterValue": "1000003", - "UMask": "0x2" - }, - { - "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BTCLEARS.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x71", - "EventName": "TOPDOWN_FE_BOUND.BRANCH_RESTEER", - "PDIR_COUNTER": "na", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BTCLEARS, which occurs when the Branch Target Buffer (BTB) predicts a taken branch.", - "SampleAfterValue": "1000003", - "UMask": "0x40" - }, - { - "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to the microcode sequencer (MS).", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x71", - "EventName": "TOPDOWN_FE_BOUND.CISC", - "PDIR_COUNTER": "na", - "PEBScounters": "0,1,2,3", - "SampleAfterValue": "1000003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to decode stalls.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x71", - "EventName": "TOPDOWN_FE_BOUND.DECODE", - "PDIR_COUNTER": "na", - "PEBScounters": "0,1,2,3", - "SampleAfterValue": "1000003", - "UMask": "0x8" - }, - { - "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to frontend bandwidth restrictions due to decode, predecode, cisc, and other limitations.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x71", - "EventName": "TOPDOWN_FE_BOUND.FRONTEND_BANDWIDTH", - "PDIR_COUNTER": "na", - "PEBScounters": "0,1,2,3", - "SampleAfterValue": "1000003", - "UMask": "0x8d" - }, - { - "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to a latency related stalls including BACLEARs, BTCLEARs, ITLB misses, and ICache misses.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x71", - "EventName": "TOPDOWN_FE_BOUND.FRONTEND_LATENCY", - "PDIR_COUNTER": "na", - "PEBScounters": "0,1,2,3", - "SampleAfterValue": "1000003", - "UMask": "0x72" - }, - { - "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to ITLB misses.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x71", - "EventName": "TOPDOWN_FE_BOUND.ITLB", - "PDIR_COUNTER": "na", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to Instruction Table Lookaside Buffer (ITLB) misses.", - "SampleAfterValue": "1000003", - "UMask": "0x10" - }, - { - "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to other common frontend stalls not categorized.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x71", - "EventName": "TOPDOWN_FE_BOUND.OTHER", - "PDIR_COUNTER": "na", - "PEBScounters": "0,1,2,3", - "SampleAfterValue": "1000003", - "UMask": "0x80" - }, - { - "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to wrong predecodes.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x71", - "EventName": "TOPDOWN_FE_BOUND.PREDECODE", - "PDIR_COUNTER": "na", - "PEBScounters": "0,1,2,3", - "SampleAfterValue": "1000003", - "UMask": "0x4" - }, - { - "BriefDescription": "Counts the total number of consumed retirement slots.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xc2", - "EventName": "TOPDOWN_RETIRING.ALL", - "PEBS": "1", - "PEBScounters": "0,1,2,3", - "SampleAfterValue": "1000003" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/tremontx/pipeline.json b/tools/perf/pmu-events/arch/x86/tremontx/pipeline.json index 200255c62249..0a77e9f9a16a 100644 --- a/tools/perf/pmu-events/arch/x86/tremontx/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/tremontx/pipeline.json @@ -274,6 +274,17 @@ "SampleAfterValue": "1000003", "UMask": "0x4" }, + { + "BriefDescription": "Counts the number of retired loads that are blocked for any of the following reasons: DTLB miss, address alias, store forward or data unknown (includes memory disambiguation blocks and ESP consuming load blocks).", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.ALL", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x10" + }, { "BriefDescription": "Counts the number of retired loads that are blocked because its address exactly matches an older store whose data is not ready.", "CollectPEBSRecord": "2", @@ -285,6 +296,17 @@ "SampleAfterValue": "1000003", "UMask": "0x1" }, + { + "BriefDescription": "Counts the number of retired loads that are blocked because its address partially overlapped with an older store.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.STORE_FORWARD", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x2" + }, { "BriefDescription": "Counts the total number of machine clears for any reason including, but not limited to, memory ordering, memory disambiguation, SMC, and FP assist.", "CollectPEBSRecord": "2", @@ -295,6 +317,17 @@ "PEBScounters": "0,1,2,3", "SampleAfterValue": "20003" }, + { + "BriefDescription": "Counts the number of machine clears due to memory ordering in which an internal load passes an older store within the same CPU.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xc3", + "EventName": "MACHINE_CLEARS.DISAMBIGUATION", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "20003", + "UMask": "0x8" + }, { "BriefDescription": "Counts the number of machine clears due to a page fault. Counts both I-Side and D-Side (Loads/Stores) page faults. A page fault occurs when either the page is not present, or an access violation occurs.", "CollectPEBSRecord": "2", @@ -317,6 +350,282 @@ "SampleAfterValue": "20003", "UMask": "0x1" }, + { + "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x73", + "EventName": "TOPDOWN_BAD_SPECULATION.ALL", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window including relevant microcode flows and while uops are not yet available in the instruction queue (IQ) even if an FE_bound event occurs during this period. Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear.", + "SampleAfterValue": "1000003", + "UMask": "0x6" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to fast nukes such as memory ordering and memory disambiguation machine clears.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x73", + "EventName": "TOPDOWN_BAD_SPECULATION.FASTNUKE", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x73", + "EventName": "TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to branch mispredicts.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x73", + "EventName": "TOPDOWN_BAD_SPECULATION.MISPREDICT", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x4" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event TOPDOWN_BAD_SPECULATION.FASTNUKE", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x73", + "EventName": "TOPDOWN_BAD_SPECULATION.MONUKE", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts the total number of issue slots every cycle that were not consumed by the backend due to backend stalls.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x74", + "EventName": "TOPDOWN_BE_BOUND.ALL", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to certain allocation restrictions.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x74", + "EventName": "TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to memory reservation stalls in which a scheduler is not able to accept uops.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x74", + "EventName": "TOPDOWN_BE_BOUND.MEM_SCHEDULER", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to IEC or FPC RAT stalls, which can be due to FIQ or IEC reservation stalls in which the integer, floating point or SIMD scheduler is not able to accept uops.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x74", + "EventName": "TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to the physical register file unable to accept an entry (marble stalls).", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x74", + "EventName": "TOPDOWN_BE_BOUND.REGISTER", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x20" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to the reorder buffer being full (ROB stalls).", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x74", + "EventName": "TOPDOWN_BE_BOUND.REORDER_BUFFER", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x40" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to scoreboards from the instruction queue (IQ), jump execution unit (JEU), or microcode sequencer (MS).", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x74", + "EventName": "TOPDOWN_BE_BOUND.SERIALIZATION", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x10" + }, + { + "BriefDescription": "This event is deprecated.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x74", + "EventName": "TOPDOWN_BE_BOUND.STORE_BUFFER", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to frontend stalls.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x71", + "EventName": "TOPDOWN_FE_BOUND.ALL", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BACLEARS.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x71", + "EventName": "TOPDOWN_FE_BOUND.BRANCH_DETECT", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.", + "SampleAfterValue": "1000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BTCLEARS.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x71", + "EventName": "TOPDOWN_FE_BOUND.BRANCH_RESTEER", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BTCLEARS, which occurs when the Branch Target Buffer (BTB) predicts a taken branch.", + "SampleAfterValue": "1000003", + "UMask": "0x40" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to the microcode sequencer (MS).", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x71", + "EventName": "TOPDOWN_FE_BOUND.CISC", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to decode stalls.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x71", + "EventName": "TOPDOWN_FE_BOUND.DECODE", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to frontend bandwidth restrictions due to decode, predecode, cisc, and other limitations.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x71", + "EventName": "TOPDOWN_FE_BOUND.FRONTEND_BANDWIDTH", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x8d" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to a latency related stalls including BACLEARs, BTCLEARs, ITLB misses, and ICache misses.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x71", + "EventName": "TOPDOWN_FE_BOUND.FRONTEND_LATENCY", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x72" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to ITLB misses.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x71", + "EventName": "TOPDOWN_FE_BOUND.ITLB", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to Instruction Table Lookaside Buffer (ITLB) misses.", + "SampleAfterValue": "1000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to other common frontend stalls not categorized.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x71", + "EventName": "TOPDOWN_FE_BOUND.OTHER", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x80" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to wrong predecodes.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x71", + "EventName": "TOPDOWN_FE_BOUND.PREDECODE", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Counts the total number of consumed retirement slots.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xc2", + "EventName": "TOPDOWN_RETIRING.ALL", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003" + }, + { + "BriefDescription": "Counts the number of uops issued by the front end every cycle.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x0e", + "EventName": "UOPS_ISSUED.ANY", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of uops issued by the front end every cycle. When 4-uops are requested and only 2-uops are delivered, the event counts 2. Uops_issued correlates to the number of ROB entries. If uop takes 2 ROB slots it counts as 2 uops_issued.", + "SampleAfterValue": "200003" + }, { "BriefDescription": "Counts the total number of uops retired.", "CollectPEBSRecord": "2", @@ -350,5 +659,16 @@ "PublicDescription": "Counts the number of uops that are from complex flows issued by the Microcode Sequencer (MS). This includes uops from flows due to complex instructions, faults, assists, and inserted flows.", "SampleAfterValue": "2000003", "UMask": "0x1" + }, + { + "BriefDescription": "Counts the number of x87 uops retired, includes those in MS flows.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xc2", + "EventName": "UOPS_RETIRED.X87", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "UMask": "0x2" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/tremontx/uncore-other.json b/tools/perf/pmu-events/arch/x86/tremontx/uncore-other.json index 4e1a1c6faa63..0f73582248f9 100644 --- a/tools/perf/pmu-events/arch/x86/tremontx/uncore-other.json +++ b/tools/perf/pmu-events/arch/x86/tremontx/uncore-other.json @@ -945,6 +945,7 @@ "CounterType": "FREERUN", "EventName": "UNC_IIO_CLOCKTICKS_FREERUN", "PerPkg": "1", + "PublicDescription": "Free running counter that increments for integrated IO (IIO) traffic controller clockticks", "Unit": "IIO" }, { diff --git a/tools/perf/pmu-events/arch/x86/tremontx/virtual-memory.json b/tools/perf/pmu-events/arch/x86/tremontx/virtual-memory.json index cb0784562bd1..ecbfc335a9b6 100644 --- a/tools/perf/pmu-events/arch/x86/tremontx/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/tremontx/virtual-memory.json @@ -315,6 +315,17 @@ "SampleAfterValue": "200003", "UMask": "0x10" }, + { + "BriefDescription": "Counts the number of retired loads that are blocked due to a first level TLB miss.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.DTLB_MISS", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x8" + }, { "BriefDescription": "Counts the number of memory retired ops that missed in the second level TLB.", "CollectPEBSRecord": "2", -- 2.35.1.894.gb6a874cedc-goog ^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PATCH 8/8] perf vendor events: Update events for TremontX 2022-03-17 18:28 ` [PATCH 8/8] perf vendor events: Update events for TremontX Ian Rogers @ 2022-03-18 9:26 ` Xing Zhengjun 0 siblings, 0 replies; 18+ messages in thread From: Xing Zhengjun @ 2022-03-18 9:26 UTC (permalink / raw) To: Ian Rogers, Kan Liang, Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo, Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim, Maxime Coquelin, Alexandre Torgue, Andi Kleen, James Clark, John Garry, linux-kernel, linux-perf-users Cc: Stephane Eranian On 3/18/2022 2:28 AM, Ian Rogers wrote: > Move from v1.17 to v1.19. > The change: > https://github.com/intel/event-converter-for-linux-perf/commit/fc680410402e394eed6a1ebd909c9f649d3ed3ef > moved certain "other" type of events in to the cache, memory and > pipeline topics. Update the perf json files for this change. > > Signed-off-by: Ian Rogers <irogers@google.com> Reviewed-by: Zhengjun Xing <zhengjun.xing@linux.intel.com> > --- > .../pmu-events/arch/x86/tremontx/cache.json | 839 +++++++++- > .../arch/x86/tremontx/floating-point.json | 12 + > .../pmu-events/arch/x86/tremontx/memory.json | 59 +- > .../pmu-events/arch/x86/tremontx/other.json | 1362 ++--------------- > .../arch/x86/tremontx/pipeline.json | 320 ++++ > .../arch/x86/tremontx/uncore-other.json | 1 + > .../arch/x86/tremontx/virtual-memory.json | 11 + > 7 files changed, 1329 insertions(+), 1275 deletions(-) > > diff --git a/tools/perf/pmu-events/arch/x86/tremontx/cache.json b/tools/perf/pmu-events/arch/x86/tremontx/cache.json > index 615b516ea021..e142f294b42e 100644 > --- a/tools/perf/pmu-events/arch/x86/tremontx/cache.json > +++ b/tools/perf/pmu-events/arch/x86/tremontx/cache.json > @@ -33,6 +33,53 @@ > "PublicDescription": "Counts the number of demand and prefetch transactions that the External Queue (XQ) rejects due to a full or near full condition which likely indicates back pressure from the IDI link. The XQ may reject transactions from the L2Q (non-cacheable requests), BBL (L2 misses) and WOB (L2 write-back victims).", > "SampleAfterValue": "200003" > }, > + { > + "BriefDescription": "Counts the total number of L2 Cache accesses. Counts on a per core basis.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0x24", > + "EventName": "L2_REQUEST.ALL", > + "PDIR_COUNTER": "na", > + "PEBScounters": "0,1,2,3", > + "PublicDescription": "Counts the total number of L2 Cache Accesses, includes hits, misses, rejects front door requests for CRd/DRd/RFO/ItoM/L2 Prefetches only. Counts on a per core basis.", > + "SampleAfterValue": "200003" > + }, > + { > + "BriefDescription": "Counts the number of L2 Cache accesses that resulted in a hit. Counts on a per core basis.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0x24", > + "EventName": "L2_REQUEST.HIT", > + "PDIR_COUNTER": "na", > + "PEBScounters": "0,1,2,3", > + "PublicDescription": "Counts the number of L2 Cache accesses that resulted in a hit from a front door request only (does not include rejects or recycles), Counts on a per core basis.", > + "SampleAfterValue": "200003", > + "UMask": "0x2" > + }, > + { > + "BriefDescription": "Counts the number of L2 Cache accesses that resulted in a miss. Counts on a per core basis.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0x24", > + "EventName": "L2_REQUEST.MISS", > + "PDIR_COUNTER": "na", > + "PEBScounters": "0,1,2,3", > + "PublicDescription": "Counts the number of L2 Cache accesses that resulted in a miss from a front door request only (does not include rejects or recycles). Counts on a per core basis.", > + "SampleAfterValue": "200003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts the number of L2 Cache accesses that miss the L2 and get rejected. Counts on a per core basis.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0x24", > + "EventName": "L2_REQUEST.REJECTS", > + "PDIR_COUNTER": "na", > + "PEBScounters": "0,1,2,3", > + "PublicDescription": "Counts the number of L2 Cache accesses that miss the L2 and get BBL reject short and long rejects (includes those counted in L2_reject_XQ.any). Counts on a per core basis.", > + "SampleAfterValue": "200003", > + "UMask": "0x4" > + }, > { > "BriefDescription": "Counts the number of cacheable memory requests that miss in the LLC. Counts on a per core basis.", > "CollectPEBSRecord": "2", > @@ -59,6 +106,7 @@ > }, > { > "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).", > + "CollectPEBSRecord": "2", > "Counter": "0,1,2,3", > "EventCode": "0x34", > "EventName": "MEM_BOUND_STALLS.IFETCH", > @@ -86,7 +134,7 @@ > "EventName": "MEM_BOUND_STALLS.IFETCH_L2_HIT", > "PDIR_COUNTER": "na", > "PEBScounters": "0,1,2,3", > - "PublicDescription": "Counts the number of cycles a core is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) access which hit in the L2 cache.", > + "PublicDescription": "Counts the number of cycles the core is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) access which hit in the L2 cache.", > "SampleAfterValue": "200003", > "UMask": "0x8" > }, > @@ -98,7 +146,7 @@ > "EventName": "MEM_BOUND_STALLS.IFETCH_LLC_HIT", > "PDIR_COUNTER": "na", > "PEBScounters": "0,1,2,3", > - "PublicDescription": "Counts the number of cycles a core is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) access which hit in the Last Level Cache (LLC) or other core with HITE/F/M.", > + "PublicDescription": "Counts the number of cycles the core is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) access which hit in the Last Level Cache (LLC) or other core with HITE/F/M.", > "SampleAfterValue": "200003", > "UMask": "0x10" > }, > @@ -131,7 +179,6 @@ > "EventName": "MEM_BOUND_STALLS.LOAD_L2_HIT", > "PDIR_COUNTER": "na", > "PEBScounters": "0,1,2,3", > - "PublicDescription": "Counts the number of cycles a core is stalled due to a demand load which hit in the L2 cache.", > "SampleAfterValue": "200003", > "UMask": "0x1" > }, > @@ -143,7 +190,7 @@ > "EventName": "MEM_BOUND_STALLS.LOAD_LLC_HIT", > "PDIR_COUNTER": "na", > "PEBScounters": "0,1,2,3", > - "PublicDescription": "Counts the number of cycles a core is stalled due to a demand load which hit in the Last Level Cache (LLC) or other core with HITE/F/M.", > + "PublicDescription": "Counts the number of cycles the core is stalled due to a demand load which hit in the Last Level Cache (LLC) or other core with HITE/F/M.", > "SampleAfterValue": "200003", > "UMask": "0x2" > }, > @@ -241,6 +288,18 @@ > "SampleAfterValue": "200003", > "UMask": "0x4" > }, > + { > + "BriefDescription": "Counts the number of memory uops retired. A single uop that performs both a load AND a store will be counted as 1, not 2 (e.g. ADD [mem], CONST)", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "Data_LA": "1", > + "EventCode": "0xd0", > + "EventName": "MEM_UOPS_RETIRED.ALL", > + "PEBS": "1", > + "PEBScounters": "0,1,2,3", > + "SampleAfterValue": "200003", > + "UMask": "0x83" > + }, > { > "BriefDescription": "Counts the number of load uops retired.", > "CollectPEBSRecord": "2", > @@ -267,6 +326,18 @@ > "SampleAfterValue": "200003", > "UMask": "0x82" > }, > + { > + "BriefDescription": "Counts the number of load uops retired that performed one or more locks.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "Data_LA": "1", > + "EventCode": "0xd0", > + "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", > + "PEBS": "1", > + "PEBScounters": "0,1,2,3", > + "SampleAfterValue": "200003", > + "UMask": "0x21" > + }, > { > "BriefDescription": "Counts the number of memory uops retired that were splits.", > "CollectPEBSRecord": "2", > @@ -291,6 +362,766 @@ > "SampleAfterValue": "200003", > "UMask": "0x41" > }, > + { > + "BriefDescription": "Counts the number of retired split store uops.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "Data_LA": "1", > + "EventCode": "0xd0", > + "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", > + "PEBS": "1", > + "PEBScounters": "0,1,2,3", > + "SampleAfterValue": "200003", > + "UMask": "0x42" > + }, > + { > + "BriefDescription": "Counts all code reads that were supplied by the L3 cache.", > + "Counter": "0,1,2,3", > + "EventCode": "0XB7", > + "EventName": "OCR.ALL_CODE_RD.L3_HIT", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1F803C0044", > + "Offcore": "1", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.", > + "Counter": "0,1,2,3", > + "EventCode": "0XB7", > + "EventName": "OCR.ALL_CODE_RD.L3_HIT.SNOOP_HITM", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x10003C0044", > + "Offcore": "1", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.", > + "Counter": "0,1,2,3", > + "EventCode": "0XB7", > + "EventName": "OCR.ALL_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x4003C0044", > + "Offcore": "1", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.", > + "Counter": "0,1,2,3", > + "EventCode": "0XB7", > + "EventName": "OCR.ALL_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x8003C0044", > + "Offcore": "1", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was sent but the snoop missed.", > + "Counter": "0,1,2,3", > + "EventCode": "0XB7", > + "EventName": "OCR.ALL_CODE_RD.L3_HIT.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x2003C0044", > + "Offcore": "1", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all code reads that were supplied by the L3 cache where no snoop was needed to satisfy the request.", > + "Counter": "0,1,2,3", > + "EventCode": "0XB7", > + "EventName": "OCR.ALL_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1003C0044", > + "Offcore": "1", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts modified writebacks from L1 cache and L2 cache that were supplied by the L3 cache.", > + "Counter": "0,1,2,3", > + "EventCode": "0XB7", > + "EventName": "OCR.COREWB_M.L3_HIT", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3001F803C0000", > + "Offcore": "1", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache.", > + "Counter": "0,1,2,3", > + "EventCode": "0XB7", > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1F803C0004", > + "Offcore": "1", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.", > + "Counter": "0,1,2,3", > + "EventCode": "0XB7", > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x10003C0004", > + "Offcore": "1", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.", > + "Counter": "0,1,2,3", > + "EventCode": "0XB7", > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x4003C0004", > + "Offcore": "1", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.", > + "Counter": "0,1,2,3", > + "EventCode": "0XB7", > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x8003C0004", > + "Offcore": "1", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent but the snoop missed.", > + "Counter": "0,1,2,3", > + "EventCode": "0XB7", > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x2003C0004", > + "Offcore": "1", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where no snoop was needed to satisfy the request.", > + "Counter": "0,1,2,3", > + "EventCode": "0XB7", > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1003C0004", > + "Offcore": "1", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache.", > + "Counter": "0,1,2,3", > + "EventCode": "0XB7", > + "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1F803C0001", > + "Offcore": "1", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.", > + "Counter": "0,1,2,3", > + "EventCode": "0XB7", > + "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HITM", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x10003C0001", > + "Offcore": "1", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.", > + "Counter": "0,1,2,3", > + "EventCode": "0XB7", > + "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x4003C0001", > + "Offcore": "1", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.", > + "Counter": "0,1,2,3", > + "EventCode": "0XB7", > + "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_WITH_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x8003C0001", > + "Offcore": "1", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where a snoop was sent but the snoop missed.", > + "Counter": "0,1,2,3", > + "EventCode": "0XB7", > + "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x2003C0001", > + "Offcore": "1", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where no snoop was needed to satisfy the request.", > + "Counter": "0,1,2,3", > + "EventCode": "0XB7", > + "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_NOT_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1003C0001", > + "Offcore": "1", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT", > + "Counter": "0,1,2,3", > + "EventCode": "0XB7", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1F803C0001", > + "Offcore": "1", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HITM", > + "Counter": "0,1,2,3", > + "EventCode": "0XB7", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x10003C0001", > + "Offcore": "1", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_NO_FWD", > + "Counter": "0,1,2,3", > + "EventCode": "0XB7", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x4003C0001", > + "Offcore": "1", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_WITH_FWD", > + "Counter": "0,1,2,3", > + "EventCode": "0XB7", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x8003C0001", > + "Offcore": "1", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_MISS", > + "Counter": "0,1,2,3", > + "EventCode": "0XB7", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x2003C0001", > + "Offcore": "1", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_NOT_NEEDED", > + "Counter": "0,1,2,3", > + "EventCode": "0XB7", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1003C0001", > + "Offcore": "1", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache.", > + "Counter": "0,1,2,3", > + "EventCode": "0XB7", > + "EventName": "OCR.DEMAND_RFO.L3_HIT", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1F803C0002", > + "Offcore": "1", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.", > + "Counter": "0,1,2,3", > + "EventCode": "0XB7", > + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x10003C0002", > + "Offcore": "1", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.", > + "Counter": "0,1,2,3", > + "EventCode": "0XB7", > + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x4003C0002", > + "Offcore": "1", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.", > + "Counter": "0,1,2,3", > + "EventCode": "0XB7", > + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x8003C0002", > + "Offcore": "1", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent but the snoop missed.", > + "Counter": "0,1,2,3", > + "EventCode": "0XB7", > + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x2003C0002", > + "Offcore": "1", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where no snoop was needed to satisfy the request.", > + "Counter": "0,1,2,3", > + "EventCode": "0XB7", > + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_NOT_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1003C0002", > + "Offcore": "1", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts streaming stores which modify a full 64 byte cacheline that were supplied by the L3 cache.", > + "Counter": "0,1,2,3", > + "EventCode": "0XB7", > + "EventName": "OCR.FULL_STREAMING_WR.L3_HIT", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x801F803C0000", > + "Offcore": "1", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L1 data cache hardware prefetches and software prefetches (except PREFETCHW and PFRFO) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.", > + "Counter": "0,1,2,3", > + "EventCode": "0XB7", > + "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT.SNOOP_HITM", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x10003C0400", > + "Offcore": "1", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache.", > + "Counter": "0,1,2,3", > + "EventCode": "0XB7", > + "EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1F803C0040", > + "Offcore": "1", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.", > + "Counter": "0,1,2,3", > + "EventCode": "0XB7", > + "EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_HITM", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x10003C0040", > + "Offcore": "1", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.", > + "Counter": "0,1,2,3", > + "EventCode": "0XB7", > + "EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x4003C0040", > + "Offcore": "1", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.", > + "Counter": "0,1,2,3", > + "EventCode": "0XB7", > + "EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x8003C0040", > + "Offcore": "1", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent but the snoop missed.", > + "Counter": "0,1,2,3", > + "EventCode": "0XB7", > + "EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x2003C0040", > + "Offcore": "1", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where no snoop was needed to satisfy the request.", > + "Counter": "0,1,2,3", > + "EventCode": "0XB7", > + "EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1003C0040", > + "Offcore": "1", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache.", > + "Counter": "0,1,2,3", > + "EventCode": "0XB7", > + "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1F803C0010", > + "Offcore": "1", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.", > + "Counter": "0,1,2,3", > + "EventCode": "0XB7", > + "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HITM", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x10003C0010", > + "Offcore": "1", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.", > + "Counter": "0,1,2,3", > + "EventCode": "0XB7", > + "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x4003C0010", > + "Offcore": "1", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.", > + "Counter": "0,1,2,3", > + "EventCode": "0XB7", > + "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x8003C0010", > + "Offcore": "1", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent but the snoop missed.", > + "Counter": "0,1,2,3", > + "EventCode": "0XB7", > + "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x2003C0010", > + "Offcore": "1", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where no snoop was needed to satisfy the request.", > + "Counter": "0,1,2,3", > + "EventCode": "0XB7", > + "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1003C0010", > + "Offcore": "1", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache.", > + "Counter": "0,1,2,3", > + "EventCode": "0XB7", > + "EventName": "OCR.HWPF_L2_RFO.L3_HIT", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1F803C0020", > + "Offcore": "1", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.", > + "Counter": "0,1,2,3", > + "EventCode": "0XB7", > + "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HITM", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x10003C0020", > + "Offcore": "1", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.", > + "Counter": "0,1,2,3", > + "EventCode": "0XB7", > + "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HIT_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x4003C0020", > + "Offcore": "1", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.", > + "Counter": "0,1,2,3", > + "EventCode": "0XB7", > + "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x8003C0020", > + "Offcore": "1", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent but the snoop missed.", > + "Counter": "0,1,2,3", > + "EventCode": "0XB7", > + "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x2003C0020", > + "Offcore": "1", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where no snoop was needed to satisfy the request.", > + "Counter": "0,1,2,3", > + "EventCode": "0XB7", > + "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_NOT_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1003C0020", > + "Offcore": "1", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts modified writebacks from L1 cache that miss the L2 cache that were supplied by the L3 cache.", > + "Counter": "0,1,2,3", > + "EventCode": "0XB7", > + "EventName": "OCR.L1WB_M.L3_HIT", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1001F803C0000", > + "Offcore": "1", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts modified writeBacks from L2 cache that miss the L3 cache that were supplied by the L3 cache.", > + "Counter": "0,1,2,3", > + "EventCode": "0XB7", > + "EventName": "OCR.L2WB_M.L3_HIT", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x2001F803C0000", > + "Offcore": "1", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts streaming stores which modify only part of a 64 byte cacheline that were supplied by the L3 cache.", > + "Counter": "0,1,2,3", > + "EventCode": "0XB7", > + "EventName": "OCR.PARTIAL_STREAMING_WR.L3_HIT", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x401F803C0000", > + "Offcore": "1", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache.", > + "Counter": "0,1,2,3", > + "EventCode": "0XB7", > + "EventName": "OCR.READS_TO_CORE.L3_HIT", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1F803C0477", > + "Offcore": "1", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.", > + "Counter": "0,1,2,3", > + "EventCode": "0XB7", > + "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HITM", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x10003C0477", > + "Offcore": "1", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.", > + "Counter": "0,1,2,3", > + "EventCode": "0XB7", > + "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x4003C0477", > + "Offcore": "1", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.", > + "Counter": "0,1,2,3", > + "EventCode": "0XB7", > + "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_WITH_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x8003C0477", > + "Offcore": "1", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where a snoop was sent but the snoop missed.", > + "Counter": "0,1,2,3", > + "EventCode": "0XB7", > + "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x2003C0477", > + "Offcore": "1", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where no snoop was needed to satisfy the request.", > + "Counter": "0,1,2,3", > + "EventCode": "0XB7", > + "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_NOT_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1003C0477", > + "Offcore": "1", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts streaming stores that were supplied by the L3 cache.", > + "Counter": "0,1,2,3", > + "EventCode": "0XB7", > + "EventName": "OCR.STREAMING_WR.L3_HIT", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1F803C0800", > + "Offcore": "1", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts uncached memory reads that were supplied by the L3 cache.", > + "Counter": "0,1,2,3", > + "EventCode": "0XB7", > + "EventName": "OCR.UC_RD.L3_HIT", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x101F803C0000", > + "Offcore": "1", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts uncached memory reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.", > + "Counter": "0,1,2,3", > + "EventCode": "0XB7", > + "EventName": "OCR.UC_RD.L3_HIT.SNOOP_HITM", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1010003C0000", > + "Offcore": "1", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts uncached memory reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.", > + "Counter": "0,1,2,3", > + "EventCode": "0XB7", > + "EventName": "OCR.UC_RD.L3_HIT.SNOOP_HIT_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1004003C0000", > + "Offcore": "1", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts uncached memory reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.", > + "Counter": "0,1,2,3", > + "EventCode": "0XB7", > + "EventName": "OCR.UC_RD.L3_HIT.SNOOP_HIT_WITH_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1008003C0000", > + "Offcore": "1", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts uncached memory reads that were supplied by the L3 cache where a snoop was sent but the snoop missed.", > + "Counter": "0,1,2,3", > + "EventCode": "0XB7", > + "EventName": "OCR.UC_RD.L3_HIT.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1002003C0000", > + "Offcore": "1", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts uncached memory reads that were supplied by the L3 cache where no snoop was needed to satisfy the request.", > + "Counter": "0,1,2,3", > + "EventCode": "0XB7", > + "EventName": "OCR.UC_RD.L3_HIT.SNOOP_NOT_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1001003C0000", > + "Offcore": "1", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts uncached memory writes that were supplied by the L3 cache.", > + "Counter": "0,1,2,3", > + "EventCode": "0XB7", > + "EventName": "OCR.UC_WR.L3_HIT", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x201F803C0000", > + "Offcore": "1", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > { > "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to instruction cache misses.", > "CollectPEBSRecord": "2", > diff --git a/tools/perf/pmu-events/arch/x86/tremontx/floating-point.json b/tools/perf/pmu-events/arch/x86/tremontx/floating-point.json > index 2515b9aa6e66..c7780fa54689 100644 > --- a/tools/perf/pmu-events/arch/x86/tremontx/floating-point.json > +++ b/tools/perf/pmu-events/arch/x86/tremontx/floating-point.json > @@ -10,6 +10,18 @@ > "SampleAfterValue": "200003", > "UMask": "0x2" > }, > + { > + "BriefDescription": "Counts the number of floating point operations retired that required microcode assist.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0xc3", > + "EventName": "MACHINE_CLEARS.FP_ASSIST", > + "PDIR_COUNTER": "na", > + "PEBScounters": "0,1,2,3", > + "PublicDescription": "Counts the number of floating point operations retired that required microcode assist, which is not a reflection of the number of FP operations, instructions or uops.", > + "SampleAfterValue": "20003", > + "UMask": "0x4" > + }, > { > "BriefDescription": "Counts the number of floating point divide uops retired (x87 and SSE, including x87 sqrt).", > "CollectPEBSRecord": "2", > diff --git a/tools/perf/pmu-events/arch/x86/tremontx/memory.json b/tools/perf/pmu-events/arch/x86/tremontx/memory.json > index 4486f78035d8..76eaefafdc89 100644 > --- a/tools/perf/pmu-events/arch/x86/tremontx/memory.json > +++ b/tools/perf/pmu-events/arch/x86/tremontx/memory.json > @@ -10,6 +10,28 @@ > "SampleAfterValue": "20003", > "UMask": "0x2" > }, > + { > + "BriefDescription": "Counts the number of misaligned load uops that are 4K page splits.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0x13", > + "EventName": "MISALIGN_MEM_REF.LOAD_PAGE_SPLIT", > + "PEBS": "1", > + "PEBScounters": "0,1,2,3", > + "SampleAfterValue": "200003", > + "UMask": "0x2" > + }, > + { > + "BriefDescription": "Counts the number of misaligned store uops that are 4K page splits.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0x13", > + "EventName": "MISALIGN_MEM_REF.STORE_PAGE_SPLIT", > + "PEBS": "1", > + "PEBScounters": "0,1,2,3", > + "SampleAfterValue": "200003", > + "UMask": "0x4" > + }, > { > "BriefDescription": "Counts all code reads that were not supplied by the L3 cache.", > "Counter": "0,1,2,3", > @@ -18,7 +40,6 @@ > "MSRIndex": "0x1a6,0x1a7", > "MSRValue": "0x2184000044", > "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > @@ -30,7 +51,6 @@ > "MSRIndex": "0x1a6,0x1a7", > "MSRValue": "0x2184000044", > "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > @@ -42,7 +62,6 @@ > "MSRIndex": "0x1a6,0x1a7", > "MSRValue": "0x3002184000000", > "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > @@ -54,7 +73,6 @@ > "MSRIndex": "0x1a6,0x1a7", > "MSRValue": "0x3002184000000", > "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > @@ -66,7 +84,6 @@ > "MSRIndex": "0x1a6,0x1a7", > "MSRValue": "0x2184000004", > "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > @@ -78,7 +95,6 @@ > "MSRIndex": "0x1a6,0x1a7", > "MSRValue": "0x2184000004", > "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > @@ -90,7 +106,6 @@ > "MSRIndex": "0x1a6,0x1a7", > "MSRValue": "0x2184000001", > "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > @@ -102,7 +117,6 @@ > "MSRIndex": "0x1a6,0x1a7", > "MSRValue": "0x2184000001", > "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > @@ -114,7 +128,6 @@ > "MSRIndex": "0x1a6,0x1a7", > "MSRValue": "0x2184000001", > "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > @@ -126,7 +139,6 @@ > "MSRIndex": "0x1a6,0x1a7", > "MSRValue": "0x2184000001", > "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > @@ -138,7 +150,6 @@ > "MSRIndex": "0x1a6,0x1a7", > "MSRValue": "0x2184000002", > "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > @@ -150,7 +161,6 @@ > "MSRIndex": "0x1a6,0x1a7", > "MSRValue": "0x2184000002", > "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > @@ -162,7 +172,6 @@ > "MSRIndex": "0x1a6,0x1a7", > "MSRValue": "0x802184000000", > "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > @@ -174,7 +183,6 @@ > "MSRIndex": "0x1a6,0x1a7", > "MSRValue": "0x802184000000", > "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > @@ -186,7 +194,6 @@ > "MSRIndex": "0x1a6,0x1a7", > "MSRValue": "0x2184000040", > "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > @@ -198,7 +205,6 @@ > "MSRIndex": "0x1a6,0x1a7", > "MSRValue": "0x2184000040", > "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > @@ -210,7 +216,6 @@ > "MSRIndex": "0x1a6,0x1a7", > "MSRValue": "0x2184000010", > "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > @@ -222,7 +227,6 @@ > "MSRIndex": "0x1a6,0x1a7", > "MSRValue": "0x2184000010", > "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > @@ -234,7 +238,6 @@ > "MSRIndex": "0x1a6,0x1a7", > "MSRValue": "0x2184000020", > "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > @@ -246,7 +249,6 @@ > "MSRIndex": "0x1a6,0x1a7", > "MSRValue": "0x2184000020", > "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > @@ -258,7 +260,6 @@ > "MSRIndex": "0x1a6,0x1a7", > "MSRValue": "0x1002184000000", > "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > @@ -270,7 +271,6 @@ > "MSRIndex": "0x1a6,0x1a7", > "MSRValue": "0x1002184000000", > "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > @@ -282,7 +282,6 @@ > "MSRIndex": "0x1a6,0x1a7", > "MSRValue": "0x2002184000000", > "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > @@ -294,7 +293,6 @@ > "MSRIndex": "0x1a6,0x1a7", > "MSRValue": "0x2002184000000", > "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > @@ -306,7 +304,6 @@ > "MSRIndex": "0x1a6,0x1a7", > "MSRValue": "0x2184008000", > "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > @@ -318,7 +315,6 @@ > "MSRIndex": "0x1a6,0x1a7", > "MSRValue": "0x2184008000", > "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > @@ -330,7 +326,6 @@ > "MSRIndex": "0x1a6,0x1a7", > "MSRValue": "0x402184000000", > "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > @@ -342,7 +337,6 @@ > "MSRIndex": "0x1a6,0x1a7", > "MSRValue": "0x402184000000", > "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > @@ -354,7 +348,6 @@ > "MSRIndex": "0x1a6,0x1a7", > "MSRValue": "0x2184000470", > "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > @@ -366,7 +359,6 @@ > "MSRIndex": "0x1a6,0x1a7", > "MSRValue": "0x2184000477", > "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > @@ -378,7 +370,6 @@ > "MSRIndex": "0x1a6,0x1a7", > "MSRValue": "0x2184000477", > "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > @@ -390,7 +381,6 @@ > "MSRIndex": "0x1a6,0x1a7", > "MSRValue": "0x2184000800", > "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > @@ -402,7 +392,6 @@ > "MSRIndex": "0x1a6,0x1a7", > "MSRValue": "0x2184000800", > "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > @@ -414,7 +403,6 @@ > "MSRIndex": "0x1a6,0x1a7", > "MSRValue": "0x102184000000", > "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > @@ -426,7 +414,6 @@ > "MSRIndex": "0x1a6,0x1a7", > "MSRValue": "0x102184000000", > "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > @@ -438,7 +425,6 @@ > "MSRIndex": "0x1a6,0x1a7", > "MSRValue": "0x202184000000", > "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > @@ -450,7 +436,6 @@ > "MSRIndex": "0x1a6,0x1a7", > "MSRValue": "0x202184000000", > "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > } > diff --git a/tools/perf/pmu-events/arch/x86/tremontx/other.json b/tools/perf/pmu-events/arch/x86/tremontx/other.json > index 522eb795574d..4f20f45a4898 100644 > --- a/tools/perf/pmu-events/arch/x86/tremontx/other.json > +++ b/tools/perf/pmu-events/arch/x86/tremontx/other.json > @@ -152,7 +152,6 @@ > "MSRIndex": "0x1a6,0x1a7", > "MSRValue": "0x10044", > "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > @@ -164,79 +163,6 @@ > "MSRIndex": "0x1a6,0x1a7", > "MSRValue": "0x184000044", > "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all code reads that were supplied by the L3 cache.", > - "Counter": "0,1,2,3", > - "EventCode": "0XB7", > - "EventName": "OCR.ALL_CODE_RD.L3_HIT", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1F803C0044", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.", > - "Counter": "0,1,2,3", > - "EventCode": "0XB7", > - "EventName": "OCR.ALL_CODE_RD.L3_HIT.SNOOP_HITM", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10003C0044", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.", > - "Counter": "0,1,2,3", > - "EventCode": "0XB7", > - "EventName": "OCR.ALL_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x4003C0044", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.", > - "Counter": "0,1,2,3", > - "EventCode": "0XB7", > - "EventName": "OCR.ALL_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x8003C0044", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was sent but the snoop missed.", > - "Counter": "0,1,2,3", > - "EventCode": "0XB7", > - "EventName": "OCR.ALL_CODE_RD.L3_HIT.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x2003C0044", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all code reads that were supplied by the L3 cache where no snoop was needed to satisfy the request.", > - "Counter": "0,1,2,3", > - "EventCode": "0XB7", > - "EventName": "OCR.ALL_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1003C0044", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > @@ -248,7 +174,6 @@ > "MSRIndex": "0x1a6,0x1a7", > "MSRValue": "0x184000044", > "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > @@ -260,7 +185,6 @@ > "MSRIndex": "0x1a6", > "MSRValue": "0x8000000000000044", > "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > @@ -272,19 +196,6 @@ > "MSRIndex": "0x1a6,0x1a7", > "MSRValue": "0x3000000010000", > "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts modified writebacks from L1 cache and L2 cache that were supplied by the L3 cache.", > - "Counter": "0,1,2,3", > - "EventCode": "0XB7", > - "EventName": "OCR.COREWB_M.L3_HIT", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3001F803C0000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > @@ -296,7 +207,6 @@ > "MSRIndex": "0x1a6", > "MSRValue": "0x8003000000000000", > "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > @@ -308,7 +218,6 @@ > "MSRIndex": "0x1a6,0x1a7", > "MSRValue": "0x10004", > "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > @@ -320,1473 +229,458 @@ > "MSRIndex": "0x1a6,0x1a7", > "MSRValue": "0x184000004", > "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache.", > - "Counter": "0,1,2,3", > - "EventCode": "0XB7", > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1F803C0004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.", > + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM.", > "Counter": "0,1,2,3", > "EventCode": "0XB7", > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM", > + "EventName": "OCR.DEMAND_CODE_RD.LOCAL_DRAM", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10003C0004", > + "MSRValue": "0x184000004", > "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.", > + "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that have any type of response.", > "Counter": "0,1,2,3", > "EventCode": "0XB7", > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD", > + "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.ANY_RESPONSE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x4003C0004", > + "MSRValue": "0x10001", > "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.", > + "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by DRAM.", > "Counter": "0,1,2,3", > "EventCode": "0XB7", > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD", > + "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.DRAM", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x8003C0004", > + "MSRValue": "0x184000001", > "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent but the snoop missed.", > + "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by DRAM.", > "Counter": "0,1,2,3", > "EventCode": "0XB7", > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS", > + "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.LOCAL_DRAM", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x2003C0004", > + "MSRValue": "0x184000001", > "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where no snoop was needed to satisfy the request.", > + "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency).", > "Counter": "0,1,2,3", > "EventCode": "0XB7", > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1003C0004", > + "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.OUTSTANDING", > + "MSRIndex": "0x1a6", > + "MSRValue": "0x8000000000000001", > "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM.", > + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.ANY_RESPONSE", > "Counter": "0,1,2,3", > "EventCode": "0XB7", > - "EventName": "OCR.DEMAND_CODE_RD.LOCAL_DRAM", > + "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x184000004", > + "MSRValue": "0x10001", > "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that have any type of response.", > + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.DRAM", > "Counter": "0,1,2,3", > "EventCode": "0XB7", > - "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.ANY_RESPONSE", > + "EventName": "OCR.DEMAND_DATA_RD.DRAM", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10001", > + "MSRValue": "0x184000001", > "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by DRAM.", > + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.LOCAL_DRAM", > "Counter": "0,1,2,3", > "EventCode": "0XB7", > - "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.DRAM", > + "EventName": "OCR.DEMAND_DATA_RD.LOCAL_DRAM", > "MSRIndex": "0x1a6,0x1a7", > "MSRValue": "0x184000001", > "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache.", > + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.OUTSTANDING", > "Counter": "0,1,2,3", > "EventCode": "0XB7", > - "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1F803C0001", > + "EventName": "OCR.DEMAND_DATA_RD.OUTSTANDING", > + "MSRIndex": "0x1a6", > + "MSRValue": "0x8000000000000001", > "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.", > + "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.", > "Counter": "0,1,2,3", > "EventCode": "0XB7", > - "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HITM", > + "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10003C0001", > + "MSRValue": "0x10002", > "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.", > + "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM.", > "Counter": "0,1,2,3", > "EventCode": "0XB7", > - "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_NO_FWD", > + "EventName": "OCR.DEMAND_RFO.DRAM", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x4003C0001", > + "MSRValue": "0x184000002", > "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.", > + "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM.", > "Counter": "0,1,2,3", > "EventCode": "0XB7", > - "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_WITH_FWD", > + "EventName": "OCR.DEMAND_RFO.LOCAL_DRAM", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x8003C0001", > + "MSRValue": "0x184000002", > "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where a snoop was sent but the snoop missed.", > + "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency).", > "Counter": "0,1,2,3", > "EventCode": "0XB7", > - "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x2003C0001", > + "EventName": "OCR.DEMAND_RFO.OUTSTANDING", > + "MSRIndex": "0x1a6", > + "MSRValue": "0x8000000000000002", > "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where no snoop was needed to satisfy the request.", > + "BriefDescription": "Counts streaming stores which modify a full 64 byte cacheline that have any type of response.", > "Counter": "0,1,2,3", > "EventCode": "0XB7", > - "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_NOT_NEEDED", > + "EventName": "OCR.FULL_STREAMING_WR.ANY_RESPONSE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1003C0001", > + "MSRValue": "0x800000010000", > "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by DRAM.", > + "BriefDescription": "Counts L1 data cache hardware prefetches and software prefetches (except PREFETCHW and PFRFO) that have any type of response.", > "Counter": "0,1,2,3", > "EventCode": "0XB7", > - "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.LOCAL_DRAM", > + "EventName": "OCR.HWPF_L1D_AND_SWPF.ANY_RESPONSE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x184000001", > + "MSRValue": "0x10400", > "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency).", > + "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that have any type of response.", > "Counter": "0,1,2,3", > "EventCode": "0XB7", > - "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.OUTSTANDING", > - "MSRIndex": "0x1a6", > - "MSRValue": "0x8000000000000001", > + "EventName": "OCR.HWPF_L2_CODE_RD.ANY_RESPONSE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x10040", > "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.ANY_RESPONSE", > + "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by DRAM.", > "Counter": "0,1,2,3", > "EventCode": "0XB7", > - "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", > + "EventName": "OCR.HWPF_L2_CODE_RD.DRAM", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10001", > + "MSRValue": "0x184000040", > "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.DRAM", > + "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by DRAM.", > "Counter": "0,1,2,3", > "EventCode": "0XB7", > - "EventName": "OCR.DEMAND_DATA_RD.DRAM", > + "EventName": "OCR.HWPF_L2_CODE_RD.LOCAL_DRAM", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x184000001", > + "MSRValue": "0x184000040", > "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT", > + "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency).", > "Counter": "0,1,2,3", > "EventCode": "0XB7", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1F803C0001", > + "EventName": "OCR.HWPF_L2_CODE_RD.OUTSTANDING", > + "MSRIndex": "0x1a6", > + "MSRValue": "0x8000000000000040", > "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HITM", > + "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that have any type of response.", > "Counter": "0,1,2,3", > "EventCode": "0XB7", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", > + "EventName": "OCR.HWPF_L2_DATA_RD.ANY_RESPONSE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10003C0001", > + "MSRValue": "0x10010", > "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_NO_FWD", > + "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by DRAM.", > "Counter": "0,1,2,3", > "EventCode": "0XB7", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", > + "EventName": "OCR.HWPF_L2_DATA_RD.DRAM", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x4003C0001", > + "MSRValue": "0x184000010", > "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_WITH_FWD", > + "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by DRAM.", > "Counter": "0,1,2,3", > "EventCode": "0XB7", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", > + "EventName": "OCR.HWPF_L2_DATA_RD.LOCAL_DRAM", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x8003C0001", > + "MSRValue": "0x184000010", > "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_MISS", > + "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that have any type of response.", > "Counter": "0,1,2,3", > "EventCode": "0XB7", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS", > + "EventName": "OCR.HWPF_L2_RFO.ANY_RESPONSE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x2003C0001", > + "MSRValue": "0x10020", > "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_NOT_NEEDED", > + "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by DRAM.", > "Counter": "0,1,2,3", > "EventCode": "0XB7", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED", > + "EventName": "OCR.HWPF_L2_RFO.DRAM", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1003C0001", > + "MSRValue": "0x184000020", > "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.LOCAL_DRAM", > + "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by DRAM.", > "Counter": "0,1,2,3", > "EventCode": "0XB7", > - "EventName": "OCR.DEMAND_DATA_RD.LOCAL_DRAM", > + "EventName": "OCR.HWPF_L2_RFO.LOCAL_DRAM", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x184000001", > + "MSRValue": "0x184000020", > "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.OUTSTANDING", > + "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency).", > "Counter": "0,1,2,3", > "EventCode": "0XB7", > - "EventName": "OCR.DEMAND_DATA_RD.OUTSTANDING", > + "EventName": "OCR.HWPF_L2_RFO.OUTSTANDING", > "MSRIndex": "0x1a6", > - "MSRValue": "0x8000000000000001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.", > - "Counter": "0,1,2,3", > - "EventCode": "0XB7", > - "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10002", > + "MSRValue": "0x8000000000000020", > "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM.", > + "BriefDescription": "Counts modified writebacks from L1 cache that miss the L2 cache that have any type of response.", > "Counter": "0,1,2,3", > "EventCode": "0XB7", > - "EventName": "OCR.DEMAND_RFO.DRAM", > + "EventName": "OCR.L1WB_M.ANY_RESPONSE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x184000002", > + "MSRValue": "0x1000000010000", > "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache.", > + "BriefDescription": "Counts modified writeBacks from L2 cache that miss the L3 cache that have any type of response.", > "Counter": "0,1,2,3", > "EventCode": "0XB7", > - "EventName": "OCR.DEMAND_RFO.L3_HIT", > + "EventName": "OCR.L2WB_M.ANY_RESPONSE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1F803C0002", > + "MSRValue": "0x2000000010000", > "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.", > + "BriefDescription": "Counts miscellaneous requests, such as I/O accesses, that have any type of response.", > "Counter": "0,1,2,3", > "EventCode": "0XB7", > - "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", > + "EventName": "OCR.OTHER.ANY_RESPONSE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10003C0002", > + "MSRValue": "0x18000", > "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.", > + "BriefDescription": "Counts streaming stores which modify only part of a 64 byte cacheline that have any type of response.", > "Counter": "0,1,2,3", > "EventCode": "0XB7", > - "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_NO_FWD", > + "EventName": "OCR.PARTIAL_STREAMING_WR.ANY_RESPONSE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x4003C0002", > + "MSRValue": "0x400000010000", > "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.", > + "BriefDescription": "Counts all hardware and software prefetches that have any type of response.", > "Counter": "0,1,2,3", > "EventCode": "0XB7", > - "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", > + "EventName": "OCR.PREFETCHES.ANY_RESPONSE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x8003C0002", > + "MSRValue": "0x10470", > "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent but the snoop missed.", > + "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that have any type of response.", > "Counter": "0,1,2,3", > "EventCode": "0XB7", > - "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS", > + "EventName": "OCR.READS_TO_CORE.ANY_RESPONSE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x2003C0002", > + "MSRValue": "0x10477", > "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where no snoop was needed to satisfy the request.", > + "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM.", > "Counter": "0,1,2,3", > "EventCode": "0XB7", > - "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_NOT_NEEDED", > + "EventName": "OCR.READS_TO_CORE.DRAM", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1003C0002", > + "MSRValue": "0x184000477", > "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM.", > + "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM.", > "Counter": "0,1,2,3", > "EventCode": "0XB7", > - "EventName": "OCR.DEMAND_RFO.LOCAL_DRAM", > + "EventName": "OCR.READS_TO_CORE.LOCAL_DRAM", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x184000002", > + "MSRValue": "0x184000477", > "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency).", > + "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency).", > "Counter": "0,1,2,3", > "EventCode": "0XB7", > - "EventName": "OCR.DEMAND_RFO.OUTSTANDING", > + "EventName": "OCR.READS_TO_CORE.OUTSTANDING", > "MSRIndex": "0x1a6", > - "MSRValue": "0x8000000000000002", > + "MSRValue": "0x8000000000000477", > "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts streaming stores which modify a full 64 byte cacheline that have any type of response.", > + "BriefDescription": "Counts streaming stores that have any type of response.", > "Counter": "0,1,2,3", > "EventCode": "0XB7", > - "EventName": "OCR.FULL_STREAMING_WR.ANY_RESPONSE", > + "EventName": "OCR.STREAMING_WR.ANY_RESPONSE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800000010000", > + "MSRValue": "0x10800", > "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts streaming stores which modify a full 64 byte cacheline that were supplied by the L3 cache.", > + "BriefDescription": "Counts uncached memory reads that have any type of response.", > "Counter": "0,1,2,3", > "EventCode": "0XB7", > - "EventName": "OCR.FULL_STREAMING_WR.L3_HIT", > + "EventName": "OCR.UC_RD.ANY_RESPONSE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x801F803C0000", > + "MSRValue": "0x100000010000", > "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that have any type of response.", > + "BriefDescription": "Counts uncached memory reads that were supplied by DRAM.", > "Counter": "0,1,2,3", > "EventCode": "0XB7", > - "EventName": "OCR.HWPF_L2_CODE_RD.ANY_RESPONSE", > + "EventName": "OCR.UC_RD.DRAM", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10040", > + "MSRValue": "0x100184000000", > "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by DRAM.", > + "BriefDescription": "Counts uncached memory reads that were supplied by DRAM.", > "Counter": "0,1,2,3", > "EventCode": "0XB7", > - "EventName": "OCR.HWPF_L2_CODE_RD.DRAM", > + "EventName": "OCR.UC_RD.LOCAL_DRAM", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x184000040", > + "MSRValue": "0x100184000000", > "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache.", > + "BriefDescription": "Counts uncached memory reads that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency).", > "Counter": "0,1,2,3", > "EventCode": "0XB7", > - "EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1F803C0040", > + "EventName": "OCR.UC_RD.OUTSTANDING", > + "MSRIndex": "0x1a6", > + "MSRValue": "0x8000100000000000", > "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.", > + "BriefDescription": "Counts uncached memory writes that have any type of response.", > "Counter": "0,1,2,3", > "EventCode": "0XB7", > - "EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_HITM", > + "EventName": "OCR.UC_WR.ANY_RESPONSE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10003C0040", > + "MSRValue": "0x200000010000", > "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.", > - "Counter": "0,1,2,3", > - "EventCode": "0XB7", > - "EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x4003C0040", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.", > - "Counter": "0,1,2,3", > - "EventCode": "0XB7", > - "EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x8003C0040", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent but the snoop missed.", > - "Counter": "0,1,2,3", > - "EventCode": "0XB7", > - "EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x2003C0040", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where no snoop was needed to satisfy the request.", > - "Counter": "0,1,2,3", > - "EventCode": "0XB7", > - "EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1003C0040", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by DRAM.", > - "Counter": "0,1,2,3", > - "EventCode": "0XB7", > - "EventName": "OCR.HWPF_L2_CODE_RD.LOCAL_DRAM", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x184000040", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency).", > - "Counter": "0,1,2,3", > - "EventCode": "0XB7", > - "EventName": "OCR.HWPF_L2_CODE_RD.OUTSTANDING", > - "MSRIndex": "0x1a6", > - "MSRValue": "0x8000000000000040", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that have any type of response.", > - "Counter": "0,1,2,3", > - "EventCode": "0XB7", > - "EventName": "OCR.HWPF_L2_DATA_RD.ANY_RESPONSE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by DRAM.", > - "Counter": "0,1,2,3", > - "EventCode": "0XB7", > - "EventName": "OCR.HWPF_L2_DATA_RD.DRAM", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x184000010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache.", > - "Counter": "0,1,2,3", > - "EventCode": "0XB7", > - "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1F803C0010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.", > - "Counter": "0,1,2,3", > - "EventCode": "0XB7", > - "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HITM", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10003C0010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.", > - "Counter": "0,1,2,3", > - "EventCode": "0XB7", > - "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x4003C0010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.", > - "Counter": "0,1,2,3", > - "EventCode": "0XB7", > - "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x8003C0010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent but the snoop missed.", > - "Counter": "0,1,2,3", > - "EventCode": "0XB7", > - "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x2003C0010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where no snoop was needed to satisfy the request.", > - "Counter": "0,1,2,3", > - "EventCode": "0XB7", > - "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1003C0010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by DRAM.", > - "Counter": "0,1,2,3", > - "EventCode": "0XB7", > - "EventName": "OCR.HWPF_L2_DATA_RD.LOCAL_DRAM", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x184000010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that have any type of response.", > - "Counter": "0,1,2,3", > - "EventCode": "0XB7", > - "EventName": "OCR.HWPF_L2_RFO.ANY_RESPONSE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by DRAM.", > - "Counter": "0,1,2,3", > - "EventCode": "0XB7", > - "EventName": "OCR.HWPF_L2_RFO.DRAM", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x184000020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache.", > - "Counter": "0,1,2,3", > - "EventCode": "0XB7", > - "EventName": "OCR.HWPF_L2_RFO.L3_HIT", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1F803C0020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.", > - "Counter": "0,1,2,3", > - "EventCode": "0XB7", > - "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HITM", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10003C0020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.", > - "Counter": "0,1,2,3", > - "EventCode": "0XB7", > - "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HIT_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x4003C0020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.", > - "Counter": "0,1,2,3", > - "EventCode": "0XB7", > - "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x8003C0020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent but the snoop missed.", > - "Counter": "0,1,2,3", > - "EventCode": "0XB7", > - "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x2003C0020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where no snoop was needed to satisfy the request.", > - "Counter": "0,1,2,3", > - "EventCode": "0XB7", > - "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_NOT_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1003C0020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by DRAM.", > - "Counter": "0,1,2,3", > - "EventCode": "0XB7", > - "EventName": "OCR.HWPF_L2_RFO.LOCAL_DRAM", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x184000020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency).", > - "Counter": "0,1,2,3", > - "EventCode": "0XB7", > - "EventName": "OCR.HWPF_L2_RFO.OUTSTANDING", > - "MSRIndex": "0x1a6", > - "MSRValue": "0x8000000000000020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts modified writebacks from L1 cache that miss the L2 cache that have any type of response.", > - "Counter": "0,1,2,3", > - "EventCode": "0XB7", > - "EventName": "OCR.L1WB_M.ANY_RESPONSE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000000010000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts modified writebacks from L1 cache that miss the L2 cache that were supplied by the L3 cache.", > - "Counter": "0,1,2,3", > - "EventCode": "0XB7", > - "EventName": "OCR.L1WB_M.L3_HIT", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1001F803C0000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts modified writeBacks from L2 cache that miss the L3 cache that have any type of response.", > - "Counter": "0,1,2,3", > - "EventCode": "0XB7", > - "EventName": "OCR.L2WB_M.ANY_RESPONSE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x2000000010000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts modified writeBacks from L2 cache that miss the L3 cache that were supplied by the L3 cache.", > - "Counter": "0,1,2,3", > - "EventCode": "0XB7", > - "EventName": "OCR.L2WB_M.L3_HIT", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x2001F803C0000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts miscellaneous requests, such as I/O accesses, that have any type of response.", > - "Counter": "0,1,2,3", > - "EventCode": "0XB7", > - "EventName": "OCR.OTHER.ANY_RESPONSE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x18000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts streaming stores which modify only part of a 64 byte cacheline that have any type of response.", > - "Counter": "0,1,2,3", > - "EventCode": "0XB7", > - "EventName": "OCR.PARTIAL_STREAMING_WR.ANY_RESPONSE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400000010000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts streaming stores which modify only part of a 64 byte cacheline that were supplied by the L3 cache.", > - "Counter": "0,1,2,3", > - "EventCode": "0XB7", > - "EventName": "OCR.PARTIAL_STREAMING_WR.L3_HIT", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x401F803C0000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all hardware and software prefetches that have any type of response.", > - "Counter": "0,1,2,3", > - "EventCode": "0XB7", > - "EventName": "OCR.PREFETCHES.ANY_RESPONSE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10470", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that have any type of response.", > - "Counter": "0,1,2,3", > - "EventCode": "0XB7", > - "EventName": "OCR.READS_TO_CORE.ANY_RESPONSE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10477", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM.", > - "Counter": "0,1,2,3", > - "EventCode": "0XB7", > - "EventName": "OCR.READS_TO_CORE.DRAM", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x184000477", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache.", > - "Counter": "0,1,2,3", > - "EventCode": "0XB7", > - "EventName": "OCR.READS_TO_CORE.L3_HIT", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1F803C0477", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.", > - "Counter": "0,1,2,3", > - "EventCode": "0XB7", > - "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HITM", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10003C0477", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.", > - "Counter": "0,1,2,3", > - "EventCode": "0XB7", > - "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x4003C0477", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.", > - "Counter": "0,1,2,3", > - "EventCode": "0XB7", > - "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_WITH_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x8003C0477", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where a snoop was sent but the snoop missed.", > - "Counter": "0,1,2,3", > - "EventCode": "0XB7", > - "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x2003C0477", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where no snoop was needed to satisfy the request.", > - "Counter": "0,1,2,3", > - "EventCode": "0XB7", > - "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_NOT_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1003C0477", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM.", > - "Counter": "0,1,2,3", > - "EventCode": "0XB7", > - "EventName": "OCR.READS_TO_CORE.LOCAL_DRAM", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x184000477", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency).", > - "Counter": "0,1,2,3", > - "EventCode": "0XB7", > - "EventName": "OCR.READS_TO_CORE.OUTSTANDING", > - "MSRIndex": "0x1a6", > - "MSRValue": "0x8000000000000477", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts streaming stores that have any type of response.", > - "Counter": "0,1,2,3", > - "EventCode": "0XB7", > - "EventName": "OCR.STREAMING_WR.ANY_RESPONSE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10800", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts streaming stores that were supplied by the L3 cache.", > - "Counter": "0,1,2,3", > - "EventCode": "0XB7", > - "EventName": "OCR.STREAMING_WR.L3_HIT", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1F803C0800", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts uncached memory reads that have any type of response.", > - "Counter": "0,1,2,3", > - "EventCode": "0XB7", > - "EventName": "OCR.UC_RD.ANY_RESPONSE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100000010000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts uncached memory reads that were supplied by DRAM.", > - "Counter": "0,1,2,3", > - "EventCode": "0XB7", > - "EventName": "OCR.UC_RD.DRAM", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100184000000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts uncached memory reads that were supplied by the L3 cache.", > - "Counter": "0,1,2,3", > - "EventCode": "0XB7", > - "EventName": "OCR.UC_RD.L3_HIT", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x101F803C0000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts uncached memory reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.", > - "Counter": "0,1,2,3", > - "EventCode": "0XB7", > - "EventName": "OCR.UC_RD.L3_HIT.SNOOP_HITM", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1010003C0000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts uncached memory reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.", > - "Counter": "0,1,2,3", > - "EventCode": "0XB7", > - "EventName": "OCR.UC_RD.L3_HIT.SNOOP_HIT_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1004003C0000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts uncached memory reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.", > - "Counter": "0,1,2,3", > - "EventCode": "0XB7", > - "EventName": "OCR.UC_RD.L3_HIT.SNOOP_HIT_WITH_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1008003C0000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts uncached memory reads that were supplied by the L3 cache where a snoop was sent but the snoop missed.", > - "Counter": "0,1,2,3", > - "EventCode": "0XB7", > - "EventName": "OCR.UC_RD.L3_HIT.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1002003C0000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts uncached memory reads that were supplied by the L3 cache where no snoop was needed to satisfy the request.", > - "Counter": "0,1,2,3", > - "EventCode": "0XB7", > - "EventName": "OCR.UC_RD.L3_HIT.SNOOP_NOT_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1001003C0000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts uncached memory reads that were supplied by DRAM.", > - "Counter": "0,1,2,3", > - "EventCode": "0XB7", > - "EventName": "OCR.UC_RD.LOCAL_DRAM", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100184000000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts uncached memory reads that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency).", > - "Counter": "0,1,2,3", > - "EventCode": "0XB7", > - "EventName": "OCR.UC_RD.OUTSTANDING", > - "MSRIndex": "0x1a6", > - "MSRValue": "0x8000100000000000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts uncached memory writes that have any type of response.", > - "Counter": "0,1,2,3", > - "EventCode": "0XB7", > - "EventName": "OCR.UC_WR.ANY_RESPONSE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200000010000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts uncached memory writes that were supplied by the L3 cache.", > - "Counter": "0,1,2,3", > - "EventCode": "0XB7", > - "EventName": "OCR.UC_WR.L3_HIT", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x201F803C0000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0x73", > - "EventName": "TOPDOWN_BAD_SPECULATION.ALL", > - "PDIR_COUNTER": "na", > - "PEBScounters": "0,1,2,3", > - "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window including relevant microcode flows and while uops are not yet available in the instruction queue (IQ) even if an FE_bound event occurs during this period. Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear.", > - "SampleAfterValue": "1000003", > - "UMask": "0x6" > - }, > - { > - "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to fast nukes such as memory ordering and memory disambiguation machine clears.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0x73", > - "EventName": "TOPDOWN_BAD_SPECULATION.FASTNUKE", > - "PDIR_COUNTER": "na", > - "PEBScounters": "0,1,2,3", > - "SampleAfterValue": "1000003", > - "UMask": "0x2" > - }, > - { > - "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0x73", > - "EventName": "TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS", > - "PDIR_COUNTER": "na", > - "PEBScounters": "0,1,2,3", > - "SampleAfterValue": "1000003", > - "UMask": "0x2" > - }, > - { > - "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to branch mispredicts.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0x73", > - "EventName": "TOPDOWN_BAD_SPECULATION.MISPREDICT", > - "PDIR_COUNTER": "na", > - "PEBScounters": "0,1,2,3", > - "SampleAfterValue": "1000003", > - "UMask": "0x4" > - }, > - { > - "BriefDescription": "This event is deprecated. Refer to new event TOPDOWN_BAD_SPECULATION.FASTNUKE", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0x73", > - "EventName": "TOPDOWN_BAD_SPECULATION.MONUKE", > - "PDIR_COUNTER": "na", > - "PEBScounters": "0,1,2,3", > - "SampleAfterValue": "1000003", > - "UMask": "0x2" > - }, > - { > - "BriefDescription": "Counts the total number of issue slots every cycle that were not consumed by the backend due to backend stalls.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0x74", > - "EventName": "TOPDOWN_BE_BOUND.ALL", > - "PDIR_COUNTER": "na", > - "PEBScounters": "0,1,2,3", > - "SampleAfterValue": "1000003" > - }, > - { > - "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to certain allocation restrictions.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0x74", > - "EventName": "TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS", > - "PDIR_COUNTER": "na", > - "PEBScounters": "0,1,2,3", > - "SampleAfterValue": "1000003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to memory reservation stalls in which a scheduler is not able to accept uops.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0x74", > - "EventName": "TOPDOWN_BE_BOUND.MEM_SCHEDULER", > - "PDIR_COUNTER": "na", > - "PEBScounters": "0,1,2,3", > - "SampleAfterValue": "1000003", > - "UMask": "0x2" > - }, > - { > - "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to IEC or FPC RAT stalls, which can be due to FIQ or IEC reservation stalls in which the integer, floating point or SIMD scheduler is not able to accept uops.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0x74", > - "EventName": "TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER", > - "PDIR_COUNTER": "na", > - "PEBScounters": "0,1,2,3", > - "SampleAfterValue": "1000003", > - "UMask": "0x8" > - }, > - { > - "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to the physical register file unable to accept an entry (marble stalls).", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0x74", > - "EventName": "TOPDOWN_BE_BOUND.REGISTER", > - "PDIR_COUNTER": "na", > - "PEBScounters": "0,1,2,3", > - "SampleAfterValue": "1000003", > - "UMask": "0x20" > - }, > - { > - "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to the reorder buffer being full (ROB stalls).", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0x74", > - "EventName": "TOPDOWN_BE_BOUND.REORDER_BUFFER", > - "PDIR_COUNTER": "na", > - "PEBScounters": "0,1,2,3", > - "SampleAfterValue": "1000003", > - "UMask": "0x40" > - }, > - { > - "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to scoreboards from the instruction queue (IQ), jump execution unit (JEU), or microcode sequencer (MS).", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0x74", > - "EventName": "TOPDOWN_BE_BOUND.SERIALIZATION", > - "PDIR_COUNTER": "na", > - "PEBScounters": "0,1,2,3", > - "SampleAfterValue": "1000003", > - "UMask": "0x10" > - }, > - { > - "BriefDescription": "This event is deprecated.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0x74", > - "EventName": "TOPDOWN_BE_BOUND.STORE_BUFFER", > - "PDIR_COUNTER": "na", > - "PEBScounters": "0,1,2,3", > - "SampleAfterValue": "1000003", > - "UMask": "0x4" > - }, > - { > - "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to frontend stalls.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0x71", > - "EventName": "TOPDOWN_FE_BOUND.ALL", > - "PDIR_COUNTER": "na", > - "PEBScounters": "0,1,2,3", > - "SampleAfterValue": "1000003" > - }, > - { > - "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BACLEARS.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0x71", > - "EventName": "TOPDOWN_FE_BOUND.BRANCH_DETECT", > - "PDIR_COUNTER": "na", > - "PEBScounters": "0,1,2,3", > - "PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.", > - "SampleAfterValue": "1000003", > - "UMask": "0x2" > - }, > - { > - "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BTCLEARS.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0x71", > - "EventName": "TOPDOWN_FE_BOUND.BRANCH_RESTEER", > - "PDIR_COUNTER": "na", > - "PEBScounters": "0,1,2,3", > - "PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BTCLEARS, which occurs when the Branch Target Buffer (BTB) predicts a taken branch.", > - "SampleAfterValue": "1000003", > - "UMask": "0x40" > - }, > - { > - "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to the microcode sequencer (MS).", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0x71", > - "EventName": "TOPDOWN_FE_BOUND.CISC", > - "PDIR_COUNTER": "na", > - "PEBScounters": "0,1,2,3", > - "SampleAfterValue": "1000003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to decode stalls.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0x71", > - "EventName": "TOPDOWN_FE_BOUND.DECODE", > - "PDIR_COUNTER": "na", > - "PEBScounters": "0,1,2,3", > - "SampleAfterValue": "1000003", > - "UMask": "0x8" > - }, > - { > - "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to frontend bandwidth restrictions due to decode, predecode, cisc, and other limitations.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0x71", > - "EventName": "TOPDOWN_FE_BOUND.FRONTEND_BANDWIDTH", > - "PDIR_COUNTER": "na", > - "PEBScounters": "0,1,2,3", > - "SampleAfterValue": "1000003", > - "UMask": "0x8d" > - }, > - { > - "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to a latency related stalls including BACLEARs, BTCLEARs, ITLB misses, and ICache misses.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0x71", > - "EventName": "TOPDOWN_FE_BOUND.FRONTEND_LATENCY", > - "PDIR_COUNTER": "na", > - "PEBScounters": "0,1,2,3", > - "SampleAfterValue": "1000003", > - "UMask": "0x72" > - }, > - { > - "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to ITLB misses.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0x71", > - "EventName": "TOPDOWN_FE_BOUND.ITLB", > - "PDIR_COUNTER": "na", > - "PEBScounters": "0,1,2,3", > - "PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to Instruction Table Lookaside Buffer (ITLB) misses.", > - "SampleAfterValue": "1000003", > - "UMask": "0x10" > - }, > - { > - "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to other common frontend stalls not categorized.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0x71", > - "EventName": "TOPDOWN_FE_BOUND.OTHER", > - "PDIR_COUNTER": "na", > - "PEBScounters": "0,1,2,3", > - "SampleAfterValue": "1000003", > - "UMask": "0x80" > - }, > - { > - "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to wrong predecodes.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0x71", > - "EventName": "TOPDOWN_FE_BOUND.PREDECODE", > - "PDIR_COUNTER": "na", > - "PEBScounters": "0,1,2,3", > - "SampleAfterValue": "1000003", > - "UMask": "0x4" > - }, > - { > - "BriefDescription": "Counts the total number of consumed retirement slots.", > - "CollectPEBSRecord": "2", > - "Counter": "0,1,2,3", > - "EventCode": "0xc2", > - "EventName": "TOPDOWN_RETIRING.ALL", > - "PEBS": "1", > - "PEBScounters": "0,1,2,3", > - "SampleAfterValue": "1000003" > } > ] > \ No newline at end of file > diff --git a/tools/perf/pmu-events/arch/x86/tremontx/pipeline.json b/tools/perf/pmu-events/arch/x86/tremontx/pipeline.json > index 200255c62249..0a77e9f9a16a 100644 > --- a/tools/perf/pmu-events/arch/x86/tremontx/pipeline.json > +++ b/tools/perf/pmu-events/arch/x86/tremontx/pipeline.json > @@ -274,6 +274,17 @@ > "SampleAfterValue": "1000003", > "UMask": "0x4" > }, > + { > + "BriefDescription": "Counts the number of retired loads that are blocked for any of the following reasons: DTLB miss, address alias, store forward or data unknown (includes memory disambiguation blocks and ESP consuming load blocks).", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0x03", > + "EventName": "LD_BLOCKS.ALL", > + "PEBS": "1", > + "PEBScounters": "0,1,2,3", > + "SampleAfterValue": "1000003", > + "UMask": "0x10" > + }, > { > "BriefDescription": "Counts the number of retired loads that are blocked because its address exactly matches an older store whose data is not ready.", > "CollectPEBSRecord": "2", > @@ -285,6 +296,17 @@ > "SampleAfterValue": "1000003", > "UMask": "0x1" > }, > + { > + "BriefDescription": "Counts the number of retired loads that are blocked because its address partially overlapped with an older store.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0x03", > + "EventName": "LD_BLOCKS.STORE_FORWARD", > + "PEBS": "1", > + "PEBScounters": "0,1,2,3", > + "SampleAfterValue": "1000003", > + "UMask": "0x2" > + }, > { > "BriefDescription": "Counts the total number of machine clears for any reason including, but not limited to, memory ordering, memory disambiguation, SMC, and FP assist.", > "CollectPEBSRecord": "2", > @@ -295,6 +317,17 @@ > "PEBScounters": "0,1,2,3", > "SampleAfterValue": "20003" > }, > + { > + "BriefDescription": "Counts the number of machine clears due to memory ordering in which an internal load passes an older store within the same CPU.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0xc3", > + "EventName": "MACHINE_CLEARS.DISAMBIGUATION", > + "PDIR_COUNTER": "na", > + "PEBScounters": "0,1,2,3", > + "SampleAfterValue": "20003", > + "UMask": "0x8" > + }, > { > "BriefDescription": "Counts the number of machine clears due to a page fault. Counts both I-Side and D-Side (Loads/Stores) page faults. A page fault occurs when either the page is not present, or an access violation occurs.", > "CollectPEBSRecord": "2", > @@ -317,6 +350,282 @@ > "SampleAfterValue": "20003", > "UMask": "0x1" > }, > + { > + "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0x73", > + "EventName": "TOPDOWN_BAD_SPECULATION.ALL", > + "PDIR_COUNTER": "na", > + "PEBScounters": "0,1,2,3", > + "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window including relevant microcode flows and while uops are not yet available in the instruction queue (IQ) even if an FE_bound event occurs during this period. Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear.", > + "SampleAfterValue": "1000003", > + "UMask": "0x6" > + }, > + { > + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to fast nukes such as memory ordering and memory disambiguation machine clears.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0x73", > + "EventName": "TOPDOWN_BAD_SPECULATION.FASTNUKE", > + "PDIR_COUNTER": "na", > + "PEBScounters": "0,1,2,3", > + "SampleAfterValue": "1000003", > + "UMask": "0x2" > + }, > + { > + "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0x73", > + "EventName": "TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS", > + "PDIR_COUNTER": "na", > + "PEBScounters": "0,1,2,3", > + "SampleAfterValue": "1000003", > + "UMask": "0x2" > + }, > + { > + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to branch mispredicts.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0x73", > + "EventName": "TOPDOWN_BAD_SPECULATION.MISPREDICT", > + "PDIR_COUNTER": "na", > + "PEBScounters": "0,1,2,3", > + "SampleAfterValue": "1000003", > + "UMask": "0x4" > + }, > + { > + "BriefDescription": "This event is deprecated. Refer to new event TOPDOWN_BAD_SPECULATION.FASTNUKE", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0x73", > + "EventName": "TOPDOWN_BAD_SPECULATION.MONUKE", > + "PDIR_COUNTER": "na", > + "PEBScounters": "0,1,2,3", > + "SampleAfterValue": "1000003", > + "UMask": "0x2" > + }, > + { > + "BriefDescription": "Counts the total number of issue slots every cycle that were not consumed by the backend due to backend stalls.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0x74", > + "EventName": "TOPDOWN_BE_BOUND.ALL", > + "PDIR_COUNTER": "na", > + "PEBScounters": "0,1,2,3", > + "SampleAfterValue": "1000003" > + }, > + { > + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to certain allocation restrictions.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0x74", > + "EventName": "TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS", > + "PDIR_COUNTER": "na", > + "PEBScounters": "0,1,2,3", > + "SampleAfterValue": "1000003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to memory reservation stalls in which a scheduler is not able to accept uops.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0x74", > + "EventName": "TOPDOWN_BE_BOUND.MEM_SCHEDULER", > + "PDIR_COUNTER": "na", > + "PEBScounters": "0,1,2,3", > + "SampleAfterValue": "1000003", > + "UMask": "0x2" > + }, > + { > + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to IEC or FPC RAT stalls, which can be due to FIQ or IEC reservation stalls in which the integer, floating point or SIMD scheduler is not able to accept uops.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0x74", > + "EventName": "TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER", > + "PDIR_COUNTER": "na", > + "PEBScounters": "0,1,2,3", > + "SampleAfterValue": "1000003", > + "UMask": "0x8" > + }, > + { > + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to the physical register file unable to accept an entry (marble stalls).", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0x74", > + "EventName": "TOPDOWN_BE_BOUND.REGISTER", > + "PDIR_COUNTER": "na", > + "PEBScounters": "0,1,2,3", > + "SampleAfterValue": "1000003", > + "UMask": "0x20" > + }, > + { > + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to the reorder buffer being full (ROB stalls).", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0x74", > + "EventName": "TOPDOWN_BE_BOUND.REORDER_BUFFER", > + "PDIR_COUNTER": "na", > + "PEBScounters": "0,1,2,3", > + "SampleAfterValue": "1000003", > + "UMask": "0x40" > + }, > + { > + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to scoreboards from the instruction queue (IQ), jump execution unit (JEU), or microcode sequencer (MS).", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0x74", > + "EventName": "TOPDOWN_BE_BOUND.SERIALIZATION", > + "PDIR_COUNTER": "na", > + "PEBScounters": "0,1,2,3", > + "SampleAfterValue": "1000003", > + "UMask": "0x10" > + }, > + { > + "BriefDescription": "This event is deprecated.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0x74", > + "EventName": "TOPDOWN_BE_BOUND.STORE_BUFFER", > + "PDIR_COUNTER": "na", > + "PEBScounters": "0,1,2,3", > + "SampleAfterValue": "1000003", > + "UMask": "0x4" > + }, > + { > + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to frontend stalls.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0x71", > + "EventName": "TOPDOWN_FE_BOUND.ALL", > + "PDIR_COUNTER": "na", > + "PEBScounters": "0,1,2,3", > + "SampleAfterValue": "1000003" > + }, > + { > + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BACLEARS.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0x71", > + "EventName": "TOPDOWN_FE_BOUND.BRANCH_DETECT", > + "PDIR_COUNTER": "na", > + "PEBScounters": "0,1,2,3", > + "PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.", > + "SampleAfterValue": "1000003", > + "UMask": "0x2" > + }, > + { > + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BTCLEARS.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0x71", > + "EventName": "TOPDOWN_FE_BOUND.BRANCH_RESTEER", > + "PDIR_COUNTER": "na", > + "PEBScounters": "0,1,2,3", > + "PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BTCLEARS, which occurs when the Branch Target Buffer (BTB) predicts a taken branch.", > + "SampleAfterValue": "1000003", > + "UMask": "0x40" > + }, > + { > + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to the microcode sequencer (MS).", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0x71", > + "EventName": "TOPDOWN_FE_BOUND.CISC", > + "PDIR_COUNTER": "na", > + "PEBScounters": "0,1,2,3", > + "SampleAfterValue": "1000003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to decode stalls.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0x71", > + "EventName": "TOPDOWN_FE_BOUND.DECODE", > + "PDIR_COUNTER": "na", > + "PEBScounters": "0,1,2,3", > + "SampleAfterValue": "1000003", > + "UMask": "0x8" > + }, > + { > + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to frontend bandwidth restrictions due to decode, predecode, cisc, and other limitations.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0x71", > + "EventName": "TOPDOWN_FE_BOUND.FRONTEND_BANDWIDTH", > + "PDIR_COUNTER": "na", > + "PEBScounters": "0,1,2,3", > + "SampleAfterValue": "1000003", > + "UMask": "0x8d" > + }, > + { > + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to a latency related stalls including BACLEARs, BTCLEARs, ITLB misses, and ICache misses.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0x71", > + "EventName": "TOPDOWN_FE_BOUND.FRONTEND_LATENCY", > + "PDIR_COUNTER": "na", > + "PEBScounters": "0,1,2,3", > + "SampleAfterValue": "1000003", > + "UMask": "0x72" > + }, > + { > + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to ITLB misses.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0x71", > + "EventName": "TOPDOWN_FE_BOUND.ITLB", > + "PDIR_COUNTER": "na", > + "PEBScounters": "0,1,2,3", > + "PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to Instruction Table Lookaside Buffer (ITLB) misses.", > + "SampleAfterValue": "1000003", > + "UMask": "0x10" > + }, > + { > + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to other common frontend stalls not categorized.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0x71", > + "EventName": "TOPDOWN_FE_BOUND.OTHER", > + "PDIR_COUNTER": "na", > + "PEBScounters": "0,1,2,3", > + "SampleAfterValue": "1000003", > + "UMask": "0x80" > + }, > + { > + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to wrong predecodes.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0x71", > + "EventName": "TOPDOWN_FE_BOUND.PREDECODE", > + "PDIR_COUNTER": "na", > + "PEBScounters": "0,1,2,3", > + "SampleAfterValue": "1000003", > + "UMask": "0x4" > + }, > + { > + "BriefDescription": "Counts the total number of consumed retirement slots.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0xc2", > + "EventName": "TOPDOWN_RETIRING.ALL", > + "PEBS": "1", > + "PEBScounters": "0,1,2,3", > + "SampleAfterValue": "1000003" > + }, > + { > + "BriefDescription": "Counts the number of uops issued by the front end every cycle.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0x0e", > + "EventName": "UOPS_ISSUED.ANY", > + "PDIR_COUNTER": "na", > + "PEBScounters": "0,1,2,3", > + "PublicDescription": "Counts the number of uops issued by the front end every cycle. When 4-uops are requested and only 2-uops are delivered, the event counts 2. Uops_issued correlates to the number of ROB entries. If uop takes 2 ROB slots it counts as 2 uops_issued.", > + "SampleAfterValue": "200003" > + }, > { > "BriefDescription": "Counts the total number of uops retired.", > "CollectPEBSRecord": "2", > @@ -350,5 +659,16 @@ > "PublicDescription": "Counts the number of uops that are from complex flows issued by the Microcode Sequencer (MS). This includes uops from flows due to complex instructions, faults, assists, and inserted flows.", > "SampleAfterValue": "2000003", > "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts the number of x87 uops retired, includes those in MS flows.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0xc2", > + "EventName": "UOPS_RETIRED.X87", > + "PEBS": "1", > + "PEBScounters": "0,1,2,3", > + "SampleAfterValue": "2000003", > + "UMask": "0x2" > } > ] > \ No newline at end of file > diff --git a/tools/perf/pmu-events/arch/x86/tremontx/uncore-other.json b/tools/perf/pmu-events/arch/x86/tremontx/uncore-other.json > index 4e1a1c6faa63..0f73582248f9 100644 > --- a/tools/perf/pmu-events/arch/x86/tremontx/uncore-other.json > +++ b/tools/perf/pmu-events/arch/x86/tremontx/uncore-other.json > @@ -945,6 +945,7 @@ > "CounterType": "FREERUN", > "EventName": "UNC_IIO_CLOCKTICKS_FREERUN", > "PerPkg": "1", > + "PublicDescription": "Free running counter that increments for integrated IO (IIO) traffic controller clockticks", > "Unit": "IIO" > }, > { > diff --git a/tools/perf/pmu-events/arch/x86/tremontx/virtual-memory.json b/tools/perf/pmu-events/arch/x86/tremontx/virtual-memory.json > index cb0784562bd1..ecbfc335a9b6 100644 > --- a/tools/perf/pmu-events/arch/x86/tremontx/virtual-memory.json > +++ b/tools/perf/pmu-events/arch/x86/tremontx/virtual-memory.json > @@ -315,6 +315,17 @@ > "SampleAfterValue": "200003", > "UMask": "0x10" > }, > + { > + "BriefDescription": "Counts the number of retired loads that are blocked due to a first level TLB miss.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3", > + "EventCode": "0x03", > + "EventName": "LD_BLOCKS.DTLB_MISS", > + "PEBS": "1", > + "PEBScounters": "0,1,2,3", > + "SampleAfterValue": "1000003", > + "UMask": "0x8" > + }, > { > "BriefDescription": "Counts the number of memory retired ops that missed in the second level TLB.", > "CollectPEBSRecord": "2", -- Zhengjun Xing ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 1/8] perf vendor events: Update events for CascadelakeX 2022-03-17 18:28 [PATCH 1/8] perf vendor events: Update events for CascadelakeX Ian Rogers ` (6 preceding siblings ...) 2022-03-17 18:28 ` [PATCH 8/8] perf vendor events: Update events for TremontX Ian Rogers @ 2022-03-18 9:09 ` Xing Zhengjun 2022-03-18 14:44 ` Arnaldo Carvalho de Melo 2022-03-18 9:14 ` John Garry 8 siblings, 1 reply; 18+ messages in thread From: Xing Zhengjun @ 2022-03-18 9:09 UTC (permalink / raw) To: Ian Rogers, Kan Liang, Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo, Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim, Maxime Coquelin, Alexandre Torgue, Andi Kleen, James Clark, John Garry, linux-kernel, linux-perf-users Cc: Stephane Eranian On 3/18/2022 2:28 AM, Ian Rogers wrote: > The change: > https://github.com/intel/event-converter-for-linux-perf/commit/fc680410402e394eed6a1ebd909c9f649d3ed3ef > moved certain "other" type of events in to the cache topic. Update the > perf json files for this change. > > Tested: > ``` > ... > 6: Parse event definition strings : Ok > 7: Simple expression parser : Ok > 8: PERF_RECORD_* events & perf_sample fields : Ok > 9: Parse perf pmu format : Ok > 10: PMU events : > 10.1: PMU event table sanity : Ok > 10.2: PMU event map aliases : Ok > 10.3: Parsing of PMU event table metrics : Ok > 10.4: Parsing of PMU event table metrics with fake PMUs : Ok > ... > 68: Parse and process metrics : Ok > ... > 89: perf all metricgroups test : Ok > 90: perf all metrics test : FAILED! > 91: perf all PMU test : Ok > ... > ``` > > Test 90 failed due to MEM_PMM_Read_Latency as the test machine > lacks optane memory, and the divide by 0 causes the metric not to > print - which is intended behavior. > > Signed-off-by: Ian Rogers <irogers@google.com> Reviewed-by: Zhengjun Xing <zhengjun.xing@linux.intel.com> > --- > .../arch/x86/cascadelakex/cache.json | 6588 +++++++++++++++ > .../arch/x86/cascadelakex/other.json | 7446 +---------------- > 2 files changed, 7017 insertions(+), 7017 deletions(-) > > diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/cache.json b/tools/perf/pmu-events/arch/x86/cascadelakex/cache.json > index 732bf51e35af..aa906a7fa520 100644 > --- a/tools/perf/pmu-events/arch/x86/cascadelakex/cache.json > +++ b/tools/perf/pmu-events/arch/x86/cascadelakex/cache.json > @@ -602,6 +602,6558 @@ > "SampleAfterValue": "100003", > "UMask": "0x80" > }, > + { > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F803C0491", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x10003C0491", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x8003C0491", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x4003C0491", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1003C0491", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x8007C0491", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_MISS OCR.ALL_DATA_RD.L3_HIT.SNOOP_MISS", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x2003C0491", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_NONE OCR.ALL_DATA_RD.L3_HIT.SNOOP_NONE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x803C0491", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT_E.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80080491", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000080491", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800080491", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400080491", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100080491", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_MISS", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200080491", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_NONE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80080491", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT_F.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80200491", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000200491", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800200491", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400200491", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100200491", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_MISS", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200200491", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_NONE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80200491", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT_M.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80040491", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000040491", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800040491", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400040491", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100040491", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_MISS", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200040491", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_NONE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80040491", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT_S.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80100491", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000100491", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800100491", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400100491", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100100491", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_MISS", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200100491", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_NONE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80100491", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F803C0490", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x10003C0490", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x8003C0490", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x4003C0490", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1003C0490", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x8007C0490", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x2003C0490", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x803C0490", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT_E.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80080490", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000080490", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800080490", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400080490", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100080490", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_MISS", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200080490", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_NONE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80080490", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT_F.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80200490", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000200490", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800200490", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400200490", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100200490", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_MISS", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200200490", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_NONE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80200490", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT_M.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80040490", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000040490", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800040490", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400040490", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100040490", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_MISS", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200040490", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_NONE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80040490", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT_S.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80100490", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000100490", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800100490", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400100490", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100100490", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_MISS", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200100490", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_NONE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80100490", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F803C0120", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x10003C0120", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x8003C0120", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x4003C0120", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1003C0120", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x8007C0120", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_MISS OCR.ALL_PF_RFO.L3_HIT.SNOOP_MISS", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x2003C0120", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_NONE OCR.ALL_PF_RFO.L3_HIT.SNOOP_NONE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x803C0120", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT_E.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80080120", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT_E.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000080120", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800080120", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400080120", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT_E.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100080120", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_MISS", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200080120", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_NONE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80080120", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT_F.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80200120", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT_F.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000200120", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800200120", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400200120", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT_F.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100200120", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_MISS", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200200120", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_NONE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80200120", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT_M.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80040120", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT_M.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000040120", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800040120", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400040120", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT_M.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100040120", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_MISS", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200040120", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_NONE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80040120", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT_S.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80100120", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT_S.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000100120", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800100120", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400100120", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT_S.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100100120", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_MISS", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200100120", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_NONE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80100120", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_READS.L3_HIT.ANY_SNOOP OCR.ALL_READS.L3_HIT.ANY_SNOOP OCR.ALL_READS.L3_HIT.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_READS.L3_HIT.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F803C07F7", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x10003C07F7", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x8003C07F7", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x4003C07F7", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1003C07F7", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_READS.L3_HIT.SNOOP_HIT_WITH_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_READS.L3_HIT.SNOOP_HIT_WITH_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x8007C07F7", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_READS.L3_HIT.SNOOP_MISS OCR.ALL_READS.L3_HIT.SNOOP_MISS", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_READS.L3_HIT.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x2003C07F7", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_READS.L3_HIT.SNOOP_NONE OCR.ALL_READS.L3_HIT.SNOOP_NONE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_READS.L3_HIT.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x803C07F7", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_READS.L3_HIT_E.ANY_SNOOP OCR.ALL_READS.L3_HIT_E.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_READS.L3_HIT_E.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F800807F7", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_READS.L3_HIT_E.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT_E.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_READS.L3_HIT_E.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x10000807F7", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x8000807F7", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x4000807F7", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_READS.L3_HIT_E.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT_E.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_READS.L3_HIT_E.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000807F7", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_READS.L3_HIT_E.SNOOP_MISS", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_READS.L3_HIT_E.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x2000807F7", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_READS.L3_HIT_E.SNOOP_NONE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_READS.L3_HIT_E.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800807F7", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_READS.L3_HIT_F.ANY_SNOOP OCR.ALL_READS.L3_HIT_F.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_READS.L3_HIT_F.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F802007F7", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_READS.L3_HIT_F.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT_F.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_READS.L3_HIT_F.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x10002007F7", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x8002007F7", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x4002007F7", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_READS.L3_HIT_F.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT_F.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_READS.L3_HIT_F.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1002007F7", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_READS.L3_HIT_F.SNOOP_MISS", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_READS.L3_HIT_F.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x2002007F7", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_READS.L3_HIT_F.SNOOP_NONE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_READS.L3_HIT_F.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x802007F7", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_READS.L3_HIT_M.ANY_SNOOP OCR.ALL_READS.L3_HIT_M.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_READS.L3_HIT_M.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F800407F7", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_READS.L3_HIT_M.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT_M.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_READS.L3_HIT_M.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x10000407F7", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x8000407F7", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x4000407F7", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_READS.L3_HIT_M.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT_M.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_READS.L3_HIT_M.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000407F7", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_READS.L3_HIT_M.SNOOP_MISS", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_READS.L3_HIT_M.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x2000407F7", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_READS.L3_HIT_M.SNOOP_NONE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_READS.L3_HIT_M.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800407F7", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_READS.L3_HIT_S.ANY_SNOOP OCR.ALL_READS.L3_HIT_S.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_READS.L3_HIT_S.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F801007F7", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_READS.L3_HIT_S.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT_S.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_READS.L3_HIT_S.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x10001007F7", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x8001007F7", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x4001007F7", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_READS.L3_HIT_S.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT_S.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_READS.L3_HIT_S.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1001007F7", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_READS.L3_HIT_S.SNOOP_MISS", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_READS.L3_HIT_S.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x2001007F7", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_READS.L3_HIT_S.SNOOP_NONE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_READS.L3_HIT_S.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x801007F7", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_RFO.L3_HIT.ANY_SNOOP OCR.ALL_RFO.L3_HIT.ANY_SNOOP OCR.ALL_RFO.L3_HIT.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_RFO.L3_HIT.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F803C0122", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x10003C0122", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x8003C0122", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x4003C0122", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1003C0122", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x8007C0122", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_RFO.L3_HIT.SNOOP_MISS OCR.ALL_RFO.L3_HIT.SNOOP_MISS", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_RFO.L3_HIT.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x2003C0122", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_RFO.L3_HIT.SNOOP_NONE OCR.ALL_RFO.L3_HIT.SNOOP_NONE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_RFO.L3_HIT.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x803C0122", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.ANY_SNOOP OCR.ALL_RFO.L3_HIT_E.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_RFO.L3_HIT_E.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80080122", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT_E.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_RFO.L3_HIT_E.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000080122", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800080122", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400080122", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT_E.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_RFO.L3_HIT_E.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100080122", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.SNOOP_MISS", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_RFO.L3_HIT_E.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200080122", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.SNOOP_NONE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_RFO.L3_HIT_E.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80080122", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.ANY_SNOOP OCR.ALL_RFO.L3_HIT_F.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_RFO.L3_HIT_F.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80200122", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT_F.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_RFO.L3_HIT_F.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000200122", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800200122", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400200122", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT_F.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_RFO.L3_HIT_F.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100200122", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.SNOOP_MISS", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_RFO.L3_HIT_F.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200200122", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.SNOOP_NONE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_RFO.L3_HIT_F.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80200122", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.ANY_SNOOP OCR.ALL_RFO.L3_HIT_M.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_RFO.L3_HIT_M.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80040122", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT_M.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_RFO.L3_HIT_M.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000040122", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800040122", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400040122", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT_M.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_RFO.L3_HIT_M.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100040122", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.SNOOP_MISS", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_RFO.L3_HIT_M.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200040122", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.SNOOP_NONE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_RFO.L3_HIT_M.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80040122", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.ANY_SNOOP OCR.ALL_RFO.L3_HIT_S.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_RFO.L3_HIT_S.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80100122", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT_S.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_RFO.L3_HIT_S.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000100122", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800100122", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400100122", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT_S.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_RFO.L3_HIT_S.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100100122", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.SNOOP_MISS", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_RFO.L3_HIT_S.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200100122", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.SNOOP_NONE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.ALL_RFO.L3_HIT_S.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80100122", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP OCR.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F803C0004", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE OCR.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x10003C0004", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x8003C0004", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x4003C0004", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDED OCR.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1003C0004", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand code reads", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x8007C0004", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x2003C0004", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NONE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x803C0004", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_E.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80080004", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_E.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000080004", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800080004", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400080004", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_E.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100080004", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand code reads", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200080004", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand code reads", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80080004", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_F.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80200004", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_F.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000200004", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800200004", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400200004", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_F.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100200004", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand code reads", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200200004", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand code reads", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80200004", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_M.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80040004", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_M.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000040004", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800040004", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400040004", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_M.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100040004", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand code reads", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200040004", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand code reads", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80040004", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_S.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80100004", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_S.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000100004", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800100004", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400100004", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_S.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100100004", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand code reads", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200100004", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand code reads", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80100004", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP OCR.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F803C0001", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x10003C0001", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x8003C0001", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x4003C0001", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1003C0001", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand data reads", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x8007C0001", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x2003C0001", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NONE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x803C0001", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_E.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80080001", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000080001", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800080001", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400080001", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100080001", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand data reads", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200080001", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand data reads", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80080001", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_F.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80200001", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000200001", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800200001", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400200001", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100200001", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand data reads", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200200001", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand data reads", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80200001", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_M.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80040001", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000040001", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800040001", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400040001", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100040001", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand data reads", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200040001", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand data reads", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80040001", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_S.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80100001", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000100001", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800100001", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400100001", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100100001", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand data reads", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200100001", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand data reads", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80100001", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.ANY_SNOOP OCR.DEMAND_RFO.L3_HIT.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_RFO.L3_HIT.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F803C0002", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x10003C0002", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x8003C0002", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x4003C0002", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1003C0002", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand data writes (RFOs)", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x8007C0002", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x2003C0002", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.SNOOP_NONE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x803C0002", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_E.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_RFO.L3_HIT_E.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80080002", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_E.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_RFO.L3_HIT_E.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000080002", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800080002", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400080002", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_E.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_RFO.L3_HIT_E.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100080002", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand data writes (RFOs)", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_RFO.L3_HIT_E.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200080002", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand data writes (RFOs)", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_RFO.L3_HIT_E.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80080002", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_F.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_RFO.L3_HIT_F.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80200002", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_F.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_RFO.L3_HIT_F.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000200002", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800200002", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400200002", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_F.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_RFO.L3_HIT_F.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100200002", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand data writes (RFOs)", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_RFO.L3_HIT_F.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200200002", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand data writes (RFOs)", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_RFO.L3_HIT_F.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80200002", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_M.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_RFO.L3_HIT_M.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80040002", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_M.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_RFO.L3_HIT_M.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000040002", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800040002", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400040002", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_M.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_RFO.L3_HIT_M.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100040002", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand data writes (RFOs)", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_RFO.L3_HIT_M.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200040002", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand data writes (RFOs)", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_RFO.L3_HIT_M.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80040002", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_S.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_RFO.L3_HIT_S.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80100002", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_S.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_RFO.L3_HIT_S.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000100002", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800100002", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400100002", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_S.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_RFO.L3_HIT_S.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100100002", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand data writes (RFOs)", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_RFO.L3_HIT_S.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200100002", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all demand data writes (RFOs)", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.DEMAND_RFO.L3_HIT_S.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80100002", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.ANY_SNOOP OCR.OTHER.L3_HIT.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.OTHER.L3_HIT.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F803C8000", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.HITM_OTHER_CORE OCR.OTHER.L3_HIT.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.OTHER.L3_HIT.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x10003C8000", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.HIT_OTHER_CORE_FWD OCR.OTHER.L3_HIT.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.OTHER.L3_HIT.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x8003C8000", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.OTHER.L3_HIT.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.OTHER.L3_HIT.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x4003C8000", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.NO_SNOOP_NEEDED OCR.OTHER.L3_HIT.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.OTHER.L3_HIT.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1003C8000", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts any other requests", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.OTHER.L3_HIT.SNOOP_HIT_WITH_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x8007C8000", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.SNOOP_MISS", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.OTHER.L3_HIT.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x2003C8000", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.SNOOP_NONE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.OTHER.L3_HIT.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x803C8000", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_E.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.OTHER.L3_HIT_E.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80088000", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_E.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.OTHER.L3_HIT_E.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000088000", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800088000", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400088000", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_E.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.OTHER.L3_HIT_E.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100088000", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts any other requests", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.OTHER.L3_HIT_E.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200088000", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts any other requests", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.OTHER.L3_HIT_E.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80088000", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_F.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.OTHER.L3_HIT_F.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80208000", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_F.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.OTHER.L3_HIT_F.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000208000", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800208000", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400208000", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_F.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.OTHER.L3_HIT_F.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100208000", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts any other requests", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.OTHER.L3_HIT_F.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200208000", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts any other requests", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.OTHER.L3_HIT_F.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80208000", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_M.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.OTHER.L3_HIT_M.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80048000", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_M.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.OTHER.L3_HIT_M.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000048000", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800048000", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400048000", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_M.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.OTHER.L3_HIT_M.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100048000", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts any other requests", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.OTHER.L3_HIT_M.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200048000", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts any other requests", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.OTHER.L3_HIT_M.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80048000", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_S.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.OTHER.L3_HIT_S.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80108000", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_S.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.OTHER.L3_HIT_S.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000108000", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800108000", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400108000", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_S.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.OTHER.L3_HIT_S.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100108000", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts any other requests", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.OTHER.L3_HIT_S.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200108000", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts any other requests", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.OTHER.L3_HIT_S.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80108000", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.ANY_SNOOP OCR.PF_L1D_AND_SW.L3_HIT.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F803C0400", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.HITM_OTHER_CORE OCR.PF_L1D_AND_SW.L3_HIT.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x10003C0400", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x8003C0400", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x4003C0400", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1003C0400", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_HIT_WITH_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x8007C0400", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_MISS", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x2003C0400", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_NONE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x803C0400", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_E.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80080400", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_E.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000080400", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800080400", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400080400", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_E.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100080400", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200080400", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80080400", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_F.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80200400", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_F.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000200400", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800200400", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400200400", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_F.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100200400", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200200400", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80200400", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_M.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80040400", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_M.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000040400", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800040400", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400040400", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_M.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100040400", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200040400", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80040400", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_S.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80100400", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_S.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000100400", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800100400", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400100400", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_S.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100100400", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200100400", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80100400", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP OCR.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F803C0010", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.PF_L2_DATA_RD.L3_HIT.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x10003C0010", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x8003C0010", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x4003C0010", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1003C0010", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x8007C0010", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_MISS", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x2003C0010", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_NONE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x803C0010", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_E.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80080010", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000080010", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800080010", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400080010", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100080010", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200080010", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80080010", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_F.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80200010", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000200010", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800200010", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400200010", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100200010", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200200010", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80200010", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_M.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80040010", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000040010", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800040010", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400040010", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100040010", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200040010", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80040010", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_S.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80100010", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000100010", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800100010", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400100010", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100100010", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200100010", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80100010", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.ANY_SNOOP OCR.PF_L2_RFO.L3_HIT.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_RFO.L3_HIT.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F803C0020", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x10003C0020", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x8003C0020", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x4003C0020", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1003C0020", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x8007C0020", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.SNOOP_MISS", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_RFO.L3_HIT.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x2003C0020", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.SNOOP_NONE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_RFO.L3_HIT.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x803C0020", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_E.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_RFO.L3_HIT_E.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80080020", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_E.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_RFO.L3_HIT_E.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000080020", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800080020", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400080020", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_E.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_RFO.L3_HIT_E.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100080020", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_RFO.L3_HIT_E.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200080020", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_RFO.L3_HIT_E.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80080020", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_F.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_RFO.L3_HIT_F.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80200020", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_F.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_RFO.L3_HIT_F.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000200020", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800200020", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400200020", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_F.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_RFO.L3_HIT_F.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100200020", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_RFO.L3_HIT_F.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200200020", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_RFO.L3_HIT_F.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80200020", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_M.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_RFO.L3_HIT_M.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80040020", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_M.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_RFO.L3_HIT_M.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000040020", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800040020", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400040020", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_M.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_RFO.L3_HIT_M.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100040020", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_RFO.L3_HIT_M.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200040020", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_RFO.L3_HIT_M.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80040020", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_S.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_RFO.L3_HIT_S.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80100020", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_S.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_RFO.L3_HIT_S.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000100020", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800100020", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400100020", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_S.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_RFO.L3_HIT_S.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100100020", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_RFO.L3_HIT_S.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200100020", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L2_RFO.L3_HIT_S.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80100020", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP OCR.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F803C0080", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.PF_L3_DATA_RD.L3_HIT.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x10003C0080", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x8003C0080", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x4003C0080", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1003C0080", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x8007C0080", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_MISS", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x2003C0080", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_NONE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x803C0080", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_E.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80080080", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000080080", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800080080", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400080080", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100080080", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200080080", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80080080", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_F.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80200080", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000200080", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800200080", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400200080", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100200080", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200200080", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80200080", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_M.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80040080", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000040080", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800040080", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400040080", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100040080", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200040080", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80040080", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_S.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80100080", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000100080", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800100080", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400100080", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100100080", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200100080", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80100080", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.ANY_SNOOP OCR.PF_L3_RFO.L3_HIT.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_RFO.L3_HIT.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F803C0100", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.HITM_OTHER_CORE OCR.PF_L3_RFO.L3_HIT.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_RFO.L3_HIT.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x10003C0100", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x8003C0100", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x4003C0100", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1003C0100", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x8007C0100", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.SNOOP_MISS", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_RFO.L3_HIT.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x2003C0100", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.SNOOP_NONE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_RFO.L3_HIT.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x803C0100", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_E.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_RFO.L3_HIT_E.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80080100", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_E.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_RFO.L3_HIT_E.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000080100", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800080100", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400080100", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_E.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_RFO.L3_HIT_E.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100080100", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_RFO.L3_HIT_E.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200080100", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_RFO.L3_HIT_E.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80080100", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_F.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_RFO.L3_HIT_F.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80200100", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_F.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_RFO.L3_HIT_F.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000200100", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800200100", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400200100", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_F.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_RFO.L3_HIT_F.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100200100", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_RFO.L3_HIT_F.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200200100", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_RFO.L3_HIT_F.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80200100", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_M.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_RFO.L3_HIT_M.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80040100", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_M.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_RFO.L3_HIT_M.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000040100", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800040100", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400040100", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_M.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_RFO.L3_HIT_M.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100040100", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_RFO.L3_HIT_M.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200040100", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_RFO.L3_HIT_M.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80040100", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_S.ANY_SNOOP", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_RFO.L3_HIT_S.ANY_SNOOP", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F80100100", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_S.HITM_OTHER_CORE", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_RFO.L3_HIT_S.HITM_OTHER_CORE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x1000100100", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x800100100", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x400100100", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_S.NO_SNOOP_NEEDED", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_RFO.L3_HIT_S.NO_SNOOP_NEEDED", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x100100100", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_RFO.L3_HIT_S.SNOOP_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x200100100", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3", > + "EventCode": "0xB7, 0xBB", > + "EventName": "OCR.PF_L3_RFO.L3_HIT_S.SNOOP_NONE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x80100100", > + "Offcore": "1", > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > { > "BriefDescription": "Demand and prefetch data reads", > "Counter": "0,1,2,3", > @@ -9987,5 +16539,41 @@ > "PublicDescription": "Counts the number of cache line split locks sent to the uncore.", > "SampleAfterValue": "100003", > "UMask": "0x10" > + }, > + { > + "BriefDescription": "Number of PREFETCHNTA instructions executed.", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3,4,5,6,7", > + "EventCode": "0x32", > + "EventName": "SW_PREFETCH_ACCESS.NTA", > + "SampleAfterValue": "2000003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Number of PREFETCHW instructions executed.", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3,4,5,6,7", > + "EventCode": "0x32", > + "EventName": "SW_PREFETCH_ACCESS.PREFETCHW", > + "SampleAfterValue": "2000003", > + "UMask": "0x8" > + }, > + { > + "BriefDescription": "Number of PREFETCHT0 instructions executed.", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3,4,5,6,7", > + "EventCode": "0x32", > + "EventName": "SW_PREFETCH_ACCESS.T0", > + "SampleAfterValue": "2000003", > + "UMask": "0x2" > + }, > + { > + "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.", > + "Counter": "0,1,2,3", > + "CounterHTOff": "0,1,2,3,4,5,6,7", > + "EventCode": "0x32", > + "EventName": "SW_PREFETCH_ACCESS.T1_T2", > + "SampleAfterValue": "2000003", > + "UMask": "0x4" > } > ] > \ No newline at end of file > diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/other.json b/tools/perf/pmu-events/arch/x86/cascadelakex/other.json > index d8b145a7d303..bb23a91b0127 100644 > --- a/tools/perf/pmu-events/arch/x86/cascadelakex/other.json > +++ b/tools/perf/pmu-events/arch/x86/cascadelakex/other.json > @@ -83,8411 +83,1859 @@ > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP", > + "BriefDescription": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP", > + "EventName": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F803C0491", > + "MSRValue": "0x3F80400491", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE", > + "BriefDescription": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE", > + "EventName": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10003C0491", > + "MSRValue": "0x80400491", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", > + "BriefDescription": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", > + "EventName": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x8003C0491", > + "MSRValue": "0x100400491", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", > + "BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.ANY_SNOOP OCR.ALL_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", > + "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x4003C0491", > + "MSRValue": "0x3F80020491", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", > + "BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE OCR.ALL_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", > + "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1003C0491", > + "MSRValue": "0x1000020491", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", > + "BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", > + "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x8007C0491", > + "MSRValue": "0x800020491", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_MISS OCR.ALL_DATA_RD.L3_HIT.SNOOP_MISS", > + "BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_MISS", > + "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x2003C0491", > + "MSRValue": "0x400020491", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_NONE OCR.ALL_DATA_RD.L3_HIT.SNOOP_NONE", > + "BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_NONE", > + "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x803C0491", > + "MSRValue": "0x100020491", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT_E.ANY_SNOOP", > + "BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.ANY_SNOOP", > + "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80080491", > + "MSRValue": "0x200020491", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", > + "BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", > + "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000080491", > + "MSRValue": "0x80020491", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", > + "BriefDescription": "OCR.ALL_PF_DATA_RD.ANY_RESPONSE have any response type.", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", > + "EventName": "OCR.ALL_PF_DATA_RD.ANY_RESPONSE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800080491", > + "MSRValue": "0x10490", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > + "BriefDescription": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > + "EventName": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400080491", > + "MSRValue": "0x3F80400490", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", > + "BriefDescription": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", > + "EventName": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100080491", > + "MSRValue": "0x80400490", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_MISS", > + "BriefDescription": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_MISS", > + "EventName": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200080491", > + "MSRValue": "0x100400490", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_NONE", > + "BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.ANY_SNOOP OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_NONE", > + "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80080491", > + "MSRValue": "0x3F80020490", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT_F.ANY_SNOOP", > + "BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.ANY_SNOOP", > + "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80200491", > + "MSRValue": "0x1000020490", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", > + "BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", > + "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000200491", > + "MSRValue": "0x800020490", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", > + "BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", > + "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800200491", > + "MSRValue": "0x400020490", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > + "BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > + "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400200491", > + "MSRValue": "0x100020490", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", > + "BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", > + "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100200491", > + "MSRValue": "0x200020490", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_MISS", > + "BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_MISS", > + "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200200491", > + "MSRValue": "0x80020490", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_NONE", > + "BriefDescription": "OCR.ALL_PF_RFO.ANY_RESPONSE have any response type.", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_NONE", > + "EventName": "OCR.ALL_PF_RFO.ANY_RESPONSE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80200491", > + "MSRValue": "0x10120", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT_M.ANY_SNOOP", > + "BriefDescription": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.ANY_SNOOP", > + "EventName": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80040491", > + "MSRValue": "0x3F80400120", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", > + "BriefDescription": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", > + "EventName": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000040491", > + "MSRValue": "0x80400120", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", > + "BriefDescription": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", > + "EventName": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800040491", > + "MSRValue": "0x100400120", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > + "BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.ANY_SNOOP OCR.ALL_PF_RFO.SUPPLIER_NONE.ANY_SNOOP", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > + "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.ANY_SNOOP", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400040491", > + "MSRValue": "0x3F80020120", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", > + "BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HITM_OTHER_CORE OCR.ALL_PF_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", > + "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100040491", > + "MSRValue": "0x1000020120", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_MISS", > + "BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_MISS", > + "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200040491", > + "MSRValue": "0x800020120", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_NONE", > + "BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_NONE", > + "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80040491", > + "MSRValue": "0x400020120", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT_S.ANY_SNOOP", > + "BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.ANY_SNOOP", > + "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80100491", > + "MSRValue": "0x100020120", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", > + "BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_MISS", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", > + "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_MISS", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000100491", > + "MSRValue": "0x200020120", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", > + "BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NONE", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", > + "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NONE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800100491", > + "MSRValue": "0x80020120", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > + "BriefDescription": "OCR.ALL_READS.ANY_RESPONSE have any response type.", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > + "EventName": "OCR.ALL_READS.ANY_RESPONSE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400100491", > + "MSRValue": "0x107F7", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", > + "BriefDescription": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_READS.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", > + "EventName": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100100491", > + "MSRValue": "0x3F804007F7", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_MISS", > + "BriefDescription": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_MISS", > + "EventName": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200100491", > + "MSRValue": "0x804007F7", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_NONE", > + "BriefDescription": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_NONE", > + "EventName": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80100491", > + "MSRValue": "0x1004007F7", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > + "BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.ANY_SNOOP OCR.ALL_READS.SUPPLIER_NONE.ANY_SNOOP", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > + "EventName": "OCR.ALL_READS.SUPPLIER_NONE.ANY_SNOOP", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80400491", > + "MSRValue": "0x3F800207F7", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > + "BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.HITM_OTHER_CORE OCR.ALL_READS.SUPPLIER_NONE.HITM_OTHER_CORE", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > + "EventName": "OCR.ALL_READS.SUPPLIER_NONE.HITM_OTHER_CORE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80400491", > + "MSRValue": "0x10000207F7", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > + "BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_FWD OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > + "EventName": "OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100400491", > + "MSRValue": "0x8000207F7", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.ANY_SNOOP OCR.ALL_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", > + "BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", > + "EventName": "OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80020491", > + "MSRValue": "0x4000207F7", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE OCR.ALL_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", > + "BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.NO_SNOOP_NEEDED OCR.ALL_READS.SUPPLIER_NONE.NO_SNOOP_NEEDED", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", > + "EventName": "OCR.ALL_READS.SUPPLIER_NONE.NO_SNOOP_NEEDED", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000020491", > + "MSRValue": "0x1000207F7", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > + "BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.SNOOP_MISS", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > + "EventName": "OCR.ALL_READS.SUPPLIER_NONE.SNOOP_MISS", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800020491", > + "MSRValue": "0x2000207F7", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > + "BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.SNOOP_NONE", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > + "EventName": "OCR.ALL_READS.SUPPLIER_NONE.SNOOP_NONE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400020491", > + "MSRValue": "0x800207F7", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", > + "BriefDescription": "OCR.ALL_RFO.ANY_RESPONSE have any response type.", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", > + "EventName": "OCR.ALL_RFO.ANY_RESPONSE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100020491", > + "MSRValue": "0x10122", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", > + "BriefDescription": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", > + "EventName": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200020491", > + "MSRValue": "0x3F80400122", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", > + "BriefDescription": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", > + "EventName": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80020491", > + "MSRValue": "0x80400122", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.ANY_RESPONSE have any response type.", > + "BriefDescription": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.ANY_RESPONSE", > + "EventName": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10490", > + "MSRValue": "0x100400122", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP", > + "BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.ANY_SNOOP OCR.ALL_RFO.SUPPLIER_NONE.ANY_SNOOP", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP", > + "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.ANY_SNOOP", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F803C0490", > + "MSRValue": "0x3F80020122", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE", > + "BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.HITM_OTHER_CORE OCR.ALL_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE", > + "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10003C0490", > + "MSRValue": "0x1000020122", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", > + "BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", > + "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x8003C0490", > + "MSRValue": "0x800020122", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", > + "BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", > + "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x4003C0490", > + "MSRValue": "0x400020122", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", > + "BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED OCR.ALL_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", > + "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1003C0490", > + "MSRValue": "0x100020122", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", > + "BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_MISS", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", > + "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_MISS", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x8007C0490", > + "MSRValue": "0x200020122", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS", > + "BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_NONE", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS", > + "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_NONE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x2003C0490", > + "MSRValue": "0x80020122", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE", > + "BriefDescription": "Counts all demand code reads have any response type.", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE", > + "EventName": "OCR.DEMAND_CODE_RD.ANY_RESPONSE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x803C0490", > + "MSRValue": "0x10004", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT_E.ANY_SNOOP", > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.ANY_SNOOP", > + "EventName": "OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80080490", > + "MSRValue": "0x3F80400004", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", > + "EventName": "OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000080490", > + "MSRValue": "0x80400004", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", > + "EventName": "OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800080490", > + "MSRValue": "0x100400004", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.SUPPLIER_NONE.ANY_SNOOP", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > + "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.ANY_SNOOP", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400080490", > + "MSRValue": "0x3F80020004", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HITM_OTHER_CORE", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", > + "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HITM_OTHER_CORE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100080490", > + "MSRValue": "0x1000020004", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_MISS", > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_MISS", > + "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200080490", > + "MSRValue": "0x800020004", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_NONE", > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_NONE", > + "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80080490", > + "MSRValue": "0x400020004", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT_F.ANY_SNOOP", > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.ANY_SNOOP", > + "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80200490", > + "MSRValue": "0x100020004", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", > + "BriefDescription": "Counts all demand code reads", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", > + "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_MISS", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000200490", > + "MSRValue": "0x200020004", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", > + "BriefDescription": "Counts all demand code reads", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", > + "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NONE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800200490", > + "MSRValue": "0x80020004", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > + "BriefDescription": "Counts demand data reads have any response type.", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > + "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400200490", > + "MSRValue": "0x10001", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", > + "EventName": "OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100200490", > + "MSRValue": "0x3F80400001", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_MISS", > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_MISS", > + "EventName": "OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200200490", > + "MSRValue": "0x80400001", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_NONE", > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_NONE", > + "EventName": "OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80200490", > + "MSRValue": "0x100400001", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT_M.ANY_SNOOP", > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.ANY_SNOOP", > + "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80040490", > + "MSRValue": "0x3F80020001", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", > + "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000040490", > + "MSRValue": "0x1000020001", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", > + "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800040490", > + "MSRValue": "0x800020001", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > + "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400040490", > + "MSRValue": "0x400020001", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", > + "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100040490", > + "MSRValue": "0x100020001", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_MISS", > + "BriefDescription": "Counts demand data reads", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200040490", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_NONE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80040490", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT_S.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80100490", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000100490", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800100490", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400100490", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100100490", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_MISS", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200100490", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_NONE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80100490", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80400490", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80400490", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100400490", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.ANY_SNOOP OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80020490", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000020490", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800020490", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400020490", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100020490", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200020490", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80020490", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.ANY_RESPONSE have any response type.", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.ANY_RESPONSE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F803C0120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10003C0120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x8003C0120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x4003C0120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1003C0120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x8007C0120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_MISS OCR.ALL_PF_RFO.L3_HIT.SNOOP_MISS", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x2003C0120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_NONE OCR.ALL_PF_RFO.L3_HIT.SNOOP_NONE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x803C0120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT_E.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80080120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT_E.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000080120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800080120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400080120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT_E.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100080120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_MISS", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200080120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_NONE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80080120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT_F.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80200120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT_F.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000200120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800200120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400200120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT_F.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100200120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_MISS", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200200120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_NONE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80200120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT_M.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80040120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT_M.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000040120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800040120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400040120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT_M.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100040120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_MISS", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200040120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_NONE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80040120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT_S.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80100120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT_S.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000100120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800100120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400100120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT_S.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100100120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_MISS", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200100120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_NONE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80100120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80400120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80400120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100400120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.ANY_SNOOP OCR.ALL_PF_RFO.SUPPLIER_NONE.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80020120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HITM_OTHER_CORE OCR.ALL_PF_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000020120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800020120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400020120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100020120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_MISS", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200020120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NONE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80020120", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.ANY_RESPONSE have any response type.", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.ANY_RESPONSE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x107F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.L3_HIT.ANY_SNOOP OCR.ALL_READS.L3_HIT.ANY_SNOOP OCR.ALL_READS.L3_HIT.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.L3_HIT.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F803C07F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10003C07F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x8003C07F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x4003C07F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1003C07F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.L3_HIT.SNOOP_HIT_WITH_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.L3_HIT.SNOOP_HIT_WITH_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x8007C07F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.L3_HIT.SNOOP_MISS OCR.ALL_READS.L3_HIT.SNOOP_MISS", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.L3_HIT.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x2003C07F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.L3_HIT.SNOOP_NONE OCR.ALL_READS.L3_HIT.SNOOP_NONE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.L3_HIT.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x803C07F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.L3_HIT_E.ANY_SNOOP OCR.ALL_READS.L3_HIT_E.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.L3_HIT_E.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F800807F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.L3_HIT_E.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT_E.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.L3_HIT_E.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10000807F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x8000807F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x4000807F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.L3_HIT_E.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT_E.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.L3_HIT_E.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000807F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.L3_HIT_E.SNOOP_MISS", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.L3_HIT_E.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x2000807F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.L3_HIT_E.SNOOP_NONE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.L3_HIT_E.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800807F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.L3_HIT_F.ANY_SNOOP OCR.ALL_READS.L3_HIT_F.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.L3_HIT_F.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F802007F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.L3_HIT_F.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT_F.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.L3_HIT_F.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10002007F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x8002007F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x4002007F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.L3_HIT_F.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT_F.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.L3_HIT_F.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1002007F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.L3_HIT_F.SNOOP_MISS", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.L3_HIT_F.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x2002007F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.L3_HIT_F.SNOOP_NONE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.L3_HIT_F.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x802007F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.L3_HIT_M.ANY_SNOOP OCR.ALL_READS.L3_HIT_M.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.L3_HIT_M.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F800407F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.L3_HIT_M.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT_M.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.L3_HIT_M.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10000407F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x8000407F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x4000407F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.L3_HIT_M.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT_M.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.L3_HIT_M.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000407F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.L3_HIT_M.SNOOP_MISS", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.L3_HIT_M.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x2000407F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.L3_HIT_M.SNOOP_NONE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.L3_HIT_M.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800407F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.L3_HIT_S.ANY_SNOOP OCR.ALL_READS.L3_HIT_S.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.L3_HIT_S.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F801007F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.L3_HIT_S.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT_S.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.L3_HIT_S.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10001007F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x8001007F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x4001007F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.L3_HIT_S.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT_S.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.L3_HIT_S.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1001007F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.L3_HIT_S.SNOOP_MISS", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.L3_HIT_S.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x2001007F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.L3_HIT_S.SNOOP_NONE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.L3_HIT_S.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x801007F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_READS.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F804007F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x804007F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1004007F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.ANY_SNOOP OCR.ALL_READS.SUPPLIER_NONE.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.SUPPLIER_NONE.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F800207F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.HITM_OTHER_CORE OCR.ALL_READS.SUPPLIER_NONE.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.SUPPLIER_NONE.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10000207F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_FWD OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x8000207F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x4000207F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.NO_SNOOP_NEEDED OCR.ALL_READS.SUPPLIER_NONE.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.SUPPLIER_NONE.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000207F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.SNOOP_MISS", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.SUPPLIER_NONE.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x2000207F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.SNOOP_NONE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_READS.SUPPLIER_NONE.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800207F7", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.ANY_RESPONSE have any response type.", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.ANY_RESPONSE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.L3_HIT.ANY_SNOOP OCR.ALL_RFO.L3_HIT.ANY_SNOOP OCR.ALL_RFO.L3_HIT.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.L3_HIT.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F803C0122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10003C0122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x8003C0122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x4003C0122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1003C0122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x8007C0122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.L3_HIT.SNOOP_MISS OCR.ALL_RFO.L3_HIT.SNOOP_MISS", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.L3_HIT.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x2003C0122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.L3_HIT.SNOOP_NONE OCR.ALL_RFO.L3_HIT.SNOOP_NONE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.L3_HIT.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x803C0122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.ANY_SNOOP OCR.ALL_RFO.L3_HIT_E.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.L3_HIT_E.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80080122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT_E.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.L3_HIT_E.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000080122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800080122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400080122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT_E.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.L3_HIT_E.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100080122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.SNOOP_MISS", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.L3_HIT_E.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200080122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.SNOOP_NONE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.L3_HIT_E.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80080122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.ANY_SNOOP OCR.ALL_RFO.L3_HIT_F.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.L3_HIT_F.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80200122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT_F.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.L3_HIT_F.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000200122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800200122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400200122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT_F.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.L3_HIT_F.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100200122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.SNOOP_MISS", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.L3_HIT_F.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200200122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.SNOOP_NONE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.L3_HIT_F.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80200122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.ANY_SNOOP OCR.ALL_RFO.L3_HIT_M.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.L3_HIT_M.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80040122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT_M.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.L3_HIT_M.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000040122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800040122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400040122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT_M.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.L3_HIT_M.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100040122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.SNOOP_MISS", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.L3_HIT_M.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200040122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.SNOOP_NONE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.L3_HIT_M.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80040122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.ANY_SNOOP OCR.ALL_RFO.L3_HIT_S.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.L3_HIT_S.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80100122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT_S.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.L3_HIT_S.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000100122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800100122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400100122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT_S.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.L3_HIT_S.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100100122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.SNOOP_MISS", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.L3_HIT_S.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200100122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.SNOOP_NONE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.L3_HIT_S.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80100122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80400122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80400122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100400122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.ANY_SNOOP OCR.ALL_RFO.SUPPLIER_NONE.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80020122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.HITM_OTHER_CORE OCR.ALL_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000020122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800020122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400020122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED OCR.ALL_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100020122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_MISS", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200020122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_NONE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80020122", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads have any response type.", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.ANY_RESPONSE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP OCR.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F803C0004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE OCR.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10003C0004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x8003C0004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x4003C0004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDED OCR.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1003C0004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x8007C0004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x2003C0004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NONE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x803C0004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_E.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80080004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_E.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000080004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800080004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400080004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_E.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100080004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200080004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80080004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_F.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80200004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_F.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000200004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800200004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400200004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_F.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100200004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200200004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80200004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_M.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80040004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_M.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000040004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800040004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400040004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_M.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100040004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200040004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80040004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_S.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80100004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_S.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000100004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800100004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400100004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_S.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100100004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200100004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80100004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80400004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80400004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100400004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.SUPPLIER_NONE.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80020004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000020004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800020004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400020004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100020004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200020004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand code reads", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80020004", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads have any response type.", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP OCR.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F803C0001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10003C0001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x8003C0001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x4003C0001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1003C0001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x8007C0001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x2003C0001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NONE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x803C0001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_E.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80080001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000080001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800080001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400080001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100080001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200080001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80080001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_F.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80200001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000200001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800200001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400200001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100200001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200200001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80200001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_M.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80040001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000040001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800040001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400040001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100040001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200040001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80040001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_S.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80100001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000100001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800100001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400100001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100100001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200100001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80100001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80400001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80400001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100400001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80020001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000020001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800020001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400020001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100020001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200020001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts demand data reads", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80020001", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs) have any response type.", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.ANY_SNOOP OCR.DEMAND_RFO.L3_HIT.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.L3_HIT.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F803C0002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10003C0002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x8003C0002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x4003C0002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1003C0002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs)", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x8007C0002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x2003C0002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.SNOOP_NONE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x803C0002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_E.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.L3_HIT_E.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80080002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_E.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.L3_HIT_E.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000080002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800080002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400080002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_E.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.L3_HIT_E.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100080002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs)", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.L3_HIT_E.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200080002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs)", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.L3_HIT_E.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80080002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_F.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.L3_HIT_F.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80200002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_F.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.L3_HIT_F.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000200002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800200002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400200002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_F.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.L3_HIT_F.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100200002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs)", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.L3_HIT_F.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200200002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs)", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.L3_HIT_F.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80200002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_M.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.L3_HIT_M.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80040002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_M.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.L3_HIT_M.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000040002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800040002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400040002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_M.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.L3_HIT_M.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100040002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs)", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.L3_HIT_M.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200040002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs)", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.L3_HIT_M.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80040002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_S.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.L3_HIT_S.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80100002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_S.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.L3_HIT_S.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000100002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800100002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400100002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_S.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.L3_HIT_S.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100100002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs)", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.L3_HIT_S.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200100002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs)", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.L3_HIT_S.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80100002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80400002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80400002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100400002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.SUPPLIER_NONE.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80020002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000020002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800020002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400020002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100020002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs)", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200020002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all demand data writes (RFOs)", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80020002", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests have any response type.", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.ANY_RESPONSE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x18000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.ANY_SNOOP OCR.OTHER.L3_HIT.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.L3_HIT.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F803C8000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.HITM_OTHER_CORE OCR.OTHER.L3_HIT.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.L3_HIT.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10003C8000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.HIT_OTHER_CORE_FWD OCR.OTHER.L3_HIT.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.L3_HIT.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x8003C8000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.OTHER.L3_HIT.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.L3_HIT.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x4003C8000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.NO_SNOOP_NEEDED OCR.OTHER.L3_HIT.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.L3_HIT.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1003C8000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.L3_HIT.SNOOP_HIT_WITH_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x8007C8000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.SNOOP_MISS", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.L3_HIT.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x2003C8000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.SNOOP_NONE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.L3_HIT.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x803C8000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_E.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.L3_HIT_E.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80088000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_E.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.L3_HIT_E.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000088000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800088000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400088000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_E.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.L3_HIT_E.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100088000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.L3_HIT_E.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200088000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.L3_HIT_E.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80088000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_F.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.L3_HIT_F.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80208000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_F.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.L3_HIT_F.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000208000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800208000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400208000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_F.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.L3_HIT_F.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100208000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.L3_HIT_F.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200208000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.L3_HIT_F.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80208000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_M.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.L3_HIT_M.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80048000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_M.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.L3_HIT_M.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000048000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800048000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400048000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_M.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.L3_HIT_M.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100048000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.L3_HIT_M.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200048000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.L3_HIT_M.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80048000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_S.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.L3_HIT_S.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80108000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_S.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.L3_HIT_S.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000108000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800108000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400108000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_S.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.L3_HIT_S.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100108000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.L3_HIT_S.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200108000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.L3_HIT_S.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80108000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests OCR.OTHER.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80408000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80408000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100408000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests OCR.OTHER.SUPPLIER_NONE.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.SUPPLIER_NONE.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80028000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests OCR.OTHER.SUPPLIER_NONE.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.SUPPLIER_NONE.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000028000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800028000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400028000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests OCR.OTHER.SUPPLIER_NONE.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.SUPPLIER_NONE.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100028000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.SUPPLIER_NONE.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200028000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts any other requests", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.OTHER.SUPPLIER_NONE.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80028000", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests have any response type.", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.ANY_RESPONSE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.ANY_SNOOP OCR.PF_L1D_AND_SW.L3_HIT.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F803C0400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.HITM_OTHER_CORE OCR.PF_L1D_AND_SW.L3_HIT.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10003C0400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x8003C0400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x4003C0400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1003C0400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_HIT_WITH_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x8007C0400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_MISS", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x2003C0400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_NONE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x803C0400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_E.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80080400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_E.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000080400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800080400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400080400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_E.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100080400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200080400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80080400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_F.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80200400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_F.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000200400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800200400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400200400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_F.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100200400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200200400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80200400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_M.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80040400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_M.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000040400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800040400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400040400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_M.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100040400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200040400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80040400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_S.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80100400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_S.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000100400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800100400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400100400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_S.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100100400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200100400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80100400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80400400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80400400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100400400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.SUPPLIER_NONE.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80020400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000020400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800020400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400020400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.SUPPLIER_NONE.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100020400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200020400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80020400", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads have any response type.", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.ANY_RESPONSE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP OCR.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F803C0010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.PF_L2_DATA_RD.L3_HIT.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10003C0010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x8003C0010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x4003C0010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1003C0010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x8007C0010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_MISS", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x2003C0010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_NONE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x803C0010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_E.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80080010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000080010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800080010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400080010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100080010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200080010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80080010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_F.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80200010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000200010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800200010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400200010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100200010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200200010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80200010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_M.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80040010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000040010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800040010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400040010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100040010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200040010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80040010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_S.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80100010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000100010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800100010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400100010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100100010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200100010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80100010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80400010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80400010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100400010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80020010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000020010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800020010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400020010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100020010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200020010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80020010", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs have any response type.", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.ANY_RESPONSE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.ANY_SNOOP OCR.PF_L2_RFO.L3_HIT.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.L3_HIT.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F803C0020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10003C0020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x8003C0020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x4003C0020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1003C0020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x8007C0020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.SNOOP_MISS", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.L3_HIT.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x2003C0020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.SNOOP_NONE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.L3_HIT.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x803C0020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_E.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.L3_HIT_E.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80080020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_E.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.L3_HIT_E.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000080020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800080020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400080020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_E.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.L3_HIT_E.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100080020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.L3_HIT_E.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200080020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.L3_HIT_E.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80080020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_F.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.L3_HIT_F.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80200020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_F.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.L3_HIT_F.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000200020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800200020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400200020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_F.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.L3_HIT_F.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100200020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.L3_HIT_F.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200200020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.L3_HIT_F.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80200020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_M.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.L3_HIT_M.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80040020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_M.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.L3_HIT_M.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000040020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800040020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400040020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_M.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.L3_HIT_M.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100040020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.L3_HIT_M.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200040020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.L3_HIT_M.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80040020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_S.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.L3_HIT_S.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80100020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_S.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.L3_HIT_S.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000100020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800100020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400100020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_S.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.L3_HIT_S.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100100020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.L3_HIT_S.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200100020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.L3_HIT_S.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80100020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80400020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80400020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100400020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.SUPPLIER_NONE.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80020020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000020020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800020020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400020020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100020020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200020020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80020020", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads have any response type.", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.ANY_RESPONSE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10080", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP OCR.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F803C0080", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.PF_L3_DATA_RD.L3_HIT.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10003C0080", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x8003C0080", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x4003C0080", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1003C0080", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x8007C0080", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_MISS", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x2003C0080", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_NONE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_NONE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x803C0080", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_E.ANY_SNOOP", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.ANY_SNOOP", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80080080", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000080080", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800080080", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400080080", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100080080", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.SNOOP_MISS", > - "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200080080", > - "Offcore": "1", > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > - "SampleAfterValue": "100003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3", > - "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.SNOOP_NONE", > + "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80080080", > + "MSRValue": "0x200020001", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_F.ANY_SNOOP", > + "BriefDescription": "Counts demand data reads", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.ANY_SNOOP", > + "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80200080", > + "MSRValue": "0x80020001", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", > + "BriefDescription": "Counts all demand data writes (RFOs) have any response type.", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", > + "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000200080", > + "MSRValue": "0x10002", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", > + "EventName": "OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800200080", > + "MSRValue": "0x3F80400002", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > + "EventName": "OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400200080", > + "MSRValue": "0x80400002", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", > + "EventName": "OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100200080", > + "MSRValue": "0x100400002", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.SUPPLIER_NONE.ANY_SNOOP", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.SNOOP_MISS", > + "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.ANY_SNOOP", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200200080", > + "MSRValue": "0x3F80020002", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.SNOOP_NONE", > + "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80200080", > + "MSRValue": "0x1000020002", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_M.ANY_SNOOP", > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.ANY_SNOOP", > + "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80040080", > + "MSRValue": "0x800020002", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", > + "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000040080", > + "MSRValue": "0x400020002", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", > + "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800040080", > + "MSRValue": "0x100020002", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > + "BriefDescription": "Counts all demand data writes (RFOs)", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > + "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.SNOOP_MISS", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400040080", > + "MSRValue": "0x200020002", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", > + "BriefDescription": "Counts all demand data writes (RFOs)", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", > + "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.SNOOP_NONE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100040080", > + "MSRValue": "0x80020002", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", > + "BriefDescription": "Counts any other requests have any response type.", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.SNOOP_MISS", > + "EventName": "OCR.OTHER.ANY_RESPONSE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200040080", > + "MSRValue": "0x18000", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", > + "BriefDescription": "Counts any other requests OCR.OTHER.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.SNOOP_NONE", > + "EventName": "OCR.OTHER.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80040080", > + "MSRValue": "0x3F80408000", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_S.ANY_SNOOP", > + "BriefDescription": "Counts any other requests OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.ANY_SNOOP", > + "EventName": "OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80100080", > + "MSRValue": "0x80408000", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", > + "BriefDescription": "Counts any other requests OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", > + "EventName": "OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000100080", > + "MSRValue": "0x100408000", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", > + "BriefDescription": "Counts any other requests OCR.OTHER.SUPPLIER_NONE.ANY_SNOOP", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", > + "EventName": "OCR.OTHER.SUPPLIER_NONE.ANY_SNOOP", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800100080", > + "MSRValue": "0x3F80028000", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > + "BriefDescription": "Counts any other requests OCR.OTHER.SUPPLIER_NONE.HITM_OTHER_CORE", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > + "EventName": "OCR.OTHER.SUPPLIER_NONE.HITM_OTHER_CORE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400100080", > + "MSRValue": "0x1000028000", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", > + "BriefDescription": "Counts any other requests OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", > + "EventName": "OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100100080", > + "MSRValue": "0x800028000", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", > + "BriefDescription": "Counts any other requests OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.SNOOP_MISS", > + "EventName": "OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200100080", > + "MSRValue": "0x400028000", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", > + "BriefDescription": "Counts any other requests OCR.OTHER.SUPPLIER_NONE.NO_SNOOP_NEEDED", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.SNOOP_NONE", > + "EventName": "OCR.OTHER.SUPPLIER_NONE.NO_SNOOP_NEEDED", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80100080", > + "MSRValue": "0x100028000", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > + "BriefDescription": "Counts any other requests", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > + "EventName": "OCR.OTHER.SUPPLIER_NONE.SNOOP_MISS", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80400080", > + "MSRValue": "0x200028000", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > + "BriefDescription": "Counts any other requests", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > + "EventName": "OCR.OTHER.SUPPLIER_NONE.SNOOP_NONE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80400080", > + "MSRValue": "0x80028000", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests have any response type.", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > + "EventName": "OCR.PF_L1D_AND_SW.ANY_RESPONSE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100400080", > + "MSRValue": "0x10400", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", > + "EventName": "OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80020080", > + "MSRValue": "0x3F80400400", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", > + "EventName": "OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000020080", > + "MSRValue": "0x80400400", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > + "EventName": "OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800020080", > + "MSRValue": "0x100400400", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.SUPPLIER_NONE.ANY_SNOOP", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > + "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.ANY_SNOOP", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400020080", > + "MSRValue": "0x3F80020400", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HITM_OTHER_CORE", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", > + "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HITM_OTHER_CORE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100020080", > + "MSRValue": "0x1000020400", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", > + "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200020080", > + "MSRValue": "0x800020400", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", > + "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80020080", > + "MSRValue": "0x400020400", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs have any response type.", > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.SUPPLIER_NONE.NO_SNOOP_NEEDED", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_RFO.ANY_RESPONSE", > + "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.NO_SNOOP_NEEDED", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10100", > + "MSRValue": "0x100020400", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.ANY_SNOOP OCR.PF_L3_RFO.L3_HIT.ANY_SNOOP", > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_RFO.L3_HIT.ANY_SNOOP", > + "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.SNOOP_MISS", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F803C0100", > + "MSRValue": "0x200020400", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.HITM_OTHER_CORE OCR.PF_L3_RFO.L3_HIT.HITM_OTHER_CORE", > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_RFO.L3_HIT.HITM_OTHER_CORE", > + "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.SNOOP_NONE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x10003C0100", > + "MSRValue": "0x80020400", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_FWD", > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads have any response type.", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_FWD", > + "EventName": "OCR.PF_L2_DATA_RD.ANY_RESPONSE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x8003C0100", > + "MSRValue": "0x10010", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", > + "EventName": "OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x4003C0100", > + "MSRValue": "0x3F80400010", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED", > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED", > + "EventName": "OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1003C0100", > + "MSRValue": "0x80400010", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", > + "EventName": "OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x8007C0100", > + "MSRValue": "0x100400010", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.SNOOP_MISS", > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_RFO.L3_HIT.SNOOP_MISS", > + "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x2003C0100", > + "MSRValue": "0x3F80020010", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.SNOOP_NONE", > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_RFO.L3_HIT.SNOOP_NONE", > + "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x803C0100", > + "MSRValue": "0x1000020010", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_E.ANY_SNOOP", > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_RFO.L3_HIT_E.ANY_SNOOP", > + "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80080100", > + "MSRValue": "0x800020010", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_E.HITM_OTHER_CORE", > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_RFO.L3_HIT_E.HITM_OTHER_CORE", > + "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000080100", > + "MSRValue": "0x400020010", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", > + "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800080100", > + "MSRValue": "0x100020010", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > + "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400080100", > + "MSRValue": "0x200020010", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_E.NO_SNOOP_NEEDED", > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_RFO.L3_HIT_E.NO_SNOOP_NEEDED", > + "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100080100", > + "MSRValue": "0x80020010", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs have any response type.", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_RFO.L3_HIT_E.SNOOP_MISS", > + "EventName": "OCR.PF_L2_RFO.ANY_RESPONSE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200080100", > + "MSRValue": "0x10020", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_RFO.L3_HIT_E.SNOOP_NONE", > + "EventName": "OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80080100", > + "MSRValue": "0x3F80400020", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_F.ANY_SNOOP", > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_RFO.L3_HIT_F.ANY_SNOOP", > + "EventName": "OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80200100", > + "MSRValue": "0x80400020", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_F.HITM_OTHER_CORE", > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_RFO.L3_HIT_F.HITM_OTHER_CORE", > + "EventName": "OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000200100", > + "MSRValue": "0x100400020", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.SUPPLIER_NONE.ANY_SNOOP", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", > + "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.ANY_SNOOP", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800200100", > + "MSRValue": "0x3F80020020", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > + "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400200100", > + "MSRValue": "0x1000020020", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_F.NO_SNOOP_NEEDED", > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_RFO.L3_HIT_F.NO_SNOOP_NEEDED", > + "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100200100", > + "MSRValue": "0x800020020", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_RFO.L3_HIT_F.SNOOP_MISS", > + "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200200100", > + "MSRValue": "0x400020020", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_RFO.L3_HIT_F.SNOOP_NONE", > + "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80200100", > + "MSRValue": "0x100020020", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_M.ANY_SNOOP", > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_RFO.L3_HIT_M.ANY_SNOOP", > + "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.SNOOP_MISS", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80040100", > + "MSRValue": "0x200020020", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_M.HITM_OTHER_CORE", > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_RFO.L3_HIT_M.HITM_OTHER_CORE", > + "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.SNOOP_NONE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000040100", > + "MSRValue": "0x80020020", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads have any response type.", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", > + "EventName": "OCR.PF_L3_DATA_RD.ANY_RESPONSE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800040100", > + "MSRValue": "0x10080", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > + "EventName": "OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400040100", > + "MSRValue": "0x3F80400080", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_M.NO_SNOOP_NEEDED", > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_RFO.L3_HIT_M.NO_SNOOP_NEEDED", > + "EventName": "OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100040100", > + "MSRValue": "0x80400080", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_RFO.L3_HIT_M.SNOOP_MISS", > + "EventName": "OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200040100", > + "MSRValue": "0x100400080", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_RFO.L3_HIT_M.SNOOP_NONE", > + "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80040100", > + "MSRValue": "0x3F80020080", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_S.ANY_SNOOP", > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_RFO.L3_HIT_S.ANY_SNOOP", > + "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x3F80100100", > + "MSRValue": "0x1000020080", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_S.HITM_OTHER_CORE", > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_RFO.L3_HIT_S.HITM_OTHER_CORE", > + "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x1000100100", > + "MSRValue": "0x800020080", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", > + "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x800100100", > + "MSRValue": "0x400020080", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > + "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x400100100", > + "MSRValue": "0x100020080", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_S.NO_SNOOP_NEEDED", > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_RFO.L3_HIT_S.NO_SNOOP_NEEDED", > + "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x100100100", > + "MSRValue": "0x200020080", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_RFO.L3_HIT_S.SNOOP_MISS", > + "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x200100100", > + "MSRValue": "0x80020080", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > }, > { > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs have any response type.", > "Counter": "0,1,2,3", > "CounterHTOff": "0,1,2,3", > "EventCode": "0xB7, 0xBB", > - "EventName": "OCR.PF_L3_RFO.L3_HIT_S.SNOOP_NONE", > + "EventName": "OCR.PF_L3_RFO.ANY_RESPONSE", > "MSRIndex": "0x1a6,0x1a7", > - "MSRValue": "0x80100100", > + "MSRValue": "0x10100", > "Offcore": "1", > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > @@ -8622,41 +2070,5 @@ > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > "SampleAfterValue": "100003", > "UMask": "0x1" > - }, > - { > - "BriefDescription": "Number of PREFETCHNTA instructions executed.", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3,4,5,6,7", > - "EventCode": "0x32", > - "EventName": "SW_PREFETCH_ACCESS.NTA", > - "SampleAfterValue": "2000003", > - "UMask": "0x1" > - }, > - { > - "BriefDescription": "Number of PREFETCHW instructions executed.", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3,4,5,6,7", > - "EventCode": "0x32", > - "EventName": "SW_PREFETCH_ACCESS.PREFETCHW", > - "SampleAfterValue": "2000003", > - "UMask": "0x8" > - }, > - { > - "BriefDescription": "Number of PREFETCHT0 instructions executed.", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3,4,5,6,7", > - "EventCode": "0x32", > - "EventName": "SW_PREFETCH_ACCESS.T0", > - "SampleAfterValue": "2000003", > - "UMask": "0x2" > - }, > - { > - "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.", > - "Counter": "0,1,2,3", > - "CounterHTOff": "0,1,2,3,4,5,6,7", > - "EventCode": "0x32", > - "EventName": "SW_PREFETCH_ACCESS.T1_T2", > - "SampleAfterValue": "2000003", > - "UMask": "0x4" > } > ] > \ No newline at end of file -- Zhengjun Xing ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 1/8] perf vendor events: Update events for CascadelakeX 2022-03-18 9:09 ` [PATCH 1/8] perf vendor events: Update events for CascadelakeX Xing Zhengjun @ 2022-03-18 14:44 ` Arnaldo Carvalho de Melo 0 siblings, 0 replies; 18+ messages in thread From: Arnaldo Carvalho de Melo @ 2022-03-18 14:44 UTC (permalink / raw) To: Xing Zhengjun Cc: Ian Rogers, Kan Liang, Peter Zijlstra, Ingo Molnar, Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim, Maxime Coquelin, Alexandre Torgue, Andi Kleen, James Clark, John Garry, linux-kernel, linux-perf-users, Stephane Eranian Em Fri, Mar 18, 2022 at 05:09:40PM +0800, Xing Zhengjun escreveu: > On 3/18/2022 2:28 AM, Ian Rogers wrote: > > The change: > > https://github.com/intel/event-converter-for-linux-perf/commit/fc680410402e394eed6a1ebd909c9f649d3ed3ef > > moved certain "other" type of events in to the cache topic. Update the > > perf json files for this change. > > > > Tested: > > ``` > > ... > > 6: Parse event definition strings : Ok > > 7: Simple expression parser : Ok > > 8: PERF_RECORD_* events & perf_sample fields : Ok > > 9: Parse perf pmu format : Ok > > 10: PMU events : > > 10.1: PMU event table sanity : Ok > > 10.2: PMU event map aliases : Ok > > 10.3: Parsing of PMU event table metrics : Ok > > 10.4: Parsing of PMU event table metrics with fake PMUs : Ok > > ... > > 68: Parse and process metrics : Ok > > ... > > 89: perf all metricgroups test : Ok > > 90: perf all metrics test : FAILED! > > 91: perf all PMU test : Ok > > ... > > ``` > > > > Test 90 failed due to MEM_PMM_Read_Latency as the test machine > > lacks optane memory, and the divide by 0 causes the metric not to > > print - which is intended behavior. > > > > Signed-off-by: Ian Rogers <irogers@google.com> > > Reviewed-by: Zhengjun Xing <zhengjun.xing@linux.intel.com> Thanks, applied the series. - Arnaldo > > --- > > .../arch/x86/cascadelakex/cache.json | 6588 +++++++++++++++ > > .../arch/x86/cascadelakex/other.json | 7446 +---------------- > > 2 files changed, 7017 insertions(+), 7017 deletions(-) > > > > diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/cache.json b/tools/perf/pmu-events/arch/x86/cascadelakex/cache.json > > index 732bf51e35af..aa906a7fa520 100644 > > --- a/tools/perf/pmu-events/arch/x86/cascadelakex/cache.json > > +++ b/tools/perf/pmu-events/arch/x86/cascadelakex/cache.json > > @@ -602,6 +602,6558 @@ > > "SampleAfterValue": "100003", > > "UMask": "0x80" > > }, > > + { > > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x3F803C0491", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x10003C0491", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x8003C0491", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x4003C0491", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x1003C0491", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x8007C0491", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_MISS OCR.ALL_DATA_RD.L3_HIT.SNOOP_MISS", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_MISS", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x2003C0491", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_NONE OCR.ALL_DATA_RD.L3_HIT.SNOOP_NONE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_NONE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x803C0491", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT_E.ANY_SNOOP", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.ANY_SNOOP", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x3F80080491", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x1000080491", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x800080491", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x400080491", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x100080491", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_MISS", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_MISS", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x200080491", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_NONE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_NONE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x80080491", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT_F.ANY_SNOOP", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.ANY_SNOOP", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x3F80200491", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x1000200491", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x800200491", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x400200491", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x100200491", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_MISS", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_MISS", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x200200491", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_NONE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_NONE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x80200491", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT_M.ANY_SNOOP", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.ANY_SNOOP", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x3F80040491", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x1000040491", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x800040491", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x400040491", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x100040491", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_MISS", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_MISS", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x200040491", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_NONE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_NONE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x80040491", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT_S.ANY_SNOOP", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.ANY_SNOOP", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x3F80100491", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x1000100491", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x800100491", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x400100491", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x100100491", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_MISS", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_MISS", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x200100491", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_NONE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_NONE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x80100491", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x3F803C0490", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x10003C0490", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x8003C0490", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x4003C0490", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x1003C0490", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x8007C0490", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x2003C0490", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x803C0490", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT_E.ANY_SNOOP", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.ANY_SNOOP", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x3F80080490", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x1000080490", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x800080490", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x400080490", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x100080490", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_MISS", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_MISS", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x200080490", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_NONE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_NONE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x80080490", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT_F.ANY_SNOOP", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.ANY_SNOOP", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x3F80200490", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x1000200490", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x800200490", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x400200490", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x100200490", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_MISS", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_MISS", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x200200490", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_NONE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_NONE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x80200490", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT_M.ANY_SNOOP", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.ANY_SNOOP", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x3F80040490", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x1000040490", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x800040490", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x400040490", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x100040490", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_MISS", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_MISS", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x200040490", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_NONE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_NONE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x80040490", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT_S.ANY_SNOOP", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.ANY_SNOOP", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x3F80100490", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x1000100490", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x800100490", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x400100490", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x100100490", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_MISS", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_MISS", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x200100490", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_NONE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_NONE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x80100490", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x3F803C0120", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x10003C0120", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x8003C0120", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x4003C0120", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x1003C0120", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x8007C0120", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_MISS OCR.ALL_PF_RFO.L3_HIT.SNOOP_MISS", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_MISS", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x2003C0120", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_NONE OCR.ALL_PF_RFO.L3_HIT.SNOOP_NONE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_NONE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x803C0120", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT_E.ANY_SNOOP", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.ANY_SNOOP", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x3F80080120", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT_E.HITM_OTHER_CORE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.HITM_OTHER_CORE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x1000080120", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x800080120", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x400080120", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT_E.NO_SNOOP_NEEDED", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.NO_SNOOP_NEEDED", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x100080120", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_MISS", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_MISS", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x200080120", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_NONE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_NONE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x80080120", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT_F.ANY_SNOOP", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.ANY_SNOOP", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x3F80200120", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT_F.HITM_OTHER_CORE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.HITM_OTHER_CORE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x1000200120", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x800200120", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x400200120", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT_F.NO_SNOOP_NEEDED", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.NO_SNOOP_NEEDED", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x100200120", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_MISS", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_MISS", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x200200120", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_NONE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_NONE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x80200120", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT_M.ANY_SNOOP", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.ANY_SNOOP", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x3F80040120", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT_M.HITM_OTHER_CORE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.HITM_OTHER_CORE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x1000040120", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x800040120", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x400040120", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT_M.NO_SNOOP_NEEDED", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.NO_SNOOP_NEEDED", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x100040120", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_MISS", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_MISS", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x200040120", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_NONE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_NONE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x80040120", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT_S.ANY_SNOOP", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.ANY_SNOOP", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x3F80100120", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT_S.HITM_OTHER_CORE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.HITM_OTHER_CORE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x1000100120", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x800100120", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x400100120", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT_S.NO_SNOOP_NEEDED", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.NO_SNOOP_NEEDED", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x100100120", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_MISS", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_MISS", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x200100120", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_NONE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_NONE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x80100120", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_READS.L3_HIT.ANY_SNOOP OCR.ALL_READS.L3_HIT.ANY_SNOOP OCR.ALL_READS.L3_HIT.ANY_SNOOP", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_READS.L3_HIT.ANY_SNOOP", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x3F803C07F7", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x10003C07F7", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x8003C07F7", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x4003C07F7", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x1003C07F7", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_READS.L3_HIT.SNOOP_HIT_WITH_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_READS.L3_HIT.SNOOP_HIT_WITH_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x8007C07F7", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_READS.L3_HIT.SNOOP_MISS OCR.ALL_READS.L3_HIT.SNOOP_MISS", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_READS.L3_HIT.SNOOP_MISS", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x2003C07F7", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_READS.L3_HIT.SNOOP_NONE OCR.ALL_READS.L3_HIT.SNOOP_NONE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_READS.L3_HIT.SNOOP_NONE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x803C07F7", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_READS.L3_HIT_E.ANY_SNOOP OCR.ALL_READS.L3_HIT_E.ANY_SNOOP", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_READS.L3_HIT_E.ANY_SNOOP", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x3F800807F7", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_READS.L3_HIT_E.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT_E.HITM_OTHER_CORE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_READS.L3_HIT_E.HITM_OTHER_CORE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x10000807F7", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x8000807F7", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x4000807F7", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_READS.L3_HIT_E.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT_E.NO_SNOOP_NEEDED", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_READS.L3_HIT_E.NO_SNOOP_NEEDED", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x1000807F7", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_READS.L3_HIT_E.SNOOP_MISS", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_READS.L3_HIT_E.SNOOP_MISS", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x2000807F7", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_READS.L3_HIT_E.SNOOP_NONE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_READS.L3_HIT_E.SNOOP_NONE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x800807F7", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_READS.L3_HIT_F.ANY_SNOOP OCR.ALL_READS.L3_HIT_F.ANY_SNOOP", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_READS.L3_HIT_F.ANY_SNOOP", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x3F802007F7", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_READS.L3_HIT_F.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT_F.HITM_OTHER_CORE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_READS.L3_HIT_F.HITM_OTHER_CORE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x10002007F7", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x8002007F7", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x4002007F7", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_READS.L3_HIT_F.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT_F.NO_SNOOP_NEEDED", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_READS.L3_HIT_F.NO_SNOOP_NEEDED", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x1002007F7", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_READS.L3_HIT_F.SNOOP_MISS", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_READS.L3_HIT_F.SNOOP_MISS", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x2002007F7", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_READS.L3_HIT_F.SNOOP_NONE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_READS.L3_HIT_F.SNOOP_NONE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x802007F7", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_READS.L3_HIT_M.ANY_SNOOP OCR.ALL_READS.L3_HIT_M.ANY_SNOOP", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_READS.L3_HIT_M.ANY_SNOOP", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x3F800407F7", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_READS.L3_HIT_M.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT_M.HITM_OTHER_CORE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_READS.L3_HIT_M.HITM_OTHER_CORE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x10000407F7", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x8000407F7", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x4000407F7", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_READS.L3_HIT_M.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT_M.NO_SNOOP_NEEDED", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_READS.L3_HIT_M.NO_SNOOP_NEEDED", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x1000407F7", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_READS.L3_HIT_M.SNOOP_MISS", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_READS.L3_HIT_M.SNOOP_MISS", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x2000407F7", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_READS.L3_HIT_M.SNOOP_NONE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_READS.L3_HIT_M.SNOOP_NONE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x800407F7", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_READS.L3_HIT_S.ANY_SNOOP OCR.ALL_READS.L3_HIT_S.ANY_SNOOP", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_READS.L3_HIT_S.ANY_SNOOP", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x3F801007F7", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_READS.L3_HIT_S.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT_S.HITM_OTHER_CORE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_READS.L3_HIT_S.HITM_OTHER_CORE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x10001007F7", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x8001007F7", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x4001007F7", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_READS.L3_HIT_S.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT_S.NO_SNOOP_NEEDED", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_READS.L3_HIT_S.NO_SNOOP_NEEDED", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x1001007F7", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_READS.L3_HIT_S.SNOOP_MISS", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_READS.L3_HIT_S.SNOOP_MISS", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x2001007F7", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_READS.L3_HIT_S.SNOOP_NONE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_READS.L3_HIT_S.SNOOP_NONE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x801007F7", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_RFO.L3_HIT.ANY_SNOOP OCR.ALL_RFO.L3_HIT.ANY_SNOOP OCR.ALL_RFO.L3_HIT.ANY_SNOOP", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_RFO.L3_HIT.ANY_SNOOP", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x3F803C0122", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x10003C0122", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x8003C0122", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x4003C0122", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x1003C0122", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x8007C0122", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_RFO.L3_HIT.SNOOP_MISS OCR.ALL_RFO.L3_HIT.SNOOP_MISS", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_RFO.L3_HIT.SNOOP_MISS", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x2003C0122", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_RFO.L3_HIT.SNOOP_NONE OCR.ALL_RFO.L3_HIT.SNOOP_NONE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_RFO.L3_HIT.SNOOP_NONE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x803C0122", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.ANY_SNOOP OCR.ALL_RFO.L3_HIT_E.ANY_SNOOP", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_RFO.L3_HIT_E.ANY_SNOOP", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x3F80080122", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT_E.HITM_OTHER_CORE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_RFO.L3_HIT_E.HITM_OTHER_CORE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x1000080122", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x800080122", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x400080122", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT_E.NO_SNOOP_NEEDED", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_RFO.L3_HIT_E.NO_SNOOP_NEEDED", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x100080122", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.SNOOP_MISS", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_RFO.L3_HIT_E.SNOOP_MISS", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x200080122", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.SNOOP_NONE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_RFO.L3_HIT_E.SNOOP_NONE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x80080122", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.ANY_SNOOP OCR.ALL_RFO.L3_HIT_F.ANY_SNOOP", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_RFO.L3_HIT_F.ANY_SNOOP", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x3F80200122", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT_F.HITM_OTHER_CORE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_RFO.L3_HIT_F.HITM_OTHER_CORE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x1000200122", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x800200122", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x400200122", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT_F.NO_SNOOP_NEEDED", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_RFO.L3_HIT_F.NO_SNOOP_NEEDED", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x100200122", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.SNOOP_MISS", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_RFO.L3_HIT_F.SNOOP_MISS", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x200200122", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.SNOOP_NONE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_RFO.L3_HIT_F.SNOOP_NONE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x80200122", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.ANY_SNOOP OCR.ALL_RFO.L3_HIT_M.ANY_SNOOP", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_RFO.L3_HIT_M.ANY_SNOOP", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x3F80040122", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT_M.HITM_OTHER_CORE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_RFO.L3_HIT_M.HITM_OTHER_CORE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x1000040122", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x800040122", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x400040122", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT_M.NO_SNOOP_NEEDED", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_RFO.L3_HIT_M.NO_SNOOP_NEEDED", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x100040122", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.SNOOP_MISS", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_RFO.L3_HIT_M.SNOOP_MISS", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x200040122", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.SNOOP_NONE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_RFO.L3_HIT_M.SNOOP_NONE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x80040122", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.ANY_SNOOP OCR.ALL_RFO.L3_HIT_S.ANY_SNOOP", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_RFO.L3_HIT_S.ANY_SNOOP", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x3F80100122", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT_S.HITM_OTHER_CORE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_RFO.L3_HIT_S.HITM_OTHER_CORE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x1000100122", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x800100122", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x400100122", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT_S.NO_SNOOP_NEEDED", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_RFO.L3_HIT_S.NO_SNOOP_NEEDED", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x100100122", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.SNOOP_MISS", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_RFO.L3_HIT_S.SNOOP_MISS", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x200100122", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.SNOOP_NONE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.ALL_RFO.L3_HIT_S.SNOOP_NONE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x80100122", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP OCR.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x3F803C0004", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE OCR.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x10003C0004", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x8003C0004", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x4003C0004", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDED OCR.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDED", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDED", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x1003C0004", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all demand code reads", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x8007C0004", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x2003C0004", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NONE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NONE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x803C0004", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_E.ANY_SNOOP", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.ANY_SNOOP", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x3F80080004", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_E.HITM_OTHER_CORE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.HITM_OTHER_CORE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x1000080004", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x800080004", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x400080004", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_E.NO_SNOOP_NEEDED", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.NO_SNOOP_NEEDED", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x100080004", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all demand code reads", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.SNOOP_MISS", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x200080004", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all demand code reads", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NONE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x80080004", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_F.ANY_SNOOP", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.ANY_SNOOP", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x3F80200004", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_F.HITM_OTHER_CORE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.HITM_OTHER_CORE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x1000200004", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x800200004", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x400200004", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_F.NO_SNOOP_NEEDED", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.NO_SNOOP_NEEDED", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x100200004", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all demand code reads", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.SNOOP_MISS", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x200200004", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all demand code reads", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.SNOOP_NONE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x80200004", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_M.ANY_SNOOP", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.ANY_SNOOP", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x3F80040004", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_M.HITM_OTHER_CORE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.HITM_OTHER_CORE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x1000040004", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x800040004", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x400040004", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_M.NO_SNOOP_NEEDED", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.NO_SNOOP_NEEDED", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x100040004", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all demand code reads", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.SNOOP_MISS", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x200040004", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all demand code reads", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NONE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x80040004", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_S.ANY_SNOOP", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.ANY_SNOOP", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x3F80100004", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_S.HITM_OTHER_CORE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.HITM_OTHER_CORE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x1000100004", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x800100004", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x400100004", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_S.NO_SNOOP_NEEDED", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.NO_SNOOP_NEEDED", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x100100004", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all demand code reads", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.SNOOP_MISS", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x200100004", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all demand code reads", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NONE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x80100004", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP OCR.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x3F803C0001", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x10003C0001", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x8003C0001", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x4003C0001", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x1003C0001", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts demand data reads", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x8007C0001", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x2003C0001", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NONE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NONE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x803C0001", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_E.ANY_SNOOP", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.ANY_SNOOP", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x3F80080001", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x1000080001", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x800080001", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x400080001", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x100080001", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts demand data reads", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.SNOOP_MISS", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x200080001", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts demand data reads", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NONE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x80080001", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_F.ANY_SNOOP", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.ANY_SNOOP", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x3F80200001", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x1000200001", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x800200001", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x400200001", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x100200001", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts demand data reads", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.SNOOP_MISS", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x200200001", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts demand data reads", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.SNOOP_NONE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x80200001", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_M.ANY_SNOOP", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.ANY_SNOOP", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x3F80040001", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x1000040001", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x800040001", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x400040001", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x100040001", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts demand data reads", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.SNOOP_MISS", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x200040001", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts demand data reads", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.SNOOP_NONE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x80040001", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_S.ANY_SNOOP", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.ANY_SNOOP", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x3F80100001", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x1000100001", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x800100001", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x400100001", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x100100001", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts demand data reads", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.SNOOP_MISS", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x200100001", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts demand data reads", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.SNOOP_NONE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x80100001", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.ANY_SNOOP OCR.DEMAND_RFO.L3_HIT.ANY_SNOOP", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_RFO.L3_HIT.ANY_SNOOP", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x3F803C0002", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x10003C0002", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x8003C0002", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x4003C0002", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x1003C0002", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all demand data writes (RFOs)", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x8007C0002", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x2003C0002", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.SNOOP_NONE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_NONE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x803C0002", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_E.ANY_SNOOP", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_RFO.L3_HIT_E.ANY_SNOOP", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x3F80080002", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_E.HITM_OTHER_CORE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_RFO.L3_HIT_E.HITM_OTHER_CORE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x1000080002", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x800080002", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x400080002", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_E.NO_SNOOP_NEEDED", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_RFO.L3_HIT_E.NO_SNOOP_NEEDED", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x100080002", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all demand data writes (RFOs)", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_RFO.L3_HIT_E.SNOOP_MISS", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x200080002", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all demand data writes (RFOs)", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_RFO.L3_HIT_E.SNOOP_NONE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x80080002", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_F.ANY_SNOOP", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_RFO.L3_HIT_F.ANY_SNOOP", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x3F80200002", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_F.HITM_OTHER_CORE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_RFO.L3_HIT_F.HITM_OTHER_CORE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x1000200002", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x800200002", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x400200002", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_F.NO_SNOOP_NEEDED", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_RFO.L3_HIT_F.NO_SNOOP_NEEDED", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x100200002", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all demand data writes (RFOs)", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_RFO.L3_HIT_F.SNOOP_MISS", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x200200002", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all demand data writes (RFOs)", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_RFO.L3_HIT_F.SNOOP_NONE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x80200002", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_M.ANY_SNOOP", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_RFO.L3_HIT_M.ANY_SNOOP", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x3F80040002", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_M.HITM_OTHER_CORE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_RFO.L3_HIT_M.HITM_OTHER_CORE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x1000040002", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x800040002", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x400040002", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_M.NO_SNOOP_NEEDED", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_RFO.L3_HIT_M.NO_SNOOP_NEEDED", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x100040002", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all demand data writes (RFOs)", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_RFO.L3_HIT_M.SNOOP_MISS", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x200040002", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all demand data writes (RFOs)", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_RFO.L3_HIT_M.SNOOP_NONE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x80040002", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_S.ANY_SNOOP", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_RFO.L3_HIT_S.ANY_SNOOP", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x3F80100002", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_S.HITM_OTHER_CORE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_RFO.L3_HIT_S.HITM_OTHER_CORE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x1000100002", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x800100002", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x400100002", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_S.NO_SNOOP_NEEDED", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_RFO.L3_HIT_S.NO_SNOOP_NEEDED", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x100100002", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all demand data writes (RFOs)", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_RFO.L3_HIT_S.SNOOP_MISS", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x200100002", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all demand data writes (RFOs)", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.DEMAND_RFO.L3_HIT_S.SNOOP_NONE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x80100002", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.ANY_SNOOP OCR.OTHER.L3_HIT.ANY_SNOOP", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.OTHER.L3_HIT.ANY_SNOOP", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x3F803C8000", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.HITM_OTHER_CORE OCR.OTHER.L3_HIT.HITM_OTHER_CORE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.OTHER.L3_HIT.HITM_OTHER_CORE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x10003C8000", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.HIT_OTHER_CORE_FWD OCR.OTHER.L3_HIT.HIT_OTHER_CORE_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.OTHER.L3_HIT.HIT_OTHER_CORE_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x8003C8000", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.OTHER.L3_HIT.HIT_OTHER_CORE_NO_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.OTHER.L3_HIT.HIT_OTHER_CORE_NO_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x4003C8000", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.NO_SNOOP_NEEDED OCR.OTHER.L3_HIT.NO_SNOOP_NEEDED", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.OTHER.L3_HIT.NO_SNOOP_NEEDED", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x1003C8000", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts any other requests", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.OTHER.L3_HIT.SNOOP_HIT_WITH_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x8007C8000", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.SNOOP_MISS", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.OTHER.L3_HIT.SNOOP_MISS", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x2003C8000", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.SNOOP_NONE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.OTHER.L3_HIT.SNOOP_NONE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x803C8000", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_E.ANY_SNOOP", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.OTHER.L3_HIT_E.ANY_SNOOP", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x3F80088000", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_E.HITM_OTHER_CORE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.OTHER.L3_HIT_E.HITM_OTHER_CORE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x1000088000", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x800088000", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x400088000", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_E.NO_SNOOP_NEEDED", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.OTHER.L3_HIT_E.NO_SNOOP_NEEDED", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x100088000", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts any other requests", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.OTHER.L3_HIT_E.SNOOP_MISS", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x200088000", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts any other requests", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.OTHER.L3_HIT_E.SNOOP_NONE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x80088000", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_F.ANY_SNOOP", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.OTHER.L3_HIT_F.ANY_SNOOP", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x3F80208000", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_F.HITM_OTHER_CORE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.OTHER.L3_HIT_F.HITM_OTHER_CORE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x1000208000", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x800208000", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x400208000", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_F.NO_SNOOP_NEEDED", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.OTHER.L3_HIT_F.NO_SNOOP_NEEDED", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x100208000", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts any other requests", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.OTHER.L3_HIT_F.SNOOP_MISS", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x200208000", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts any other requests", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.OTHER.L3_HIT_F.SNOOP_NONE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x80208000", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_M.ANY_SNOOP", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.OTHER.L3_HIT_M.ANY_SNOOP", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x3F80048000", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_M.HITM_OTHER_CORE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.OTHER.L3_HIT_M.HITM_OTHER_CORE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x1000048000", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x800048000", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x400048000", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_M.NO_SNOOP_NEEDED", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.OTHER.L3_HIT_M.NO_SNOOP_NEEDED", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x100048000", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts any other requests", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.OTHER.L3_HIT_M.SNOOP_MISS", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x200048000", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts any other requests", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.OTHER.L3_HIT_M.SNOOP_NONE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x80048000", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_S.ANY_SNOOP", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.OTHER.L3_HIT_S.ANY_SNOOP", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x3F80108000", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_S.HITM_OTHER_CORE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.OTHER.L3_HIT_S.HITM_OTHER_CORE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x1000108000", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x800108000", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x400108000", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_S.NO_SNOOP_NEEDED", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.OTHER.L3_HIT_S.NO_SNOOP_NEEDED", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x100108000", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts any other requests", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.OTHER.L3_HIT_S.SNOOP_MISS", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x200108000", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts any other requests", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.OTHER.L3_HIT_S.SNOOP_NONE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x80108000", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.ANY_SNOOP OCR.PF_L1D_AND_SW.L3_HIT.ANY_SNOOP", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.ANY_SNOOP", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x3F803C0400", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.HITM_OTHER_CORE OCR.PF_L1D_AND_SW.L3_HIT.HITM_OTHER_CORE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.HITM_OTHER_CORE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x10003C0400", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x8003C0400", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_NO_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_NO_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x4003C0400", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDED", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDED", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x1003C0400", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_HIT_WITH_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x8007C0400", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_MISS", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_MISS", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x2003C0400", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_NONE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_NONE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x803C0400", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_E.ANY_SNOOP", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.ANY_SNOOP", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x3F80080400", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_E.HITM_OTHER_CORE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.HITM_OTHER_CORE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x1000080400", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x800080400", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x400080400", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_E.NO_SNOOP_NEEDED", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.NO_SNOOP_NEEDED", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x100080400", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.SNOOP_MISS", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x200080400", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.SNOOP_NONE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x80080400", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_F.ANY_SNOOP", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.ANY_SNOOP", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x3F80200400", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_F.HITM_OTHER_CORE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.HITM_OTHER_CORE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x1000200400", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x800200400", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x400200400", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_F.NO_SNOOP_NEEDED", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.NO_SNOOP_NEEDED", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x100200400", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.SNOOP_MISS", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x200200400", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.SNOOP_NONE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x80200400", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_M.ANY_SNOOP", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.ANY_SNOOP", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x3F80040400", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_M.HITM_OTHER_CORE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.HITM_OTHER_CORE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x1000040400", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x800040400", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x400040400", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_M.NO_SNOOP_NEEDED", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.NO_SNOOP_NEEDED", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x100040400", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.SNOOP_MISS", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x200040400", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.SNOOP_NONE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x80040400", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_S.ANY_SNOOP", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.ANY_SNOOP", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x3F80100400", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_S.HITM_OTHER_CORE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.HITM_OTHER_CORE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x1000100400", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x800100400", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x400100400", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_S.NO_SNOOP_NEEDED", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.NO_SNOOP_NEEDED", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x100100400", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.SNOOP_MISS", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x200100400", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.SNOOP_NONE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x80100400", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP OCR.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x3F803C0010", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.PF_L2_DATA_RD.L3_HIT.HITM_OTHER_CORE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.HITM_OTHER_CORE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x10003C0010", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x8003C0010", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x4003C0010", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x1003C0010", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x8007C0010", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_MISS", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_MISS", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x2003C0010", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_NONE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_NONE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x803C0010", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_E.ANY_SNOOP", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.ANY_SNOOP", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x3F80080010", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x1000080010", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x800080010", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x400080010", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x100080010", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.SNOOP_MISS", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x200080010", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.SNOOP_NONE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x80080010", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_F.ANY_SNOOP", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.ANY_SNOOP", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x3F80200010", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x1000200010", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x800200010", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x400200010", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x100200010", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.SNOOP_MISS", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x200200010", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.SNOOP_NONE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x80200010", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_M.ANY_SNOOP", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.ANY_SNOOP", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x3F80040010", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x1000040010", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x800040010", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x400040010", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x100040010", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.SNOOP_MISS", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x200040010", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.SNOOP_NONE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x80040010", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_S.ANY_SNOOP", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.ANY_SNOOP", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x3F80100010", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x1000100010", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x800100010", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x400100010", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x100100010", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.SNOOP_MISS", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x200100010", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.SNOOP_NONE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x80100010", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.ANY_SNOOP OCR.PF_L2_RFO.L3_HIT.ANY_SNOOP", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L2_RFO.L3_HIT.ANY_SNOOP", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x3F803C0020", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x10003C0020", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x8003C0020", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x4003C0020", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x1003C0020", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L2_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x8007C0020", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.SNOOP_MISS", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L2_RFO.L3_HIT.SNOOP_MISS", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x2003C0020", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.SNOOP_NONE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L2_RFO.L3_HIT.SNOOP_NONE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x803C0020", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_E.ANY_SNOOP", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L2_RFO.L3_HIT_E.ANY_SNOOP", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x3F80080020", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_E.HITM_OTHER_CORE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L2_RFO.L3_HIT_E.HITM_OTHER_CORE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x1000080020", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x800080020", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x400080020", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_E.NO_SNOOP_NEEDED", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L2_RFO.L3_HIT_E.NO_SNOOP_NEEDED", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x100080020", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L2_RFO.L3_HIT_E.SNOOP_MISS", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x200080020", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L2_RFO.L3_HIT_E.SNOOP_NONE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x80080020", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_F.ANY_SNOOP", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L2_RFO.L3_HIT_F.ANY_SNOOP", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x3F80200020", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_F.HITM_OTHER_CORE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L2_RFO.L3_HIT_F.HITM_OTHER_CORE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x1000200020", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x800200020", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x400200020", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_F.NO_SNOOP_NEEDED", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L2_RFO.L3_HIT_F.NO_SNOOP_NEEDED", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x100200020", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L2_RFO.L3_HIT_F.SNOOP_MISS", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x200200020", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L2_RFO.L3_HIT_F.SNOOP_NONE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x80200020", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_M.ANY_SNOOP", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L2_RFO.L3_HIT_M.ANY_SNOOP", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x3F80040020", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_M.HITM_OTHER_CORE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L2_RFO.L3_HIT_M.HITM_OTHER_CORE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x1000040020", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x800040020", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x400040020", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_M.NO_SNOOP_NEEDED", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L2_RFO.L3_HIT_M.NO_SNOOP_NEEDED", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x100040020", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L2_RFO.L3_HIT_M.SNOOP_MISS", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x200040020", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L2_RFO.L3_HIT_M.SNOOP_NONE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x80040020", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_S.ANY_SNOOP", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L2_RFO.L3_HIT_S.ANY_SNOOP", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x3F80100020", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_S.HITM_OTHER_CORE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L2_RFO.L3_HIT_S.HITM_OTHER_CORE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x1000100020", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x800100020", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x400100020", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_S.NO_SNOOP_NEEDED", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L2_RFO.L3_HIT_S.NO_SNOOP_NEEDED", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x100100020", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L2_RFO.L3_HIT_S.SNOOP_MISS", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x200100020", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L2_RFO.L3_HIT_S.SNOOP_NONE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x80100020", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP OCR.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x3F803C0080", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.PF_L3_DATA_RD.L3_HIT.HITM_OTHER_CORE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.HITM_OTHER_CORE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x10003C0080", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x8003C0080", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x4003C0080", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x1003C0080", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x8007C0080", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_MISS", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_MISS", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x2003C0080", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_NONE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_NONE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x803C0080", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_E.ANY_SNOOP", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.ANY_SNOOP", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x3F80080080", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x1000080080", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x800080080", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x400080080", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x100080080", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.SNOOP_MISS", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x200080080", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.SNOOP_NONE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x80080080", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_F.ANY_SNOOP", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.ANY_SNOOP", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x3F80200080", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x1000200080", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x800200080", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x400200080", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x100200080", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.SNOOP_MISS", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x200200080", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.SNOOP_NONE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x80200080", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_M.ANY_SNOOP", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.ANY_SNOOP", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x3F80040080", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x1000040080", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x800040080", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x400040080", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x100040080", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.SNOOP_MISS", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x200040080", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.SNOOP_NONE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x80040080", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_S.ANY_SNOOP", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.ANY_SNOOP", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x3F80100080", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x1000100080", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x800100080", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x400100080", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x100100080", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.SNOOP_MISS", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x200100080", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.SNOOP_NONE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x80100080", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.ANY_SNOOP OCR.PF_L3_RFO.L3_HIT.ANY_SNOOP", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L3_RFO.L3_HIT.ANY_SNOOP", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x3F803C0100", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.HITM_OTHER_CORE OCR.PF_L3_RFO.L3_HIT.HITM_OTHER_CORE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L3_RFO.L3_HIT.HITM_OTHER_CORE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x10003C0100", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x8003C0100", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x4003C0100", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x1003C0100", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L3_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x8007C0100", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.SNOOP_MISS", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L3_RFO.L3_HIT.SNOOP_MISS", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x2003C0100", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.SNOOP_NONE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L3_RFO.L3_HIT.SNOOP_NONE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x803C0100", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_E.ANY_SNOOP", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L3_RFO.L3_HIT_E.ANY_SNOOP", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x3F80080100", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_E.HITM_OTHER_CORE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L3_RFO.L3_HIT_E.HITM_OTHER_CORE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x1000080100", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x800080100", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x400080100", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_E.NO_SNOOP_NEEDED", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L3_RFO.L3_HIT_E.NO_SNOOP_NEEDED", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x100080100", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L3_RFO.L3_HIT_E.SNOOP_MISS", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x200080100", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L3_RFO.L3_HIT_E.SNOOP_NONE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x80080100", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_F.ANY_SNOOP", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L3_RFO.L3_HIT_F.ANY_SNOOP", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x3F80200100", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_F.HITM_OTHER_CORE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L3_RFO.L3_HIT_F.HITM_OTHER_CORE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x1000200100", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x800200100", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x400200100", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_F.NO_SNOOP_NEEDED", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L3_RFO.L3_HIT_F.NO_SNOOP_NEEDED", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x100200100", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L3_RFO.L3_HIT_F.SNOOP_MISS", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x200200100", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L3_RFO.L3_HIT_F.SNOOP_NONE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x80200100", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_M.ANY_SNOOP", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L3_RFO.L3_HIT_M.ANY_SNOOP", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x3F80040100", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_M.HITM_OTHER_CORE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L3_RFO.L3_HIT_M.HITM_OTHER_CORE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x1000040100", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x800040100", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x400040100", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_M.NO_SNOOP_NEEDED", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L3_RFO.L3_HIT_M.NO_SNOOP_NEEDED", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x100040100", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L3_RFO.L3_HIT_M.SNOOP_MISS", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x200040100", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L3_RFO.L3_HIT_M.SNOOP_NONE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x80040100", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_S.ANY_SNOOP", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L3_RFO.L3_HIT_S.ANY_SNOOP", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x3F80100100", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_S.HITM_OTHER_CORE", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L3_RFO.L3_HIT_S.HITM_OTHER_CORE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x1000100100", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x800100100", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x400100100", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_S.NO_SNOOP_NEEDED", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L3_RFO.L3_HIT_S.NO_SNOOP_NEEDED", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x100100100", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L3_RFO.L3_HIT_S.SNOOP_MISS", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x200100100", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3", > > + "EventCode": "0xB7, 0xBB", > > + "EventName": "OCR.PF_L3_RFO.L3_HIT_S.SNOOP_NONE", > > + "MSRIndex": "0x1a6,0x1a7", > > + "MSRValue": "0x80100100", > > + "Offcore": "1", > > + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > + "SampleAfterValue": "100003", > > + "UMask": "0x1" > > + }, > > { > > "BriefDescription": "Demand and prefetch data reads", > > "Counter": "0,1,2,3", > > @@ -9987,5 +16539,41 @@ > > "PublicDescription": "Counts the number of cache line split locks sent to the uncore.", > > "SampleAfterValue": "100003", > > "UMask": "0x10" > > + }, > > + { > > + "BriefDescription": "Number of PREFETCHNTA instructions executed.", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3,4,5,6,7", > > + "EventCode": "0x32", > > + "EventName": "SW_PREFETCH_ACCESS.NTA", > > + "SampleAfterValue": "2000003", > > + "UMask": "0x1" > > + }, > > + { > > + "BriefDescription": "Number of PREFETCHW instructions executed.", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3,4,5,6,7", > > + "EventCode": "0x32", > > + "EventName": "SW_PREFETCH_ACCESS.PREFETCHW", > > + "SampleAfterValue": "2000003", > > + "UMask": "0x8" > > + }, > > + { > > + "BriefDescription": "Number of PREFETCHT0 instructions executed.", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3,4,5,6,7", > > + "EventCode": "0x32", > > + "EventName": "SW_PREFETCH_ACCESS.T0", > > + "SampleAfterValue": "2000003", > > + "UMask": "0x2" > > + }, > > + { > > + "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.", > > + "Counter": "0,1,2,3", > > + "CounterHTOff": "0,1,2,3,4,5,6,7", > > + "EventCode": "0x32", > > + "EventName": "SW_PREFETCH_ACCESS.T1_T2", > > + "SampleAfterValue": "2000003", > > + "UMask": "0x4" > > } > > ] > > \ No newline at end of file > > diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/other.json b/tools/perf/pmu-events/arch/x86/cascadelakex/other.json > > index d8b145a7d303..bb23a91b0127 100644 > > --- a/tools/perf/pmu-events/arch/x86/cascadelakex/other.json > > +++ b/tools/perf/pmu-events/arch/x86/cascadelakex/other.json > > @@ -83,8411 +83,1859 @@ > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP", > > + "BriefDescription": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP", > > + "EventName": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F803C0491", > > + "MSRValue": "0x3F80400491", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE", > > + "BriefDescription": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE", > > + "EventName": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x10003C0491", > > + "MSRValue": "0x80400491", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", > > + "BriefDescription": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", > > + "EventName": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x8003C0491", > > + "MSRValue": "0x100400491", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", > > + "BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.ANY_SNOOP OCR.ALL_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", > > + "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x4003C0491", > > + "MSRValue": "0x3F80020491", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", > > + "BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE OCR.ALL_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", > > + "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x1003C0491", > > + "MSRValue": "0x1000020491", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", > > + "BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", > > + "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x8007C0491", > > + "MSRValue": "0x800020491", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_MISS OCR.ALL_DATA_RD.L3_HIT.SNOOP_MISS", > > + "BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_MISS", > > + "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x2003C0491", > > + "MSRValue": "0x400020491", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_NONE OCR.ALL_DATA_RD.L3_HIT.SNOOP_NONE", > > + "BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_NONE", > > + "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x803C0491", > > + "MSRValue": "0x100020491", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT_E.ANY_SNOOP", > > + "BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.ANY_SNOOP", > > + "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F80080491", > > + "MSRValue": "0x200020491", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", > > + "BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", > > + "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x1000080491", > > + "MSRValue": "0x80020491", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", > > + "BriefDescription": "OCR.ALL_PF_DATA_RD.ANY_RESPONSE have any response type.", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", > > + "EventName": "OCR.ALL_PF_DATA_RD.ANY_RESPONSE", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x800080491", > > + "MSRValue": "0x10490", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > > + "BriefDescription": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > > + "EventName": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x400080491", > > + "MSRValue": "0x3F80400490", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", > > + "BriefDescription": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", > > + "EventName": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x100080491", > > + "MSRValue": "0x80400490", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_MISS", > > + "BriefDescription": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_MISS", > > + "EventName": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x200080491", > > + "MSRValue": "0x100400490", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_NONE", > > + "BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.ANY_SNOOP OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_NONE", > > + "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x80080491", > > + "MSRValue": "0x3F80020490", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT_F.ANY_SNOOP", > > + "BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.ANY_SNOOP", > > + "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F80200491", > > + "MSRValue": "0x1000020490", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", > > + "BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", > > + "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x1000200491", > > + "MSRValue": "0x800020490", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", > > + "BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", > > + "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x800200491", > > + "MSRValue": "0x400020490", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > > + "BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > > + "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x400200491", > > + "MSRValue": "0x100020490", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", > > + "BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", > > + "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x100200491", > > + "MSRValue": "0x200020490", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_MISS", > > + "BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_MISS", > > + "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x200200491", > > + "MSRValue": "0x80020490", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_NONE", > > + "BriefDescription": "OCR.ALL_PF_RFO.ANY_RESPONSE have any response type.", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_NONE", > > + "EventName": "OCR.ALL_PF_RFO.ANY_RESPONSE", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x80200491", > > + "MSRValue": "0x10120", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT_M.ANY_SNOOP", > > + "BriefDescription": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.ANY_SNOOP", > > + "EventName": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F80040491", > > + "MSRValue": "0x3F80400120", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", > > + "BriefDescription": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", > > + "EventName": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x1000040491", > > + "MSRValue": "0x80400120", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", > > + "BriefDescription": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", > > + "EventName": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x800040491", > > + "MSRValue": "0x100400120", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > > + "BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.ANY_SNOOP OCR.ALL_PF_RFO.SUPPLIER_NONE.ANY_SNOOP", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > > + "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.ANY_SNOOP", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x400040491", > > + "MSRValue": "0x3F80020120", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", > > + "BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HITM_OTHER_CORE OCR.ALL_PF_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", > > + "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x100040491", > > + "MSRValue": "0x1000020120", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_MISS", > > + "BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_MISS", > > + "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x200040491", > > + "MSRValue": "0x800020120", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_NONE", > > + "BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_NONE", > > + "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x80040491", > > + "MSRValue": "0x400020120", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT_S.ANY_SNOOP", > > + "BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.ANY_SNOOP", > > + "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F80100491", > > + "MSRValue": "0x100020120", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", > > + "BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_MISS", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", > > + "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_MISS", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x1000100491", > > + "MSRValue": "0x200020120", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", > > + "BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NONE", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", > > + "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NONE", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x800100491", > > + "MSRValue": "0x80020120", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > > + "BriefDescription": "OCR.ALL_READS.ANY_RESPONSE have any response type.", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > > + "EventName": "OCR.ALL_READS.ANY_RESPONSE", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x400100491", > > + "MSRValue": "0x107F7", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", > > + "BriefDescription": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_READS.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", > > + "EventName": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x100100491", > > + "MSRValue": "0x3F804007F7", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_MISS", > > + "BriefDescription": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_MISS", > > + "EventName": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x200100491", > > + "MSRValue": "0x804007F7", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_NONE", > > + "BriefDescription": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_NONE", > > + "EventName": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x80100491", > > + "MSRValue": "0x1004007F7", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > > + "BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.ANY_SNOOP OCR.ALL_READS.SUPPLIER_NONE.ANY_SNOOP", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > > + "EventName": "OCR.ALL_READS.SUPPLIER_NONE.ANY_SNOOP", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F80400491", > > + "MSRValue": "0x3F800207F7", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > > + "BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.HITM_OTHER_CORE OCR.ALL_READS.SUPPLIER_NONE.HITM_OTHER_CORE", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > > + "EventName": "OCR.ALL_READS.SUPPLIER_NONE.HITM_OTHER_CORE", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x80400491", > > + "MSRValue": "0x10000207F7", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > > + "BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_FWD OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > > + "EventName": "OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x100400491", > > + "MSRValue": "0x8000207F7", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.ANY_SNOOP OCR.ALL_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", > > + "BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", > > + "EventName": "OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F80020491", > > + "MSRValue": "0x4000207F7", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE OCR.ALL_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", > > + "BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.NO_SNOOP_NEEDED OCR.ALL_READS.SUPPLIER_NONE.NO_SNOOP_NEEDED", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", > > + "EventName": "OCR.ALL_READS.SUPPLIER_NONE.NO_SNOOP_NEEDED", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x1000020491", > > + "MSRValue": "0x1000207F7", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > > + "BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.SNOOP_MISS", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > > + "EventName": "OCR.ALL_READS.SUPPLIER_NONE.SNOOP_MISS", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x800020491", > > + "MSRValue": "0x2000207F7", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > > + "BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.SNOOP_NONE", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > > + "EventName": "OCR.ALL_READS.SUPPLIER_NONE.SNOOP_NONE", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x400020491", > > + "MSRValue": "0x800207F7", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", > > + "BriefDescription": "OCR.ALL_RFO.ANY_RESPONSE have any response type.", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", > > + "EventName": "OCR.ALL_RFO.ANY_RESPONSE", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x100020491", > > + "MSRValue": "0x10122", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", > > + "BriefDescription": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", > > + "EventName": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x200020491", > > + "MSRValue": "0x3F80400122", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", > > + "BriefDescription": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", > > + "EventName": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x80020491", > > + "MSRValue": "0x80400122", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "OCR.ALL_PF_DATA_RD.ANY_RESPONSE have any response type.", > > + "BriefDescription": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_DATA_RD.ANY_RESPONSE", > > + "EventName": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x10490", > > + "MSRValue": "0x100400122", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP", > > + "BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.ANY_SNOOP OCR.ALL_RFO.SUPPLIER_NONE.ANY_SNOOP", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP", > > + "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.ANY_SNOOP", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F803C0490", > > + "MSRValue": "0x3F80020122", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE", > > + "BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.HITM_OTHER_CORE OCR.ALL_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE", > > + "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x10003C0490", > > + "MSRValue": "0x1000020122", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", > > + "BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", > > + "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x8003C0490", > > + "MSRValue": "0x800020122", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", > > + "BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", > > + "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x4003C0490", > > + "MSRValue": "0x400020122", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", > > + "BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED OCR.ALL_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", > > + "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x1003C0490", > > + "MSRValue": "0x100020122", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", > > + "BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_MISS", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", > > + "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_MISS", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x8007C0490", > > + "MSRValue": "0x200020122", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS", > > + "BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_NONE", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS", > > + "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_NONE", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x2003C0490", > > + "MSRValue": "0x80020122", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE", > > + "BriefDescription": "Counts all demand code reads have any response type.", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE", > > + "EventName": "OCR.DEMAND_CODE_RD.ANY_RESPONSE", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x803C0490", > > + "MSRValue": "0x10004", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT_E.ANY_SNOOP", > > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.ANY_SNOOP", > > + "EventName": "OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F80080490", > > + "MSRValue": "0x3F80400004", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", > > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", > > + "EventName": "OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x1000080490", > > + "MSRValue": "0x80400004", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", > > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", > > + "EventName": "OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x800080490", > > + "MSRValue": "0x100400004", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.SUPPLIER_NONE.ANY_SNOOP", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > > + "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.ANY_SNOOP", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x400080490", > > + "MSRValue": "0x3F80020004", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", > > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HITM_OTHER_CORE", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", > > + "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HITM_OTHER_CORE", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x100080490", > > + "MSRValue": "0x1000020004", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_MISS", > > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_MISS", > > + "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x200080490", > > + "MSRValue": "0x800020004", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_NONE", > > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_NONE", > > + "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x80080490", > > + "MSRValue": "0x400020004", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT_F.ANY_SNOOP", > > + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.ANY_SNOOP", > > + "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F80200490", > > + "MSRValue": "0x100020004", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", > > + "BriefDescription": "Counts all demand code reads", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", > > + "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_MISS", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x1000200490", > > + "MSRValue": "0x200020004", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", > > + "BriefDescription": "Counts all demand code reads", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", > > + "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NONE", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x800200490", > > + "MSRValue": "0x80020004", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > > + "BriefDescription": "Counts demand data reads have any response type.", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > > + "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x400200490", > > + "MSRValue": "0x10001", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", > > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", > > + "EventName": "OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x100200490", > > + "MSRValue": "0x3F80400001", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_MISS", > > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_MISS", > > + "EventName": "OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x200200490", > > + "MSRValue": "0x80400001", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_NONE", > > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_NONE", > > + "EventName": "OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x80200490", > > + "MSRValue": "0x100400001", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT_M.ANY_SNOOP", > > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.ANY_SNOOP", > > + "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F80040490", > > + "MSRValue": "0x3F80020001", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", > > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", > > + "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x1000040490", > > + "MSRValue": "0x1000020001", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", > > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", > > + "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x800040490", > > + "MSRValue": "0x800020001", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > > + "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x400040490", > > + "MSRValue": "0x400020001", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", > > + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", > > + "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x100040490", > > + "MSRValue": "0x100020001", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_MISS", > > + "BriefDescription": "Counts demand data reads", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_MISS", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x200040490", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_NONE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_NONE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x80040490", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT_S.ANY_SNOOP", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.ANY_SNOOP", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F80100490", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x1000100490", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x800100490", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x400100490", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x100100490", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_MISS", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_MISS", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x200100490", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_NONE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_NONE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x80100490", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F80400490", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x80400490", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x100400490", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.ANY_SNOOP OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F80020490", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x1000020490", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x800020490", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x400020490", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x100020490", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x200020490", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x80020490", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_PF_RFO.ANY_RESPONSE have any response type.", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_RFO.ANY_RESPONSE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x10120", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F803C0120", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x10003C0120", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x8003C0120", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x4003C0120", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x1003C0120", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x8007C0120", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_MISS OCR.ALL_PF_RFO.L3_HIT.SNOOP_MISS", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_MISS", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x2003C0120", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_NONE OCR.ALL_PF_RFO.L3_HIT.SNOOP_NONE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_NONE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x803C0120", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT_E.ANY_SNOOP", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.ANY_SNOOP", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F80080120", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT_E.HITM_OTHER_CORE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.HITM_OTHER_CORE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x1000080120", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x800080120", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x400080120", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT_E.NO_SNOOP_NEEDED", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.NO_SNOOP_NEEDED", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x100080120", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_MISS", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_MISS", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x200080120", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_NONE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_NONE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x80080120", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT_F.ANY_SNOOP", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.ANY_SNOOP", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F80200120", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT_F.HITM_OTHER_CORE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.HITM_OTHER_CORE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x1000200120", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x800200120", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x400200120", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT_F.NO_SNOOP_NEEDED", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.NO_SNOOP_NEEDED", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x100200120", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_MISS", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_MISS", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x200200120", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_NONE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_NONE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x80200120", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT_M.ANY_SNOOP", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.ANY_SNOOP", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F80040120", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT_M.HITM_OTHER_CORE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.HITM_OTHER_CORE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x1000040120", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x800040120", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x400040120", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT_M.NO_SNOOP_NEEDED", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.NO_SNOOP_NEEDED", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x100040120", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_MISS", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_MISS", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x200040120", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_NONE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_NONE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x80040120", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT_S.ANY_SNOOP", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.ANY_SNOOP", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F80100120", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT_S.HITM_OTHER_CORE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.HITM_OTHER_CORE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x1000100120", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x800100120", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x400100120", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT_S.NO_SNOOP_NEEDED", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.NO_SNOOP_NEEDED", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x100100120", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_MISS", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_MISS", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x200100120", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_NONE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_NONE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x80100120", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F80400120", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x80400120", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x100400120", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.ANY_SNOOP OCR.ALL_PF_RFO.SUPPLIER_NONE.ANY_SNOOP", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.ANY_SNOOP", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F80020120", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HITM_OTHER_CORE OCR.ALL_PF_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x1000020120", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x800020120", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x400020120", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x100020120", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_MISS", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_MISS", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x200020120", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NONE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NONE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x80020120", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_READS.ANY_RESPONSE have any response type.", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_READS.ANY_RESPONSE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x107F7", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_READS.L3_HIT.ANY_SNOOP OCR.ALL_READS.L3_HIT.ANY_SNOOP OCR.ALL_READS.L3_HIT.ANY_SNOOP", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_READS.L3_HIT.ANY_SNOOP", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F803C07F7", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x10003C07F7", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x8003C07F7", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x4003C07F7", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x1003C07F7", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_READS.L3_HIT.SNOOP_HIT_WITH_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_READS.L3_HIT.SNOOP_HIT_WITH_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x8007C07F7", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_READS.L3_HIT.SNOOP_MISS OCR.ALL_READS.L3_HIT.SNOOP_MISS", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_READS.L3_HIT.SNOOP_MISS", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x2003C07F7", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_READS.L3_HIT.SNOOP_NONE OCR.ALL_READS.L3_HIT.SNOOP_NONE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_READS.L3_HIT.SNOOP_NONE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x803C07F7", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_READS.L3_HIT_E.ANY_SNOOP OCR.ALL_READS.L3_HIT_E.ANY_SNOOP", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_READS.L3_HIT_E.ANY_SNOOP", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F800807F7", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_READS.L3_HIT_E.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT_E.HITM_OTHER_CORE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_READS.L3_HIT_E.HITM_OTHER_CORE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x10000807F7", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x8000807F7", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x4000807F7", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_READS.L3_HIT_E.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT_E.NO_SNOOP_NEEDED", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_READS.L3_HIT_E.NO_SNOOP_NEEDED", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x1000807F7", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_READS.L3_HIT_E.SNOOP_MISS", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_READS.L3_HIT_E.SNOOP_MISS", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x2000807F7", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_READS.L3_HIT_E.SNOOP_NONE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_READS.L3_HIT_E.SNOOP_NONE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x800807F7", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_READS.L3_HIT_F.ANY_SNOOP OCR.ALL_READS.L3_HIT_F.ANY_SNOOP", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_READS.L3_HIT_F.ANY_SNOOP", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F802007F7", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_READS.L3_HIT_F.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT_F.HITM_OTHER_CORE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_READS.L3_HIT_F.HITM_OTHER_CORE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x10002007F7", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x8002007F7", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x4002007F7", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_READS.L3_HIT_F.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT_F.NO_SNOOP_NEEDED", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_READS.L3_HIT_F.NO_SNOOP_NEEDED", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x1002007F7", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_READS.L3_HIT_F.SNOOP_MISS", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_READS.L3_HIT_F.SNOOP_MISS", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x2002007F7", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_READS.L3_HIT_F.SNOOP_NONE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_READS.L3_HIT_F.SNOOP_NONE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x802007F7", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_READS.L3_HIT_M.ANY_SNOOP OCR.ALL_READS.L3_HIT_M.ANY_SNOOP", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_READS.L3_HIT_M.ANY_SNOOP", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F800407F7", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_READS.L3_HIT_M.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT_M.HITM_OTHER_CORE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_READS.L3_HIT_M.HITM_OTHER_CORE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x10000407F7", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x8000407F7", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x4000407F7", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_READS.L3_HIT_M.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT_M.NO_SNOOP_NEEDED", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_READS.L3_HIT_M.NO_SNOOP_NEEDED", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x1000407F7", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_READS.L3_HIT_M.SNOOP_MISS", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_READS.L3_HIT_M.SNOOP_MISS", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x2000407F7", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_READS.L3_HIT_M.SNOOP_NONE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_READS.L3_HIT_M.SNOOP_NONE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x800407F7", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_READS.L3_HIT_S.ANY_SNOOP OCR.ALL_READS.L3_HIT_S.ANY_SNOOP", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_READS.L3_HIT_S.ANY_SNOOP", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F801007F7", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_READS.L3_HIT_S.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT_S.HITM_OTHER_CORE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_READS.L3_HIT_S.HITM_OTHER_CORE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x10001007F7", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x8001007F7", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x4001007F7", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_READS.L3_HIT_S.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT_S.NO_SNOOP_NEEDED", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_READS.L3_HIT_S.NO_SNOOP_NEEDED", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x1001007F7", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_READS.L3_HIT_S.SNOOP_MISS", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_READS.L3_HIT_S.SNOOP_MISS", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x2001007F7", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_READS.L3_HIT_S.SNOOP_NONE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_READS.L3_HIT_S.SNOOP_NONE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x801007F7", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_READS.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F804007F7", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x804007F7", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x1004007F7", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.ANY_SNOOP OCR.ALL_READS.SUPPLIER_NONE.ANY_SNOOP", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_READS.SUPPLIER_NONE.ANY_SNOOP", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F800207F7", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.HITM_OTHER_CORE OCR.ALL_READS.SUPPLIER_NONE.HITM_OTHER_CORE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_READS.SUPPLIER_NONE.HITM_OTHER_CORE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x10000207F7", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_FWD OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x8000207F7", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x4000207F7", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.NO_SNOOP_NEEDED OCR.ALL_READS.SUPPLIER_NONE.NO_SNOOP_NEEDED", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_READS.SUPPLIER_NONE.NO_SNOOP_NEEDED", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x1000207F7", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.SNOOP_MISS", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_READS.SUPPLIER_NONE.SNOOP_MISS", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x2000207F7", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.SNOOP_NONE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_READS.SUPPLIER_NONE.SNOOP_NONE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x800207F7", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_RFO.ANY_RESPONSE have any response type.", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_RFO.ANY_RESPONSE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x10122", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_RFO.L3_HIT.ANY_SNOOP OCR.ALL_RFO.L3_HIT.ANY_SNOOP OCR.ALL_RFO.L3_HIT.ANY_SNOOP", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_RFO.L3_HIT.ANY_SNOOP", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F803C0122", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x10003C0122", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x8003C0122", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x4003C0122", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x1003C0122", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x8007C0122", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_RFO.L3_HIT.SNOOP_MISS OCR.ALL_RFO.L3_HIT.SNOOP_MISS", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_RFO.L3_HIT.SNOOP_MISS", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x2003C0122", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_RFO.L3_HIT.SNOOP_NONE OCR.ALL_RFO.L3_HIT.SNOOP_NONE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_RFO.L3_HIT.SNOOP_NONE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x803C0122", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.ANY_SNOOP OCR.ALL_RFO.L3_HIT_E.ANY_SNOOP", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_RFO.L3_HIT_E.ANY_SNOOP", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F80080122", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT_E.HITM_OTHER_CORE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_RFO.L3_HIT_E.HITM_OTHER_CORE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x1000080122", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x800080122", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x400080122", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT_E.NO_SNOOP_NEEDED", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_RFO.L3_HIT_E.NO_SNOOP_NEEDED", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x100080122", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.SNOOP_MISS", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_RFO.L3_HIT_E.SNOOP_MISS", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x200080122", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.SNOOP_NONE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_RFO.L3_HIT_E.SNOOP_NONE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x80080122", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.ANY_SNOOP OCR.ALL_RFO.L3_HIT_F.ANY_SNOOP", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_RFO.L3_HIT_F.ANY_SNOOP", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F80200122", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT_F.HITM_OTHER_CORE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_RFO.L3_HIT_F.HITM_OTHER_CORE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x1000200122", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x800200122", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x400200122", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT_F.NO_SNOOP_NEEDED", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_RFO.L3_HIT_F.NO_SNOOP_NEEDED", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x100200122", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.SNOOP_MISS", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_RFO.L3_HIT_F.SNOOP_MISS", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x200200122", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.SNOOP_NONE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_RFO.L3_HIT_F.SNOOP_NONE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x80200122", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.ANY_SNOOP OCR.ALL_RFO.L3_HIT_M.ANY_SNOOP", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_RFO.L3_HIT_M.ANY_SNOOP", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F80040122", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT_M.HITM_OTHER_CORE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_RFO.L3_HIT_M.HITM_OTHER_CORE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x1000040122", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x800040122", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x400040122", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT_M.NO_SNOOP_NEEDED", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_RFO.L3_HIT_M.NO_SNOOP_NEEDED", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x100040122", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.SNOOP_MISS", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_RFO.L3_HIT_M.SNOOP_MISS", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x200040122", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.SNOOP_NONE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_RFO.L3_HIT_M.SNOOP_NONE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x80040122", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.ANY_SNOOP OCR.ALL_RFO.L3_HIT_S.ANY_SNOOP", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_RFO.L3_HIT_S.ANY_SNOOP", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F80100122", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT_S.HITM_OTHER_CORE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_RFO.L3_HIT_S.HITM_OTHER_CORE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x1000100122", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x800100122", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x400100122", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT_S.NO_SNOOP_NEEDED", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_RFO.L3_HIT_S.NO_SNOOP_NEEDED", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x100100122", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.SNOOP_MISS", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_RFO.L3_HIT_S.SNOOP_MISS", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x200100122", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.SNOOP_NONE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_RFO.L3_HIT_S.SNOOP_NONE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x80100122", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F80400122", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x80400122", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x100400122", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.ANY_SNOOP OCR.ALL_RFO.SUPPLIER_NONE.ANY_SNOOP", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.ANY_SNOOP", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F80020122", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.HITM_OTHER_CORE OCR.ALL_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x1000020122", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x800020122", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x400020122", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED OCR.ALL_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x100020122", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_MISS", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_MISS", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x200020122", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_NONE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_NONE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x80020122", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand code reads have any response type.", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_CODE_RD.ANY_RESPONSE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x10004", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP OCR.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F803C0004", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE OCR.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x10003C0004", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x8003C0004", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x4003C0004", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDED OCR.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDED", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDED", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x1003C0004", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand code reads", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x8007C0004", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x2003C0004", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NONE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NONE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x803C0004", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_E.ANY_SNOOP", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.ANY_SNOOP", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F80080004", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_E.HITM_OTHER_CORE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.HITM_OTHER_CORE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x1000080004", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x800080004", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x400080004", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_E.NO_SNOOP_NEEDED", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.NO_SNOOP_NEEDED", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x100080004", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand code reads", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.SNOOP_MISS", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x200080004", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand code reads", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NONE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x80080004", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_F.ANY_SNOOP", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.ANY_SNOOP", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F80200004", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_F.HITM_OTHER_CORE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.HITM_OTHER_CORE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x1000200004", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x800200004", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x400200004", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_F.NO_SNOOP_NEEDED", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.NO_SNOOP_NEEDED", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x100200004", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand code reads", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.SNOOP_MISS", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x200200004", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand code reads", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.SNOOP_NONE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x80200004", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_M.ANY_SNOOP", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.ANY_SNOOP", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F80040004", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_M.HITM_OTHER_CORE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.HITM_OTHER_CORE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x1000040004", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x800040004", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x400040004", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_M.NO_SNOOP_NEEDED", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.NO_SNOOP_NEEDED", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x100040004", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand code reads", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.SNOOP_MISS", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x200040004", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand code reads", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NONE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x80040004", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_S.ANY_SNOOP", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.ANY_SNOOP", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F80100004", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_S.HITM_OTHER_CORE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.HITM_OTHER_CORE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x1000100004", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x800100004", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x400100004", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_S.NO_SNOOP_NEEDED", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.NO_SNOOP_NEEDED", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x100100004", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand code reads", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.SNOOP_MISS", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x200100004", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand code reads", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NONE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x80100004", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F80400004", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x80400004", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x100400004", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.SUPPLIER_NONE.ANY_SNOOP", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.ANY_SNOOP", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F80020004", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HITM_OTHER_CORE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HITM_OTHER_CORE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x1000020004", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x800020004", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x400020004", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x100020004", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand code reads", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_MISS", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x200020004", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand code reads", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NONE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x80020004", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts demand data reads have any response type.", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x10001", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP OCR.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F803C0001", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x10003C0001", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x8003C0001", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x4003C0001", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x1003C0001", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts demand data reads", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x8007C0001", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x2003C0001", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NONE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NONE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x803C0001", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_E.ANY_SNOOP", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.ANY_SNOOP", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F80080001", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x1000080001", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x800080001", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x400080001", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x100080001", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts demand data reads", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.SNOOP_MISS", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x200080001", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts demand data reads", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NONE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x80080001", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_F.ANY_SNOOP", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.ANY_SNOOP", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F80200001", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x1000200001", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x800200001", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x400200001", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x100200001", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts demand data reads", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.SNOOP_MISS", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x200200001", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts demand data reads", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.SNOOP_NONE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x80200001", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_M.ANY_SNOOP", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.ANY_SNOOP", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F80040001", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x1000040001", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x800040001", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x400040001", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x100040001", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts demand data reads", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.SNOOP_MISS", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x200040001", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts demand data reads", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.SNOOP_NONE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x80040001", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_S.ANY_SNOOP", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.ANY_SNOOP", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F80100001", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x1000100001", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x800100001", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x400100001", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x100100001", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts demand data reads", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.SNOOP_MISS", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x200100001", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts demand data reads", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.SNOOP_NONE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x80100001", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F80400001", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x80400001", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x100400001", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F80020001", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x1000020001", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x800020001", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x400020001", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x100020001", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts demand data reads", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x200020001", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts demand data reads", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x80020001", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand data writes (RFOs) have any response type.", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x10002", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.ANY_SNOOP OCR.DEMAND_RFO.L3_HIT.ANY_SNOOP", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_RFO.L3_HIT.ANY_SNOOP", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F803C0002", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x10003C0002", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x8003C0002", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x4003C0002", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x1003C0002", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand data writes (RFOs)", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x8007C0002", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x2003C0002", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.SNOOP_NONE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_NONE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x803C0002", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_E.ANY_SNOOP", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_RFO.L3_HIT_E.ANY_SNOOP", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F80080002", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_E.HITM_OTHER_CORE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_RFO.L3_HIT_E.HITM_OTHER_CORE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x1000080002", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x800080002", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x400080002", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_E.NO_SNOOP_NEEDED", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_RFO.L3_HIT_E.NO_SNOOP_NEEDED", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x100080002", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand data writes (RFOs)", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_RFO.L3_HIT_E.SNOOP_MISS", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x200080002", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand data writes (RFOs)", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_RFO.L3_HIT_E.SNOOP_NONE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x80080002", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_F.ANY_SNOOP", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_RFO.L3_HIT_F.ANY_SNOOP", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F80200002", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_F.HITM_OTHER_CORE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_RFO.L3_HIT_F.HITM_OTHER_CORE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x1000200002", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x800200002", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x400200002", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_F.NO_SNOOP_NEEDED", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_RFO.L3_HIT_F.NO_SNOOP_NEEDED", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x100200002", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand data writes (RFOs)", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_RFO.L3_HIT_F.SNOOP_MISS", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x200200002", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand data writes (RFOs)", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_RFO.L3_HIT_F.SNOOP_NONE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x80200002", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_M.ANY_SNOOP", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_RFO.L3_HIT_M.ANY_SNOOP", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F80040002", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_M.HITM_OTHER_CORE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_RFO.L3_HIT_M.HITM_OTHER_CORE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x1000040002", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x800040002", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x400040002", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_M.NO_SNOOP_NEEDED", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_RFO.L3_HIT_M.NO_SNOOP_NEEDED", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x100040002", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand data writes (RFOs)", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_RFO.L3_HIT_M.SNOOP_MISS", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x200040002", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand data writes (RFOs)", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_RFO.L3_HIT_M.SNOOP_NONE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x80040002", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_S.ANY_SNOOP", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_RFO.L3_HIT_S.ANY_SNOOP", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F80100002", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_S.HITM_OTHER_CORE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_RFO.L3_HIT_S.HITM_OTHER_CORE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x1000100002", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x800100002", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x400100002", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_S.NO_SNOOP_NEEDED", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_RFO.L3_HIT_S.NO_SNOOP_NEEDED", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x100100002", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand data writes (RFOs)", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_RFO.L3_HIT_S.SNOOP_MISS", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x200100002", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand data writes (RFOs)", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_RFO.L3_HIT_S.SNOOP_NONE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x80100002", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F80400002", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x80400002", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x100400002", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.SUPPLIER_NONE.ANY_SNOOP", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.ANY_SNOOP", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F80020002", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x1000020002", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x800020002", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x400020002", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x100020002", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand data writes (RFOs)", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.SNOOP_MISS", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x200020002", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all demand data writes (RFOs)", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.SNOOP_NONE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x80020002", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts any other requests have any response type.", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.OTHER.ANY_RESPONSE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x18000", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.ANY_SNOOP OCR.OTHER.L3_HIT.ANY_SNOOP", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.OTHER.L3_HIT.ANY_SNOOP", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F803C8000", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.HITM_OTHER_CORE OCR.OTHER.L3_HIT.HITM_OTHER_CORE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.OTHER.L3_HIT.HITM_OTHER_CORE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x10003C8000", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.HIT_OTHER_CORE_FWD OCR.OTHER.L3_HIT.HIT_OTHER_CORE_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.OTHER.L3_HIT.HIT_OTHER_CORE_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x8003C8000", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.OTHER.L3_HIT.HIT_OTHER_CORE_NO_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.OTHER.L3_HIT.HIT_OTHER_CORE_NO_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x4003C8000", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.NO_SNOOP_NEEDED OCR.OTHER.L3_HIT.NO_SNOOP_NEEDED", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.OTHER.L3_HIT.NO_SNOOP_NEEDED", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x1003C8000", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts any other requests", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.OTHER.L3_HIT.SNOOP_HIT_WITH_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x8007C8000", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.SNOOP_MISS", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.OTHER.L3_HIT.SNOOP_MISS", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x2003C8000", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.SNOOP_NONE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.OTHER.L3_HIT.SNOOP_NONE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x803C8000", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_E.ANY_SNOOP", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.OTHER.L3_HIT_E.ANY_SNOOP", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F80088000", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_E.HITM_OTHER_CORE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.OTHER.L3_HIT_E.HITM_OTHER_CORE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x1000088000", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x800088000", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x400088000", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_E.NO_SNOOP_NEEDED", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.OTHER.L3_HIT_E.NO_SNOOP_NEEDED", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x100088000", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts any other requests", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.OTHER.L3_HIT_E.SNOOP_MISS", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x200088000", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts any other requests", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.OTHER.L3_HIT_E.SNOOP_NONE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x80088000", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_F.ANY_SNOOP", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.OTHER.L3_HIT_F.ANY_SNOOP", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F80208000", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_F.HITM_OTHER_CORE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.OTHER.L3_HIT_F.HITM_OTHER_CORE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x1000208000", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x800208000", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x400208000", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_F.NO_SNOOP_NEEDED", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.OTHER.L3_HIT_F.NO_SNOOP_NEEDED", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x100208000", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts any other requests", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.OTHER.L3_HIT_F.SNOOP_MISS", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x200208000", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts any other requests", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.OTHER.L3_HIT_F.SNOOP_NONE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x80208000", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_M.ANY_SNOOP", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.OTHER.L3_HIT_M.ANY_SNOOP", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F80048000", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_M.HITM_OTHER_CORE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.OTHER.L3_HIT_M.HITM_OTHER_CORE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x1000048000", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x800048000", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x400048000", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_M.NO_SNOOP_NEEDED", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.OTHER.L3_HIT_M.NO_SNOOP_NEEDED", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x100048000", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts any other requests", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.OTHER.L3_HIT_M.SNOOP_MISS", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x200048000", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts any other requests", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.OTHER.L3_HIT_M.SNOOP_NONE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x80048000", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_S.ANY_SNOOP", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.OTHER.L3_HIT_S.ANY_SNOOP", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F80108000", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_S.HITM_OTHER_CORE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.OTHER.L3_HIT_S.HITM_OTHER_CORE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x1000108000", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x800108000", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x400108000", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_S.NO_SNOOP_NEEDED", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.OTHER.L3_HIT_S.NO_SNOOP_NEEDED", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x100108000", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts any other requests", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.OTHER.L3_HIT_S.SNOOP_MISS", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x200108000", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts any other requests", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.OTHER.L3_HIT_S.SNOOP_NONE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x80108000", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts any other requests OCR.OTHER.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.OTHER.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F80408000", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts any other requests OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x80408000", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts any other requests OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x100408000", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts any other requests OCR.OTHER.SUPPLIER_NONE.ANY_SNOOP", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.OTHER.SUPPLIER_NONE.ANY_SNOOP", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F80028000", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts any other requests OCR.OTHER.SUPPLIER_NONE.HITM_OTHER_CORE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.OTHER.SUPPLIER_NONE.HITM_OTHER_CORE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x1000028000", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts any other requests OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x800028000", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts any other requests OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x400028000", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts any other requests OCR.OTHER.SUPPLIER_NONE.NO_SNOOP_NEEDED", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.OTHER.SUPPLIER_NONE.NO_SNOOP_NEEDED", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x100028000", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts any other requests", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.OTHER.SUPPLIER_NONE.SNOOP_MISS", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x200028000", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts any other requests", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.OTHER.SUPPLIER_NONE.SNOOP_NONE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x80028000", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests have any response type.", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L1D_AND_SW.ANY_RESPONSE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x10400", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.ANY_SNOOP OCR.PF_L1D_AND_SW.L3_HIT.ANY_SNOOP", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.ANY_SNOOP", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F803C0400", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.HITM_OTHER_CORE OCR.PF_L1D_AND_SW.L3_HIT.HITM_OTHER_CORE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.HITM_OTHER_CORE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x10003C0400", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x8003C0400", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_NO_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_NO_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x4003C0400", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDED", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDED", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x1003C0400", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_HIT_WITH_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x8007C0400", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_MISS", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_MISS", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x2003C0400", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_NONE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_NONE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x803C0400", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_E.ANY_SNOOP", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.ANY_SNOOP", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F80080400", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_E.HITM_OTHER_CORE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.HITM_OTHER_CORE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x1000080400", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x800080400", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x400080400", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_E.NO_SNOOP_NEEDED", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.NO_SNOOP_NEEDED", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x100080400", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.SNOOP_MISS", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x200080400", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.SNOOP_NONE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x80080400", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_F.ANY_SNOOP", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.ANY_SNOOP", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F80200400", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_F.HITM_OTHER_CORE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.HITM_OTHER_CORE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x1000200400", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x800200400", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x400200400", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_F.NO_SNOOP_NEEDED", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.NO_SNOOP_NEEDED", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x100200400", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.SNOOP_MISS", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x200200400", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.SNOOP_NONE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x80200400", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_M.ANY_SNOOP", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.ANY_SNOOP", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F80040400", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_M.HITM_OTHER_CORE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.HITM_OTHER_CORE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x1000040400", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x800040400", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x400040400", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_M.NO_SNOOP_NEEDED", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.NO_SNOOP_NEEDED", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x100040400", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.SNOOP_MISS", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x200040400", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.SNOOP_NONE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x80040400", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_S.ANY_SNOOP", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.ANY_SNOOP", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F80100400", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_S.HITM_OTHER_CORE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.HITM_OTHER_CORE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x1000100400", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x800100400", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x400100400", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_S.NO_SNOOP_NEEDED", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.NO_SNOOP_NEEDED", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x100100400", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.SNOOP_MISS", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x200100400", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.SNOOP_NONE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x80100400", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F80400400", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x80400400", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x100400400", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.SUPPLIER_NONE.ANY_SNOOP", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.ANY_SNOOP", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F80020400", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HITM_OTHER_CORE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HITM_OTHER_CORE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x1000020400", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x800020400", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x400020400", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.SUPPLIER_NONE.NO_SNOOP_NEEDED", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.NO_SNOOP_NEEDED", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x100020400", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.SNOOP_MISS", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x200020400", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.SNOOP_NONE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x80020400", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads have any response type.", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_DATA_RD.ANY_RESPONSE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x10010", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP OCR.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F803C0010", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.PF_L2_DATA_RD.L3_HIT.HITM_OTHER_CORE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.HITM_OTHER_CORE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x10003C0010", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x8003C0010", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x4003C0010", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x1003C0010", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x8007C0010", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_MISS", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_MISS", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x2003C0010", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_NONE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_NONE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x803C0010", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_E.ANY_SNOOP", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.ANY_SNOOP", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F80080010", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x1000080010", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x800080010", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x400080010", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x100080010", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.SNOOP_MISS", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x200080010", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.SNOOP_NONE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x80080010", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_F.ANY_SNOOP", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.ANY_SNOOP", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F80200010", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x1000200010", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x800200010", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x400200010", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x100200010", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.SNOOP_MISS", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x200200010", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.SNOOP_NONE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x80200010", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_M.ANY_SNOOP", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.ANY_SNOOP", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F80040010", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x1000040010", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x800040010", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x400040010", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x100040010", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.SNOOP_MISS", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x200040010", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.SNOOP_NONE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x80040010", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_S.ANY_SNOOP", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.ANY_SNOOP", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F80100010", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x1000100010", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x800100010", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x400100010", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x100100010", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.SNOOP_MISS", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x200100010", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.SNOOP_NONE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x80100010", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F80400010", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x80400010", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x100400010", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F80020010", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x1000020010", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x800020010", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x400020010", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x100020010", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x200020010", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts prefetch (that bring data to L2) data reads", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x80020010", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs have any response type.", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_RFO.ANY_RESPONSE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x10020", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.ANY_SNOOP OCR.PF_L2_RFO.L3_HIT.ANY_SNOOP", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_RFO.L3_HIT.ANY_SNOOP", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F803C0020", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x10003C0020", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x8003C0020", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x4003C0020", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x1003C0020", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x8007C0020", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.SNOOP_MISS", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_RFO.L3_HIT.SNOOP_MISS", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x2003C0020", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.SNOOP_NONE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_RFO.L3_HIT.SNOOP_NONE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x803C0020", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_E.ANY_SNOOP", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_RFO.L3_HIT_E.ANY_SNOOP", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F80080020", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_E.HITM_OTHER_CORE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_RFO.L3_HIT_E.HITM_OTHER_CORE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x1000080020", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x800080020", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x400080020", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_E.NO_SNOOP_NEEDED", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_RFO.L3_HIT_E.NO_SNOOP_NEEDED", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x100080020", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_RFO.L3_HIT_E.SNOOP_MISS", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x200080020", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_RFO.L3_HIT_E.SNOOP_NONE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x80080020", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_F.ANY_SNOOP", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_RFO.L3_HIT_F.ANY_SNOOP", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F80200020", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_F.HITM_OTHER_CORE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_RFO.L3_HIT_F.HITM_OTHER_CORE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x1000200020", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x800200020", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x400200020", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_F.NO_SNOOP_NEEDED", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_RFO.L3_HIT_F.NO_SNOOP_NEEDED", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x100200020", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_RFO.L3_HIT_F.SNOOP_MISS", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x200200020", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_RFO.L3_HIT_F.SNOOP_NONE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x80200020", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_M.ANY_SNOOP", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_RFO.L3_HIT_M.ANY_SNOOP", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F80040020", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_M.HITM_OTHER_CORE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_RFO.L3_HIT_M.HITM_OTHER_CORE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x1000040020", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x800040020", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x400040020", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_M.NO_SNOOP_NEEDED", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_RFO.L3_HIT_M.NO_SNOOP_NEEDED", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x100040020", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_RFO.L3_HIT_M.SNOOP_MISS", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x200040020", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_RFO.L3_HIT_M.SNOOP_NONE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x80040020", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_S.ANY_SNOOP", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_RFO.L3_HIT_S.ANY_SNOOP", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F80100020", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_S.HITM_OTHER_CORE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_RFO.L3_HIT_S.HITM_OTHER_CORE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x1000100020", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x800100020", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x400100020", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_S.NO_SNOOP_NEEDED", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_RFO.L3_HIT_S.NO_SNOOP_NEEDED", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x100100020", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_RFO.L3_HIT_S.SNOOP_MISS", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x200100020", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_RFO.L3_HIT_S.SNOOP_NONE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x80100020", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F80400020", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x80400020", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x100400020", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.SUPPLIER_NONE.ANY_SNOOP", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.ANY_SNOOP", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F80020020", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x1000020020", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x800020020", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x400020020", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x100020020", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.SNOOP_MISS", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x200020020", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.SNOOP_NONE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x80020020", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads have any response type.", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L3_DATA_RD.ANY_RESPONSE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x10080", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP OCR.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F803C0080", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.PF_L3_DATA_RD.L3_HIT.HITM_OTHER_CORE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.HITM_OTHER_CORE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x10003C0080", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x8003C0080", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x4003C0080", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x1003C0080", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x8007C0080", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_MISS", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_MISS", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x2003C0080", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_NONE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_NONE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x803C0080", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_E.ANY_SNOOP", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.ANY_SNOOP", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F80080080", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x1000080080", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x800080080", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x400080080", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x100080080", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.SNOOP_MISS", > > - "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x200080080", > > - "Offcore": "1", > > - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > - "SampleAfterValue": "100003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3", > > - "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.SNOOP_NONE", > > + "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x80080080", > > + "MSRValue": "0x200020001", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_F.ANY_SNOOP", > > + "BriefDescription": "Counts demand data reads", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.ANY_SNOOP", > > + "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F80200080", > > + "MSRValue": "0x80020001", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", > > + "BriefDescription": "Counts all demand data writes (RFOs) have any response type.", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", > > + "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x1000200080", > > + "MSRValue": "0x10002", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", > > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", > > + "EventName": "OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x800200080", > > + "MSRValue": "0x3F80400002", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > > + "EventName": "OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x400200080", > > + "MSRValue": "0x80400002", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", > > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", > > + "EventName": "OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x100200080", > > + "MSRValue": "0x100400002", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", > > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.SUPPLIER_NONE.ANY_SNOOP", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.SNOOP_MISS", > > + "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.ANY_SNOOP", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x200200080", > > + "MSRValue": "0x3F80020002", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", > > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.SNOOP_NONE", > > + "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x80200080", > > + "MSRValue": "0x1000020002", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_M.ANY_SNOOP", > > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.ANY_SNOOP", > > + "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F80040080", > > + "MSRValue": "0x800020002", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", > > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", > > + "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x1000040080", > > + "MSRValue": "0x400020002", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", > > + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", > > + "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x800040080", > > + "MSRValue": "0x100020002", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > > + "BriefDescription": "Counts all demand data writes (RFOs)", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > > + "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.SNOOP_MISS", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x400040080", > > + "MSRValue": "0x200020002", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", > > + "BriefDescription": "Counts all demand data writes (RFOs)", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", > > + "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.SNOOP_NONE", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x100040080", > > + "MSRValue": "0x80020002", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", > > + "BriefDescription": "Counts any other requests have any response type.", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.SNOOP_MISS", > > + "EventName": "OCR.OTHER.ANY_RESPONSE", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x200040080", > > + "MSRValue": "0x18000", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", > > + "BriefDescription": "Counts any other requests OCR.OTHER.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.SNOOP_NONE", > > + "EventName": "OCR.OTHER.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x80040080", > > + "MSRValue": "0x3F80408000", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_S.ANY_SNOOP", > > + "BriefDescription": "Counts any other requests OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.ANY_SNOOP", > > + "EventName": "OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F80100080", > > + "MSRValue": "0x80408000", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", > > + "BriefDescription": "Counts any other requests OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", > > + "EventName": "OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x1000100080", > > + "MSRValue": "0x100408000", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", > > + "BriefDescription": "Counts any other requests OCR.OTHER.SUPPLIER_NONE.ANY_SNOOP", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", > > + "EventName": "OCR.OTHER.SUPPLIER_NONE.ANY_SNOOP", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x800100080", > > + "MSRValue": "0x3F80028000", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > > + "BriefDescription": "Counts any other requests OCR.OTHER.SUPPLIER_NONE.HITM_OTHER_CORE", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > > + "EventName": "OCR.OTHER.SUPPLIER_NONE.HITM_OTHER_CORE", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x400100080", > > + "MSRValue": "0x1000028000", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", > > + "BriefDescription": "Counts any other requests OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", > > + "EventName": "OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x100100080", > > + "MSRValue": "0x800028000", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", > > + "BriefDescription": "Counts any other requests OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.SNOOP_MISS", > > + "EventName": "OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x200100080", > > + "MSRValue": "0x400028000", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", > > + "BriefDescription": "Counts any other requests OCR.OTHER.SUPPLIER_NONE.NO_SNOOP_NEEDED", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.SNOOP_NONE", > > + "EventName": "OCR.OTHER.SUPPLIER_NONE.NO_SNOOP_NEEDED", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x80100080", > > + "MSRValue": "0x100028000", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > > + "BriefDescription": "Counts any other requests", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > > + "EventName": "OCR.OTHER.SUPPLIER_NONE.SNOOP_MISS", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F80400080", > > + "MSRValue": "0x200028000", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > > + "BriefDescription": "Counts any other requests", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > > + "EventName": "OCR.OTHER.SUPPLIER_NONE.SNOOP_NONE", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x80400080", > > + "MSRValue": "0x80028000", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests have any response type.", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > > + "EventName": "OCR.PF_L1D_AND_SW.ANY_RESPONSE", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x100400080", > > + "MSRValue": "0x10400", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", > > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", > > + "EventName": "OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F80020080", > > + "MSRValue": "0x3F80400400", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", > > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", > > + "EventName": "OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x1000020080", > > + "MSRValue": "0x80400400", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > > + "EventName": "OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x800020080", > > + "MSRValue": "0x100400400", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.SUPPLIER_NONE.ANY_SNOOP", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > > + "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.ANY_SNOOP", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x400020080", > > + "MSRValue": "0x3F80020400", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", > > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HITM_OTHER_CORE", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", > > + "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HITM_OTHER_CORE", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x100020080", > > + "MSRValue": "0x1000020400", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", > > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", > > + "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x200020080", > > + "MSRValue": "0x800020400", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", > > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", > > + "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x80020080", > > + "MSRValue": "0x400020400", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs have any response type.", > > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.SUPPLIER_NONE.NO_SNOOP_NEEDED", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L3_RFO.ANY_RESPONSE", > > + "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.NO_SNOOP_NEEDED", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x10100", > > + "MSRValue": "0x100020400", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.ANY_SNOOP OCR.PF_L3_RFO.L3_HIT.ANY_SNOOP", > > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L3_RFO.L3_HIT.ANY_SNOOP", > > + "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.SNOOP_MISS", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F803C0100", > > + "MSRValue": "0x200020400", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.HITM_OTHER_CORE OCR.PF_L3_RFO.L3_HIT.HITM_OTHER_CORE", > > + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L3_RFO.L3_HIT.HITM_OTHER_CORE", > > + "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.SNOOP_NONE", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x10003C0100", > > + "MSRValue": "0x80020400", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_FWD", > > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads have any response type.", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_FWD", > > + "EventName": "OCR.PF_L2_DATA_RD.ANY_RESPONSE", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x8003C0100", > > + "MSRValue": "0x10010", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", > > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", > > + "EventName": "OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x4003C0100", > > + "MSRValue": "0x3F80400010", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED", > > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED", > > + "EventName": "OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x1003C0100", > > + "MSRValue": "0x80400010", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", > > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L3_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", > > + "EventName": "OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x8007C0100", > > + "MSRValue": "0x100400010", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.SNOOP_MISS", > > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L3_RFO.L3_HIT.SNOOP_MISS", > > + "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x2003C0100", > > + "MSRValue": "0x3F80020010", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.SNOOP_NONE", > > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L3_RFO.L3_HIT.SNOOP_NONE", > > + "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x803C0100", > > + "MSRValue": "0x1000020010", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_E.ANY_SNOOP", > > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L3_RFO.L3_HIT_E.ANY_SNOOP", > > + "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F80080100", > > + "MSRValue": "0x800020010", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_E.HITM_OTHER_CORE", > > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L3_RFO.L3_HIT_E.HITM_OTHER_CORE", > > + "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x1000080100", > > + "MSRValue": "0x400020010", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", > > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", > > + "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x800080100", > > + "MSRValue": "0x100020010", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", > > + "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x400080100", > > + "MSRValue": "0x200020010", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_E.NO_SNOOP_NEEDED", > > + "BriefDescription": "Counts prefetch (that bring data to L2) data reads", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L3_RFO.L3_HIT_E.NO_SNOOP_NEEDED", > > + "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x100080100", > > + "MSRValue": "0x80020010", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", > > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs have any response type.", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L3_RFO.L3_HIT_E.SNOOP_MISS", > > + "EventName": "OCR.PF_L2_RFO.ANY_RESPONSE", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x200080100", > > + "MSRValue": "0x10020", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", > > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L3_RFO.L3_HIT_E.SNOOP_NONE", > > + "EventName": "OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x80080100", > > + "MSRValue": "0x3F80400020", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_F.ANY_SNOOP", > > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L3_RFO.L3_HIT_F.ANY_SNOOP", > > + "EventName": "OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F80200100", > > + "MSRValue": "0x80400020", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_F.HITM_OTHER_CORE", > > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L3_RFO.L3_HIT_F.HITM_OTHER_CORE", > > + "EventName": "OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x1000200100", > > + "MSRValue": "0x100400020", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", > > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.SUPPLIER_NONE.ANY_SNOOP", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", > > + "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.ANY_SNOOP", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x800200100", > > + "MSRValue": "0x3F80020020", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", > > + "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x400200100", > > + "MSRValue": "0x1000020020", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_F.NO_SNOOP_NEEDED", > > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L3_RFO.L3_HIT_F.NO_SNOOP_NEEDED", > > + "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x100200100", > > + "MSRValue": "0x800020020", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", > > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L3_RFO.L3_HIT_F.SNOOP_MISS", > > + "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x200200100", > > + "MSRValue": "0x400020020", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", > > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L3_RFO.L3_HIT_F.SNOOP_NONE", > > + "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x80200100", > > + "MSRValue": "0x100020020", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_M.ANY_SNOOP", > > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L3_RFO.L3_HIT_M.ANY_SNOOP", > > + "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.SNOOP_MISS", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F80040100", > > + "MSRValue": "0x200020020", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_M.HITM_OTHER_CORE", > > + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L3_RFO.L3_HIT_M.HITM_OTHER_CORE", > > + "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.SNOOP_NONE", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x1000040100", > > + "MSRValue": "0x80020020", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", > > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads have any response type.", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", > > + "EventName": "OCR.PF_L3_DATA_RD.ANY_RESPONSE", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x800040100", > > + "MSRValue": "0x10080", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", > > + "EventName": "OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x400040100", > > + "MSRValue": "0x3F80400080", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_M.NO_SNOOP_NEEDED", > > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L3_RFO.L3_HIT_M.NO_SNOOP_NEEDED", > > + "EventName": "OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x100040100", > > + "MSRValue": "0x80400080", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", > > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L3_RFO.L3_HIT_M.SNOOP_MISS", > > + "EventName": "OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x200040100", > > + "MSRValue": "0x100400080", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", > > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L3_RFO.L3_HIT_M.SNOOP_NONE", > > + "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x80040100", > > + "MSRValue": "0x3F80020080", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_S.ANY_SNOOP", > > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L3_RFO.L3_HIT_S.ANY_SNOOP", > > + "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x3F80100100", > > + "MSRValue": "0x1000020080", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_S.HITM_OTHER_CORE", > > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L3_RFO.L3_HIT_S.HITM_OTHER_CORE", > > + "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x1000100100", > > + "MSRValue": "0x800020080", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", > > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", > > + "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x800100100", > > + "MSRValue": "0x400020080", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", > > + "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x400100100", > > + "MSRValue": "0x100020080", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_S.NO_SNOOP_NEEDED", > > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L3_RFO.L3_HIT_S.NO_SNOOP_NEEDED", > > + "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x100100100", > > + "MSRValue": "0x200020080", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", > > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L3_RFO.L3_HIT_S.SNOOP_MISS", > > + "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x200100100", > > + "MSRValue": "0x80020080", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > }, > > { > > - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", > > + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs have any response type.", > > "Counter": "0,1,2,3", > > "CounterHTOff": "0,1,2,3", > > "EventCode": "0xB7, 0xBB", > > - "EventName": "OCR.PF_L3_RFO.L3_HIT_S.SNOOP_NONE", > > + "EventName": "OCR.PF_L3_RFO.ANY_RESPONSE", > > "MSRIndex": "0x1a6,0x1a7", > > - "MSRValue": "0x80100100", > > + "MSRValue": "0x10100", > > "Offcore": "1", > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > @@ -8622,41 +2070,5 @@ > > "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", > > "SampleAfterValue": "100003", > > "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Number of PREFETCHNTA instructions executed.", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3,4,5,6,7", > > - "EventCode": "0x32", > > - "EventName": "SW_PREFETCH_ACCESS.NTA", > > - "SampleAfterValue": "2000003", > > - "UMask": "0x1" > > - }, > > - { > > - "BriefDescription": "Number of PREFETCHW instructions executed.", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3,4,5,6,7", > > - "EventCode": "0x32", > > - "EventName": "SW_PREFETCH_ACCESS.PREFETCHW", > > - "SampleAfterValue": "2000003", > > - "UMask": "0x8" > > - }, > > - { > > - "BriefDescription": "Number of PREFETCHT0 instructions executed.", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3,4,5,6,7", > > - "EventCode": "0x32", > > - "EventName": "SW_PREFETCH_ACCESS.T0", > > - "SampleAfterValue": "2000003", > > - "UMask": "0x2" > > - }, > > - { > > - "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.", > > - "Counter": "0,1,2,3", > > - "CounterHTOff": "0,1,2,3,4,5,6,7", > > - "EventCode": "0x32", > > - "EventName": "SW_PREFETCH_ACCESS.T1_T2", > > - "SampleAfterValue": "2000003", > > - "UMask": "0x4" > > } > > ] > > \ No newline at end of file > > -- > Zhengjun Xing -- - Arnaldo ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 1/8] perf vendor events: Update events for CascadelakeX 2022-03-17 18:28 [PATCH 1/8] perf vendor events: Update events for CascadelakeX Ian Rogers ` (7 preceding siblings ...) 2022-03-18 9:09 ` [PATCH 1/8] perf vendor events: Update events for CascadelakeX Xing Zhengjun @ 2022-03-18 9:14 ` John Garry 8 siblings, 0 replies; 18+ messages in thread From: John Garry @ 2022-03-18 9:14 UTC (permalink / raw) To: Ian Rogers, Kan Liang, Zhengjun Xing, Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo, Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim, Maxime Coquelin, Alexandre Torgue, Andi Kleen, James Clark, linux-kernel, linux-perf-users Cc: Stephane Eranian On 17/03/2022 18:28, Ian Rogers wrote: > The change: > https://github.com/intel/event-converter-for-linux-perf/commit/fc680410402e394eed6a1ebd909c9f649d3ed3ef > moved certain "other" type of events in to the cache topic. Update the > perf json files for this change. > > Tested: > ``` > ... > 6: Parse event definition strings : Ok > 7: Simple expression parser : Ok > 8: PERF_RECORD_* events & perf_sample fields : Ok > 9: Parse perf pmu format : Ok > 10: PMU events : > 10.1: PMU event table sanity : Ok > 10.2: PMU event map aliases : Ok > 10.3: Parsing of PMU event table metrics : Ok > 10.4: Parsing of PMU event table metrics with fake PMUs : Ok > ... > 68: Parse and process metrics : Ok > ... > 89: perf all metricgroups test : Ok > 90: perf all metrics test : FAILED! > 91: perf all PMU test : Ok > ... > ``` > > Test 90 failed due to MEM_PMM_Read_Latency as the test machine > lacks optane memory, and the divide by 0 causes the metric not to > print - which is intended behavior. Hi Ian, Failing is not ideal as an intended/expected behaviour. Could we make the test skip somehow for the case you describe? Thanks, John ^ permalink raw reply [flat|nested] 18+ messages in thread
end of thread, other threads:[~2022-03-18 14:45 UTC | newest] Thread overview: 18+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2022-03-17 18:28 [PATCH 1/8] perf vendor events: Update events for CascadelakeX Ian Rogers 2022-03-17 18:28 ` [PATCH 2/8] perf vendor events: Update events for Elkhartlake Ian Rogers 2022-03-18 9:12 ` Xing Zhengjun 2022-03-17 18:28 ` [PATCH 3/8] perf vendor events: Update events for Icelake Ian Rogers 2022-03-18 9:15 ` Xing Zhengjun 2022-03-17 18:28 ` [PATCH 4/8] perf vendor events: Update events for IcelakeX Ian Rogers 2022-03-18 9:19 ` Xing Zhengjun 2022-03-17 18:28 ` [PATCH 5/8] perf vendor events: Update events for Skylake Ian Rogers 2022-03-18 9:19 ` Xing Zhengjun 2022-03-17 18:28 ` [PATCH 6/8] perf vendor events: Update events for SkylakeX Ian Rogers 2022-03-18 9:21 ` Xing Zhengjun 2022-03-17 18:28 ` [PATCH 7/8] perf vendor events: Update events for Tigerlake Ian Rogers 2022-03-18 9:22 ` Xing Zhengjun 2022-03-17 18:28 ` [PATCH 8/8] perf vendor events: Update events for TremontX Ian Rogers 2022-03-18 9:26 ` Xing Zhengjun 2022-03-18 9:09 ` [PATCH 1/8] perf vendor events: Update events for CascadelakeX Xing Zhengjun 2022-03-18 14:44 ` Arnaldo Carvalho de Melo 2022-03-18 9:14 ` John Garry
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