* [PATCH] riscv: add Andes SoC family Kconfig support
@ 2025-03-05 3:05 Ben Zong-You Xie
2025-03-06 16:40 ` Conor Dooley
0 siblings, 1 reply; 5+ messages in thread
From: Ben Zong-You Xie @ 2025-03-05 3:05 UTC (permalink / raw)
To: linux-riscv, linux-kernel
Cc: paul.walmsley, palmer, aou, alex, Ben Zong-You Xie
The first SoC in the Andes series is QiLai. It includes a high-performance
quad-core RISC-V AX45MP cluster and one NX27V vector processor.
For further information, refer to [1].
[1] https://www.andestech.com/en/products-solutions/andeshape-platforms/qilai-chip/
Signed-off-by: Ben Zong-You Xie <ben717@andestech.com>
---
arch/riscv/Kconfig.errata | 2 +-
arch/riscv/Kconfig.socs | 9 +++++++++
2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata
index e318119d570d..be76883704a6 100644
--- a/arch/riscv/Kconfig.errata
+++ b/arch/riscv/Kconfig.errata
@@ -12,7 +12,7 @@ config ERRATA_ANDES
config ERRATA_ANDES_CMO
bool "Apply Andes cache management errata"
- depends on ERRATA_ANDES && ARCH_R9A07G043
+ depends on ERRATA_ANDES && (ARCH_R9A07G043 || ARCH_ANDES)
select RISCV_DMA_NONCOHERENT
default y
help
diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index 1916cf7ba450..b89b6e0d1bc9 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -1,5 +1,14 @@
menu "SoC selection"
+config ARCH_ANDES
+ bool "Andes SoCs"
+ depends on MMU && !XIP_KERNEL
+ select ERRATA_ANDES
+ select ERRATA_ANDES_CMO
+ select AX45MP_L2_CACHE
+ help
+ This enables support for Andes SoC platform hardware.
+
config ARCH_MICROCHIP_POLARFIRE
def_bool ARCH_MICROCHIP
--
2.34.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH] riscv: add Andes SoC family Kconfig support
2025-03-05 3:05 [PATCH] riscv: add Andes SoC family Kconfig support Ben Zong-You Xie
@ 2025-03-06 16:40 ` Conor Dooley
2025-03-07 10:36 ` Ben Zong-You Xie
0 siblings, 1 reply; 5+ messages in thread
From: Conor Dooley @ 2025-03-06 16:40 UTC (permalink / raw)
To: Ben Zong-You Xie
Cc: linux-riscv, linux-kernel, paul.walmsley, palmer, aou, alex
[-- Attachment #1: Type: text/plain, Size: 2029 bytes --]
On Wed, Mar 05, 2025 at 11:05:26AM +0800, Ben Zong-You Xie wrote:
> The first SoC in the Andes series is QiLai. It includes a high-performance
> quad-core RISC-V AX45MP cluster and one NX27V vector processor.
I'd expect a config option like this to come with the user, which in
this case is the dts etc for a board using the QiLai SoC or drivers for
the SoC. Without dts or drivers, there's no reason to ever enable this,
so where are those patches?
Cheers,
Conor.
>
> For further information, refer to [1].
>
> [1] https://www.andestech.com/en/products-solutions/andeshape-platforms/qilai-chip/
>
> Signed-off-by: Ben Zong-You Xie <ben717@andestech.com>
> ---
> arch/riscv/Kconfig.errata | 2 +-
> arch/riscv/Kconfig.socs | 9 +++++++++
> 2 files changed, 10 insertions(+), 1 deletion(-)
>
> diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata
> index e318119d570d..be76883704a6 100644
> --- a/arch/riscv/Kconfig.errata
> +++ b/arch/riscv/Kconfig.errata
> @@ -12,7 +12,7 @@ config ERRATA_ANDES
>
> config ERRATA_ANDES_CMO
> bool "Apply Andes cache management errata"
> - depends on ERRATA_ANDES && ARCH_R9A07G043
> + depends on ERRATA_ANDES && (ARCH_R9A07G043 || ARCH_ANDES)
> select RISCV_DMA_NONCOHERENT
> default y
> help
> diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
> index 1916cf7ba450..b89b6e0d1bc9 100644
> --- a/arch/riscv/Kconfig.socs
> +++ b/arch/riscv/Kconfig.socs
> @@ -1,5 +1,14 @@
> menu "SoC selection"
>
> +config ARCH_ANDES
> + bool "Andes SoCs"
> + depends on MMU && !XIP_KERNEL
> + select ERRATA_ANDES
> + select ERRATA_ANDES_CMO
> + select AX45MP_L2_CACHE
> + help
> + This enables support for Andes SoC platform hardware.
> +
> config ARCH_MICROCHIP_POLARFIRE
> def_bool ARCH_MICROCHIP
>
> --
> 2.34.1
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
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^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] riscv: add Andes SoC family Kconfig support
2025-03-06 16:40 ` Conor Dooley
@ 2025-03-07 10:36 ` Ben Zong-You Xie
2025-05-08 17:48 ` Palmer Dabbelt
0 siblings, 1 reply; 5+ messages in thread
From: Ben Zong-You Xie @ 2025-03-07 10:36 UTC (permalink / raw)
To: Conor Dooley
Cc: linux-riscv, linux-kernel, paul.walmsley, palmer, aou, alex,
tim609
On Thu, Mar 06, 2025 at 04:40:49PM +0000, Conor Dooley wrote:
> [EXTERNAL MAIL]
> Date: Thu, 6 Mar 2025 16:40:49 +0000
> From: Conor Dooley <conor@kernel.org>
> To: Ben Zong-You Xie <ben717@andestech.com>
> Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
> paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu,
> alex@ghiti.fr
> Subject: Re: [PATCH] riscv: add Andes SoC family Kconfig support
>
> On Wed, Mar 05, 2025 at 11:05:26AM +0800, Ben Zong-You Xie wrote:
> > The first SoC in the Andes series is QiLai. It includes a high-performance
> > quad-core RISC-V AX45MP cluster and one NX27V vector processor.
>
> I'd expect a config option like this to come with the user, which in
> this case is the dts etc for a board using the QiLai SoC or drivers for
> the SoC. Without dts or drivers, there's no reason to ever enable this,
> so where are those patches?
>
> Cheers,
> Conor.
>
Hi Conor,
We are still preparing those patches for upstream, and we will add them
in the next patch series.
Thanks,
Ben
> >
> > For further information, refer to [1].
> >
> > [1] https://www.andestech.com/en/products-solutions/andeshape-platforms/qilai-chip/
> >
> > Signed-off-by: Ben Zong-You Xie <ben717@andestech.com>
> > ---
> > arch/riscv/Kconfig.errata | 2 +-
> > arch/riscv/Kconfig.socs | 9 +++++++++
> > 2 files changed, 10 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata
> > index e318119d570d..be76883704a6 100644
> > --- a/arch/riscv/Kconfig.errata
> > +++ b/arch/riscv/Kconfig.errata
> > @@ -12,7 +12,7 @@ config ERRATA_ANDES
> >
> > config ERRATA_ANDES_CMO
> > bool "Apply Andes cache management errata"
> > - depends on ERRATA_ANDES && ARCH_R9A07G043
> > + depends on ERRATA_ANDES && (ARCH_R9A07G043 || ARCH_ANDES)
> > select RISCV_DMA_NONCOHERENT
> > default y
> > help
> > diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
> > index 1916cf7ba450..b89b6e0d1bc9 100644
> > --- a/arch/riscv/Kconfig.socs
> > +++ b/arch/riscv/Kconfig.socs
> > @@ -1,5 +1,14 @@
> > menu "SoC selection"
> >
> > +config ARCH_ANDES
> > + bool "Andes SoCs"
> > + depends on MMU && !XIP_KERNEL
> > + select ERRATA_ANDES
> > + select ERRATA_ANDES_CMO
> > + select AX45MP_L2_CACHE
> > + help
> > + This enables support for Andes SoC platform hardware.
> > +
> > config ARCH_MICROCHIP_POLARFIRE
> > def_bool ARCH_MICROCHIP
> >
> > --
> > 2.34.1
> >
> >
> > _______________________________________________
> > linux-riscv mailing list
> > linux-riscv@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] riscv: add Andes SoC family Kconfig support
2025-03-07 10:36 ` Ben Zong-You Xie
@ 2025-05-08 17:48 ` Palmer Dabbelt
2025-05-09 6:00 ` Ben Zong-You Xie
0 siblings, 1 reply; 5+ messages in thread
From: Palmer Dabbelt @ 2025-05-08 17:48 UTC (permalink / raw)
To: ben717
Cc: Conor Dooley, linux-riscv, linux-kernel, Paul Walmsley, aou, alex,
tim609
On Fri, 07 Mar 2025 02:36:25 PST (-0800), ben717@andestech.com wrote:
> On Thu, Mar 06, 2025 at 04:40:49PM +0000, Conor Dooley wrote:
>> [EXTERNAL MAIL]
>
>> Date: Thu, 6 Mar 2025 16:40:49 +0000
>> From: Conor Dooley <conor@kernel.org>
>> To: Ben Zong-You Xie <ben717@andestech.com>
>> Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
>> paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu,
>> alex@ghiti.fr
>> Subject: Re: [PATCH] riscv: add Andes SoC family Kconfig support
>>
>> On Wed, Mar 05, 2025 at 11:05:26AM +0800, Ben Zong-You Xie wrote:
>> > The first SoC in the Andes series is QiLai. It includes a high-performance
>> > quad-core RISC-V AX45MP cluster and one NX27V vector processor.
>>
>> I'd expect a config option like this to come with the user, which in
>> this case is the dts etc for a board using the QiLai SoC or drivers for
>> the SoC. Without dts or drivers, there's no reason to ever enable this,
>> so where are those patches?
>>
>> Cheers,
>> Conor.
>>
>
> Hi Conor,
>
> We are still preparing those patches for upstream, and we will add them
> in the next patch series.
This is still "Needs Ack" in patchwork, so
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Though like Conor says, we need the rest of the code to do anything
here, so that's really just a way to get it out of my queue ;)
>
> Thanks,
> Ben
>
>> >
>> > For further information, refer to [1].
>> >
>> > [1] https://www.andestech.com/en/products-solutions/andeshape-platforms/qilai-chip/
>> >
>> > Signed-off-by: Ben Zong-You Xie <ben717@andestech.com>
>> > ---
>> > arch/riscv/Kconfig.errata | 2 +-
>> > arch/riscv/Kconfig.socs | 9 +++++++++
>> > 2 files changed, 10 insertions(+), 1 deletion(-)
>> >
>> > diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata
>> > index e318119d570d..be76883704a6 100644
>> > --- a/arch/riscv/Kconfig.errata
>> > +++ b/arch/riscv/Kconfig.errata
>> > @@ -12,7 +12,7 @@ config ERRATA_ANDES
>> >
>> > config ERRATA_ANDES_CMO
>> > bool "Apply Andes cache management errata"
>> > - depends on ERRATA_ANDES && ARCH_R9A07G043
>> > + depends on ERRATA_ANDES && (ARCH_R9A07G043 || ARCH_ANDES)
>> > select RISCV_DMA_NONCOHERENT
>> > default y
>> > help
>> > diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
>> > index 1916cf7ba450..b89b6e0d1bc9 100644
>> > --- a/arch/riscv/Kconfig.socs
>> > +++ b/arch/riscv/Kconfig.socs
>> > @@ -1,5 +1,14 @@
>> > menu "SoC selection"
>> >
>> > +config ARCH_ANDES
>> > + bool "Andes SoCs"
>> > + depends on MMU && !XIP_KERNEL
>> > + select ERRATA_ANDES
>> > + select ERRATA_ANDES_CMO
>> > + select AX45MP_L2_CACHE
>> > + help
>> > + This enables support for Andes SoC platform hardware.
>> > +
>> > config ARCH_MICROCHIP_POLARFIRE
>> > def_bool ARCH_MICROCHIP
>> >
>> > --
>> > 2.34.1
>> >
>> >
>> > _______________________________________________
>> > linux-riscv mailing list
>> > linux-riscv@lists.infradead.org
>> > http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] riscv: add Andes SoC family Kconfig support
2025-05-08 17:48 ` Palmer Dabbelt
@ 2025-05-09 6:00 ` Ben Zong-You Xie
0 siblings, 0 replies; 5+ messages in thread
From: Ben Zong-You Xie @ 2025-05-09 6:00 UTC (permalink / raw)
To: Palmer Dabbelt
Cc: Conor Dooley, linux-riscv, linux-kernel, Paul Walmsley, aou, alex,
tim609
On Thu, May 08, 2025 at 10:48:46AM -0700, Palmer Dabbelt wrote:
> [EXTERNAL MAIL]
>
> On Fri, 07 Mar 2025 02:36:25 PST (-0800), ben717@andestech.com wrote:
> > On Thu, Mar 06, 2025 at 04:40:49PM +0000, Conor Dooley wrote:
> > > [EXTERNAL MAIL]
> >
> > > Date: Thu, 6 Mar 2025 16:40:49 +0000
> > > From: Conor Dooley <conor@kernel.org>
> > > To: Ben Zong-You Xie <ben717@andestech.com>
> > > Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
> > > paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu,
> > > alex@ghiti.fr
> > > Subject: Re: [PATCH] riscv: add Andes SoC family Kconfig support
> > >
> > > On Wed, Mar 05, 2025 at 11:05:26AM +0800, Ben Zong-You Xie wrote:
> > > > The first SoC in the Andes series is QiLai. It includes a high-performance
> > > > quad-core RISC-V AX45MP cluster and one NX27V vector processor.
> > >
> > > I'd expect a config option like this to come with the user, which in
> > > this case is the dts etc for a board using the QiLai SoC or drivers for
> > > the SoC. Without dts or drivers, there's no reason to ever enable this,
> > > so where are those patches?
> > >
> > > Cheers,
> > > Conor.
> > >
> >
> > Hi Conor,
> >
> > We are still preparing those patches for upstream, and we will add them
> > in the next patch series.
>
> This is still "Needs Ack" in patchwork, so
>
> Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
>
> Though like Conor says, we need the rest of the code to do anything
> here, so that's really just a way to get it out of my queue ;)
>
I have not added the remaining code in the next version of this patch series.
Instead, I’ve submitted a new patch series [1] that incorporates this patch.
Maybe add your Acked-by tag to the new series and disregard this patch.
[1] https://patchwork.kernel.org/project/linux-riscv/cover/20250503151829.605006-1-ben717@andestech.com/
Thanks,
Ben
> >
> > Thanks,
> > Ben
> >
> > > >
> > > > For further information, refer to [1].
> > > >
> > > > [1] https://www.andestech.com/en/products-solutions/andeshape-platforms/qilai-chip/
> > > >
> > > > Signed-off-by: Ben Zong-You Xie <ben717@andestech.com>
> > > > ---
> > > > arch/riscv/Kconfig.errata | 2 +-
> > > > arch/riscv/Kconfig.socs | 9 +++++++++
> > > > 2 files changed, 10 insertions(+), 1 deletion(-)
> > > >
> > > > diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata
> > > > index e318119d570d..be76883704a6 100644
> > > > --- a/arch/riscv/Kconfig.errata
> > > > +++ b/arch/riscv/Kconfig.errata
> > > > @@ -12,7 +12,7 @@ config ERRATA_ANDES
> > > >
> > > > config ERRATA_ANDES_CMO
> > > > bool "Apply Andes cache management errata"
> > > > - depends on ERRATA_ANDES && ARCH_R9A07G043
> > > > + depends on ERRATA_ANDES && (ARCH_R9A07G043 || ARCH_ANDES)
> > > > select RISCV_DMA_NONCOHERENT
> > > > default y
> > > > help
> > > > diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
> > > > index 1916cf7ba450..b89b6e0d1bc9 100644
> > > > --- a/arch/riscv/Kconfig.socs
> > > > +++ b/arch/riscv/Kconfig.socs
> > > > @@ -1,5 +1,14 @@
> > > > menu "SoC selection"
> > > >
> > > > +config ARCH_ANDES
> > > > + bool "Andes SoCs"
> > > > + depends on MMU && !XIP_KERNEL
> > > > + select ERRATA_ANDES
> > > > + select ERRATA_ANDES_CMO
> > > > + select AX45MP_L2_CACHE
> > > > + help
> > > > + This enables support for Andes SoC platform hardware.
> > > > +
> > > > config ARCH_MICROCHIP_POLARFIRE
> > > > def_bool ARCH_MICROCHIP
> > > >
> > > > --
> > > > 2.34.1
> > > >
> > > >
> > > > _______________________________________________
> > > > linux-riscv mailing list
> > > > linux-riscv@lists.infradead.org
> > > > http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 5+ messages in thread
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Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-03-05 3:05 [PATCH] riscv: add Andes SoC family Kconfig support Ben Zong-You Xie
2025-03-06 16:40 ` Conor Dooley
2025-03-07 10:36 ` Ben Zong-You Xie
2025-05-08 17:48 ` Palmer Dabbelt
2025-05-09 6:00 ` Ben Zong-You Xie
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