Re: [PATCH v5 2/2] spi: dw: Add dma controller capability checks

[Andy Shevchenko <andriy.shevchenko@intel.com>]

On Thu, Mar 30, 2023 at 06:34:50AM +0000, Joy Chakraborty wrote:
> Check capabilities of DMA controller during init to make sure it is
> capable of handling MEM2DEV for tx channel, DEV2MEM for rx channel
> and store addr_width capabilities to check per transfer to make sure the
> bits/word requirement can be met for that transfer.

...

> +static enum dma_slave_buswidth dw_spi_dma_convert_width(u8 n_bytes);

Can we avoid forward declarations please?

...

> +	if (!(tx.directions & BIT(DMA_MEM_TO_DEV) &&
> +	      rx.directions & BIT(DMA_DEV_TO_MEM)))
> +		return -ENXIO;

What about simplex transfers where we only care about sending or receiving data
and using dummy data for the other channel? Doesn't this make a regression for
that types of transfers? (Or, if we don't support such, this should be explained
in the commit message at least.)

...

> +	/*
> +	 * Assuming both channels belong to the same DMA controller hence the
> +	 * address width capabilities most likely would be the same.
> +	 */
> +	dws->dma_addr_widths = tx.dst_addr_widths & rx.src_addr_widths;

I don't think so this is correct.

Theoretically it's possible to have simplex transfers on which the one of
the channel is simply ignored / not used. See above.

-- 
With Best Regards,
Andy Shevchenko