[PATCH 0/7] phy: qcom: Add register offsets for v6 and v7

[PATCH 0/7] phy: qcom: Add register offsets for v6 and v7

[Abel Vesa]

This patchset adds some missing register offsets for the v6 and v6.20,
as well as the new v7 ones. These register offsets are used by the
new Qualcomm Snapdragon X Elite (X1E80100) platform.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
---
Abel Vesa (7):
      phy: qcom-qmp: qserdes-com: Add some more v6 register offsets
      phy: qcom-qmp: qserdes-txrx: Add some more v6.20 register offsets
      phy: qcom-qmp: pcs: Add v7 register offsets
      phy: qcom-qmp: pcs-usb: Add v7 register offsets
      phy: qcom-qmp: qserdes-com: Add v7 register offsets
      phy: qcom-qmp: qserdes-txrx: Add V6 N4 register offsets
      phy: qcom-qmp: qserdes-txrx: Add v7 register offsets

 drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v7.h     | 31 ++++++++
 drivers/phy/qualcomm/phy-qcom-qmp-pcs-v7.h         | 28 +++++++
 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h |  5 ++
 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v7.h | 86 ++++++++++++++++++++++
 .../phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6.h    |  1 +
 .../phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_20.h |  4 +
 .../phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_n4.h | 51 +++++++++++++
 .../phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v7.h    | 78 ++++++++++++++++++++
 drivers/phy/qualcomm/phy-qcom-qmp.h                |  6 ++
 9 files changed, 290 insertions(+)
---
base-commit: 07b677953b9dca02928be323e2db853511305fa9
change-id: 20231122-phy-qualcomm-v6-v6-20-v7-new-offsets-5ed528c88f62

Best regards,
-- 
Abel Vesa <abel.vesa@linaro.org>

[PATCH 1/7] phy: qcom-qmp: qserdes-com: Add some more v6 register offsets

[Abel Vesa]

Add some missing V6 registers offsets that are needed by the new
Snapdragon X Elite (X1E80100) platform.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
---
 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h  | 5 +++++
 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6.h | 1 +
 2 files changed, 6 insertions(+)

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
index f420f8faf16a..ec7291424dd1 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
@@ -22,6 +22,8 @@
 #define QSERDES_V6_COM_DIV_FRAC_START2_MODE1			0x34
 #define QSERDES_V6_COM_DIV_FRAC_START3_MODE1			0x38
 #define QSERDES_V6_COM_HSCLK_SEL_1				0x3c
+#define QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE1			0x40
+#define QSERDES_V6_COM_INTEGLOOP_GAIN1_MODE1			0x44
 #define QSERDES_V6_COM_VCO_TUNE1_MODE1				0x48
 #define QSERDES_V6_COM_VCO_TUNE2_MODE1				0x4c
 #define QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE1		0x50
@@ -48,6 +50,7 @@
 #define QSERDES_V6_COM_VCO_TUNE2_MODE0				0xac
 #define QSERDES_V6_COM_BG_TIMER					0xbc
 #define QSERDES_V6_COM_SSC_EN_CENTER				0xc0
+#define QSERDES_V6_COM_SSC_ADJ_PER1				0xc4
 #define QSERDES_V6_COM_SSC_PER1					0xcc
 #define QSERDES_V6_COM_SSC_PER2					0xd0
 #define QSERDES_V6_COM_PLL_POST_DIV_MUX				0xd8
@@ -56,6 +59,7 @@
 #define QSERDES_V6_COM_SYS_CLK_CTRL				0xe4
 #define QSERDES_V6_COM_SYSCLK_BUF_ENABLE			0xe8
 #define QSERDES_V6_COM_PLL_IVCO					0xf4
+#define QSERDES_V6_COM_PLL_IVCO_MODE1				0xf8
 #define QSERDES_V6_COM_SYSCLK_EN_SEL				0x110
 #define QSERDES_V6_COM_RESETSM_CNTRL				0x118
 #define QSERDES_V6_COM_LOCK_CMP_EN				0x120
@@ -63,6 +67,7 @@
 #define QSERDES_V6_COM_VCO_TUNE_CTRL				0x13c
 #define QSERDES_V6_COM_VCO_TUNE_MAP				0x140
 #define QSERDES_V6_COM_VCO_TUNE_INITVAL2			0x148
+#define QSERDES_V6_COM_VCO_TUNE_MAXVAL2				0x158
 #define QSERDES_V6_COM_CLK_SELECT				0x164
 #define QSERDES_V6_COM_CORE_CLK_EN				0x170
 #define QSERDES_V6_COM_CMN_CONFIG_1				0x174
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6.h
index 8883e1de730e..23ffcfae9efa 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6.h
@@ -23,6 +23,7 @@
 #define QSERDES_V6_TX_PARRATE_REC_DETECT_IDLE_EN		0x60
 #define QSERDES_V6_TX_BIST_PATTERN7				0x7c
 #define QSERDES_V6_TX_LANE_MODE_1				0x84
+#define QSERDES_V6_TX_LANE_MODE_2				0x88
 #define QSERDES_V6_TX_LANE_MODE_3				0x8c
 #define QSERDES_V6_TX_LANE_MODE_4				0x90
 #define QSERDES_V6_TX_LANE_MODE_5				0x94

-- 
2.34.1

[PATCH 2/7] phy: qcom-qmp: qserdes-txrx: Add some more v6.20 register offsets

[Abel Vesa]

Add some missing v6.20 registers offsets that are needed by the new
Snapdragon X Elite (X1E80100) platform.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
---
 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_20.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_20.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_20.h
index 5385a8b60970..7402a94d1be8 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_20.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_20.h
@@ -14,11 +14,14 @@
 #define QSERDES_V6_20_TX_LANE_MODE_3				0x80
 
 #define QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2			0x08
+#define QSERDES_V6_20_RX_UCDR_SO_GAIN_RATE_2			0x18
 #define QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3			0x0c
 #define QSERDES_V6_20_RX_UCDR_PI_CONTROLS			0x20
 #define QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3		0x34
 #define QSERDES_V6_20_RX_IVCM_CAL_CTRL2				0x9c
 #define QSERDES_V6_20_RX_IVCM_POSTCAL_OFFSET			0xa0
+#define QSERDES_V6_20_RX_DFE_1					0xac
+#define QSERDES_V6_20_RX_DFE_2					0xb0
 #define QSERDES_V6_20_RX_DFE_3					0xb4
 #define QSERDES_V6_20_RX_VGA_CAL_MAN_VAL			0xe8
 #define QSERDES_V6_20_RX_GM_CAL					0x10c
@@ -41,5 +44,6 @@
 #define QSERDES_V6_20_RX_MODE_RATE3_B4				0x220
 #define QSERDES_V6_20_RX_MODE_RATE3_B5				0x224
 #define QSERDES_V6_20_RX_MODE_RATE3_B6				0x228
+#define QSERDES_V6_20_RX_BKUP_CTRL1				0x22c
 
 #endif

-- 
2.34.1

[PATCH 3/7] phy: qcom-qmp: pcs: Add v7 register offsets

[Abel Vesa]

The X1E80100 platform bumps the HW version of QMP phy to v7 for USB,
and PCIe. Add the new PCS offsets in a dedicated header file.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
---
 drivers/phy/qualcomm/phy-qcom-qmp-pcs-v7.h | 28 ++++++++++++++++++++++++++++
 drivers/phy/qualcomm/phy-qcom-qmp.h        |  2 ++
 2 files changed, 30 insertions(+)

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v7.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v7.h
new file mode 100644
index 000000000000..520f28d802f6
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v7.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2023, Linaro Limited
+ */
+
+#ifndef QCOM_PHY_QMP_PCS_V7_H_
+#define QCOM_PHY_QMP_PCS_V7_H_
+
+/* Only for QMP V6 PHY - USB/PCIe PCS registers */
+
+#define QPHY_V7_PCS_LOCK_DETECT_CONFIG1			0xc4
+#define QPHY_V7_PCS_LOCK_DETECT_CONFIG2			0xc8
+#define QPHY_V7_PCS_LOCK_DETECT_CONFIG3			0xcc
+#define QPHY_V7_PCS_LOCK_DETECT_CONFIG6			0xd8
+#define QPHY_V7_PCS_REFGEN_REQ_CONFIG1			0xdc
+#define QPHY_V7_PCS_RX_SIGDET_LVL			0x188
+#define QPHY_V7_PCS_RCVR_DTCT_DLY_P1U2_L		0x190
+#define QPHY_V7_PCS_RCVR_DTCT_DLY_P1U2_H		0x194
+#define QPHY_V7_PCS_RATE_SLEW_CNTRL1			0x198
+#define QPHY_V7_PCS_RX_CONFIG				0x1b0
+#define QPHY_V7_PCS_ALIGN_DETECT_CONFIG1		0x1c0
+#define QPHY_V7_PCS_ALIGN_DETECT_CONFIG2		0x1c4
+#define QPHY_V7_PCS_PCS_TX_RX_CONFIG			0x1d0
+#define QPHY_V7_PCS_EQ_CONFIG1				0x1dc
+#define QPHY_V7_PCS_EQ_CONFIG2				0x1e0
+#define QPHY_V7_PCS_EQ_CONFIG5				0x1ec
+
+#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
index 71f063f4a56e..21f6a56e7ae3 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
@@ -44,6 +44,8 @@
 
 #include "phy-qcom-qmp-pcs-v6_20.h"
 
+#include "phy-qcom-qmp-pcs-v7.h"
+
 /* Only for QMP V3 & V4 PHY - DP COM registers */
 #define QPHY_V3_DP_COM_PHY_MODE_CTRL			0x00
 #define QPHY_V3_DP_COM_SW_RESET				0x04

-- 
2.34.1

[PATCH 4/7] phy: qcom-qmp: pcs-usb: Add v7 register offsets

[Abel Vesa]

The X1E80100 platform bumps the HW version of QMP phy to v7 for USB.
Add the new PCS USB specific offsets in a dedicated header file.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
---
 drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v7.h | 31 ++++++++++++++++++++++++++
 1 file changed, 31 insertions(+)

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v7.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v7.h
new file mode 100644
index 000000000000..dbb75964cef7
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v7.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2023, Linaro Limited
+ */
+
+#ifndef QCOM_PHY_QMP_PCS_USB_V7_H_
+#define QCOM_PHY_QMP_PCS_USB_V7_H_
+
+/* Only for QMP V6 PHY - USB3 have different offsets than V5 */
+#define QPHY_USB_V7_PCS_LOCK_DETECT_CONFIG1		0xc4
+#define QPHY_USB_V7_PCS_LOCK_DETECT_CONFIG2		0xc8
+#define QPHY_USB_V7_PCS_LOCK_DETECT_CONFIG3		0xcc
+#define QPHY_USB_V7_PCS_LOCK_DETECT_CONFIG6		0xd8
+#define QPHY_USB_V7_PCS_REFGEN_REQ_CONFIG1		0xdc
+#define QPHY_USB_V7_PCS_USB3_POWER_STATE_CONFIG1	0x90
+#define QPHY_USB_V7_PCS_RX_SIGDET_LVL			0x188
+#define QPHY_USB_V7_PCS_RCVR_DTCT_DLY_P1U2_L		0x190
+#define QPHY_USB_V7_PCS_RCVR_DTCT_DLY_P1U2_H		0x194
+#define QPHY_USB_V7_PCS_CDR_RESET_TIME			0x1b0
+#define QPHY_USB_V7_PCS_ALIGN_DETECT_CONFIG1		0x1c0
+#define QPHY_USB_V7_PCS_ALIGN_DETECT_CONFIG2		0x1c4
+#define QPHY_USB_V7_PCS_PCS_TX_RX_CONFIG		0x1d0
+#define QPHY_USB_V7_PCS_EQ_CONFIG1			0x1dc
+#define QPHY_USB_V7_PCS_EQ_CONFIG5			0x1ec
+
+#define QPHY_USB_V7_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL	0x18
+#define QPHY_USB_V7_PCS_USB3_RXEQTRAINING_DFE_TIME_S2	0x3c
+#define QPHY_USB_V7_PCS_USB3_RCVR_DTCT_DLY_U3_L		0x40
+#define QPHY_USB_V7_PCS_USB3_RCVR_DTCT_DLY_U3_H		0x44
+
+#endif

-- 
2.34.1

[PATCH 5/7] phy: qcom-qmp: qserdes-com: Add v7 register offsets

[Abel Vesa]

The X1E80100 platform bumps the HW version of QMP phy to v7 for USB
and PCIE g3x2. Add the new qserdes com offsets in a dedicated
header file.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
---
 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v7.h | 86 ++++++++++++++++++++++
 drivers/phy/qualcomm/phy-qcom-qmp.h                |  2 +
 2 files changed, 88 insertions(+)

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v7.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v7.h
new file mode 100644
index 000000000000..c8775ca1ab6b
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v7.h
@@ -0,0 +1,86 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2023, Linaro Limited
+ */
+
+#ifndef QCOM_PHY_QMP_QSERDES_COM_V7_H_
+#define QCOM_PHY_QMP_QSERDES_COM_V7_H_
+
+/* Only for QMP V6 PHY - QSERDES COM registers */
+
+#define QSERDES_V7_COM_SSC_STEP_SIZE1_MODE1			0x00
+#define QSERDES_V7_COM_SSC_STEP_SIZE2_MODE1			0x04
+#define QSERDES_V7_COM_CP_CTRL_MODE1				0x10
+#define QSERDES_V7_COM_PLL_RCTRL_MODE1				0x14
+#define QSERDES_V7_COM_PLL_CCTRL_MODE1				0x18
+#define QSERDES_V7_COM_CORECLK_DIV_MODE1			0x1c
+#define QSERDES_V7_COM_LOCK_CMP1_MODE1				0x20
+#define QSERDES_V7_COM_LOCK_CMP2_MODE1				0x24
+#define QSERDES_V7_COM_DEC_START_MODE1				0x28
+#define QSERDES_V7_COM_DEC_START_MSB_MODE1			0x2c
+#define QSERDES_V7_COM_DIV_FRAC_START1_MODE1			0x30
+#define QSERDES_V7_COM_DIV_FRAC_START2_MODE1			0x34
+#define QSERDES_V7_COM_DIV_FRAC_START3_MODE1			0x38
+#define QSERDES_V7_COM_HSCLK_SEL_1				0x3c
+#define QSERDES_V7_COM_INTEGLOOP_GAIN0_MODE1			0x40
+#define QSERDES_V7_COM_INTEGLOOP_GAIN1_MODE1			0x44
+#define QSERDES_V7_COM_VCO_TUNE1_MODE1				0x48
+#define QSERDES_V7_COM_VCO_TUNE2_MODE1				0x4c
+#define QSERDES_V7_COM_BIN_VCOCAL_CMP_CODE1_MODE1		0x50
+#define QSERDES_V7_COM_BIN_VCOCAL_CMP_CODE2_MODE1		0x54
+#define QSERDES_V7_COM_BIN_VCOCAL_CMP_CODE1_MODE0		0x58
+#define QSERDES_V7_COM_BIN_VCOCAL_CMP_CODE2_MODE0		0x5c
+#define QSERDES_V7_COM_SSC_STEP_SIZE1_MODE0			0x60
+#define QSERDES_V7_COM_SSC_STEP_SIZE2_MODE0			0x64
+#define QSERDES_V7_COM_CP_CTRL_MODE0				0x70
+#define QSERDES_V7_COM_PLL_RCTRL_MODE0				0x74
+#define QSERDES_V7_COM_PLL_CCTRL_MODE0				0x78
+#define QSERDES_V7_COM_PLL_CORE_CLK_DIV_MODE0			0x7c
+#define QSERDES_V7_COM_LOCK_CMP1_MODE0				0x80
+#define QSERDES_V7_COM_LOCK_CMP2_MODE0				0x84
+#define QSERDES_V7_COM_DEC_START_MODE0				0x88
+#define QSERDES_V7_COM_DEC_START_MSB_MODE0			0x8c
+#define QSERDES_V7_COM_DIV_FRAC_START1_MODE0			0x90
+#define QSERDES_V7_COM_DIV_FRAC_START2_MODE0			0x94
+#define QSERDES_V7_COM_DIV_FRAC_START3_MODE0			0x98
+#define QSERDES_V7_COM_HSCLK_HS_SWITCH_SEL_1			0x9c
+#define QSERDES_V7_COM_INTEGLOOP_GAIN0_MODE0			0xa0
+#define QSERDES_V7_COM_INTEGLOOP_GAIN1_MODE0			0xa4
+#define QSERDES_V7_COM_VCO_TUNE1_MODE0				0xa8
+#define QSERDES_V7_COM_VCO_TUNE2_MODE0				0xac
+#define QSERDES_V7_COM_BG_TIMER					0xbc
+#define QSERDES_V7_COM_SSC_EN_CENTER				0xc0
+#define QSERDES_V7_COM_SSC_PER1					0xcc
+#define QSERDES_V7_COM_SSC_PER2					0xd0
+#define QSERDES_V7_COM_PLL_POST_DIV_MUX				0xd8
+#define QSERDES_V7_COM_PLL_BIAS_EN_CLK_BUFLR_EN			0xdc
+#define QSERDES_V7_COM_CLK_ENABLE1				0xe0
+#define QSERDES_V7_COM_SYS_CLK_CTRL				0xe4
+#define QSERDES_V7_COM_SYSCLK_BUF_ENABLE			0xe8
+#define QSERDES_V7_COM_PLL_IVCO					0xf4
+#define QSERDES_V7_COM_PLL_IVCO_MODE1				0xf8
+#define QSERDES_V7_COM_SYSCLK_EN_SEL				0x110
+#define QSERDES_V7_COM_RESETSM_CNTRL				0x118
+#define QSERDES_V7_COM_LOCK_CMP_EN				0x120
+#define QSERDES_V7_COM_LOCK_CMP_CFG				0x124
+#define QSERDES_V7_COM_VCO_TUNE_CTRL				0x13c
+#define QSERDES_V7_COM_VCO_TUNE_MAP				0x140
+#define QSERDES_V7_COM_VCO_TUNE_INITVAL2			0x148
+#define QSERDES_V7_COM_VCO_TUNE_MAXVAL2				0x158
+#define QSERDES_V7_COM_CLK_SELECT				0x164
+#define QSERDES_V7_COM_CORE_CLK_EN				0x170
+#define QSERDES_V7_COM_CMN_CONFIG_1				0x174
+#define QSERDES_V7_COM_SVS_MODE_CLK_SEL				0x17c
+#define QSERDES_V7_COM_CMN_MISC_1				0x184
+#define QSERDES_V7_COM_CMN_MODE					0x188
+#define QSERDES_V7_COM_PLL_VCO_DC_LEVEL_CTRL			0x198
+#define QSERDES_V7_COM_AUTO_GAIN_ADJ_CTRL_1			0x1a4
+#define QSERDES_V7_COM_AUTO_GAIN_ADJ_CTRL_2			0x1a8
+#define QSERDES_V7_COM_AUTO_GAIN_ADJ_CTRL_3			0x1ac
+#define QSERDES_V7_COM_ADDITIONAL_MISC				0x1b4
+#define QSERDES_V7_COM_ADDITIONAL_MISC_2			0x1b8
+#define QSERDES_V7_COM_ADDITIONAL_MISC_3			0x1bc
+#define QSERDES_V7_COM_CMN_STATUS				0x1d0
+#define QSERDES_V7_COM_C_READY_STATUS				0x1f8
+
+#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
index 21f6a56e7ae3..3a0512c3e07a 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
@@ -26,6 +26,8 @@
 #include "phy-qcom-qmp-qserdes-txrx-v6_20.h"
 #include "phy-qcom-qmp-qserdes-ln-shrd-v6.h"
 
+#include "phy-qcom-qmp-qserdes-com-v7.h"
+
 #include "phy-qcom-qmp-qserdes-pll.h"
 
 #include "phy-qcom-qmp-pcs-v2.h"

-- 
2.34.1

[PATCH 6/7] phy: qcom-qmp: qserdes-txrx: Add V6 N4 register offsets

[Abel Vesa]

There is a variant of V6 offsets that are different, the QMP PHY N4,
and it is found on the X1E80100 platform.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
---
 .../phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_n4.h | 51 ++++++++++++++++++++++
 drivers/phy/qualcomm/phy-qcom-qmp.h                |  1 +
 2 files changed, 52 insertions(+)

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_n4.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_n4.h
new file mode 100644
index 000000000000..a814ad11af07
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_n4.h
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2023, Linaro Limited
+ */
+
+#ifndef QCOM_PHY_QMP_QSERDES_TXRX_V6_N4_H_
+#define QCOM_PHY_QMP_QSERDES_TXRX_V6_N4_H_
+
+#define QSERDES_V6_N4_TX_RES_CODE_LANE_OFFSET_TX	0x30
+#define QSERDES_V6_N4_TX_RES_CODE_LANE_OFFSET_RX	0x34
+#define QSERDES_V6_N4_TX_LANE_MODE_1			0x78
+#define QSERDES_V6_N4_TX_LANE_MODE_2			0x7c
+#define QSERDES_V6_N4_TX_LANE_MODE_3			0x80
+
+#define QSERDES_V6_N4_RX_UCDR_FO_GAIN_RATE2		0x8
+#define QSERDES_V6_N4_RX_UCDR_SO_GAIN_RATE2		0x18
+#define QSERDES_V6_N4_RX_UCDR_PI_CONTROLS		0x20
+#define QSERDES_V6_N4_RX_IVCM_CAL_CODE_OVERRIDE		0x94
+#define QSERDES_V6_N4_RX_RX_IVCM_CAL_CTRL2		0x9c
+#define QSERDES_V6_N4_RX_RX_IVCM_POSTCAL_OFFSET		0xa0
+#define QSERDES_V6_N4_RX_DFE_3				0xb4
+#define QSERDES_V6_N4_RX_VGA_CAL_CNTRL1			0xe0
+#define QSERDES_V6_N4_RX_VGA_CAL_MAN_VAL		0xe8
+#define QSERDES_V6_N4_RX_GM_CAL				0x10c
+#define QSERDES_V6_N4_RX_SIGDET_ENABLES			0x148
+#define QSERDES_V6_N4_RX_SIGDET_CNTRL			0x14c
+#define QSERDES_V6_N4_RX_SIGDET_DEGLITCH_CNTRL		0x154
+#define QSERDES_V6_N4_RX_DFE_CTLE_POST_CAL_OFFSET	0x194
+#define QSERDES_V6_N4_RX_Q_PI_INTRINSIC_BIAS_RATE32	0x1dc
+#define QSERDES_V6_N4_RX_UCDR_PI_CTRL1			0x23c
+#define QSERDES_V6_N4_RX_UCDR_PI_CTRL2			0x240
+#define QSERDES_V6_N4_RX_UCDR_SB2_GAIN2_RATE2		0x27c
+#define QSERDES_V6_N4_RX_DFE_DAC_ENABLE1		0x298
+#define QSERDES_V6_N4_RX_MODE_RATE_0_1_B0		0x2b8
+#define QSERDES_V6_N4_RX_MODE_RATE_0_1_B1		0x2bc
+#define QSERDES_V6_N4_RX_MODE_RATE_0_1_B2		0x2c0
+#define QSERDES_V6_N4_RX_MODE_RATE_0_1_B3		0x2c4
+#define QSERDES_V6_N4_RX_MODE_RATE_0_1_B4		0x2c8
+#define QSERDES_V6_N4_RX_MODE_RATE_0_1_B5		0x2cc
+#define QSERDES_V6_N4_RX_MODE_RATE_0_1_B6		0x2d0
+#define QSERDES_V6_N4_RX_MODE_RATE2_B0			0x2d4
+#define QSERDES_V6_N4_RX_MODE_RATE2_B1			0x2d8
+#define QSERDES_V6_N4_RX_MODE_RATE2_B2			0x2dc
+#define QSERDES_V6_N4_RX_MODE_RATE2_B3			0x2e0
+#define QSERDES_V6_N4_RX_MODE_RATE2_B4			0x2e4
+#define QSERDES_V6_N4_RX_MODE_RATE2_B5			0x2e8
+#define QSERDES_V6_N4_RX_MODE_RATE2_B6			0x2ec
+#define QSERDES_V6_N4_RX_RX_SUMMER_CAL_SPD_MODE		0x30c
+#define QSERDES_V6_N4_RX_RX_BKUP_CTRL1			0x310
+
+#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
index 3a0512c3e07a..63b3cbfcb50f 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
@@ -24,6 +24,7 @@
 #include "phy-qcom-qmp-qserdes-com-v6.h"
 #include "phy-qcom-qmp-qserdes-txrx-v6.h"
 #include "phy-qcom-qmp-qserdes-txrx-v6_20.h"
+#include "phy-qcom-qmp-qserdes-txrx-v6_n4.h"
 #include "phy-qcom-qmp-qserdes-ln-shrd-v6.h"
 
 #include "phy-qcom-qmp-qserdes-com-v7.h"

-- 
2.34.1

[PATCH 7/7] phy: qcom-qmp: qserdes-txrx: Add v7 register offsets

[Abel Vesa]

The X1E80100 platform bumps the HW version of QMP phy to v7 for USB and PCIE.
Add the new qserdes TX RX offsets in a dedicated header file.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
---
 .../phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v7.h    | 78 ++++++++++++++++++++++
 drivers/phy/qualcomm/phy-qcom-qmp.h                |  1 +
 2 files changed, 79 insertions(+)

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v7.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v7.h
new file mode 100644
index 000000000000..14023f47a95c
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v7.h
@@ -0,0 +1,78 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2023, Linaro Limited
+ */
+
+#ifndef QCOM_PHY_QMP_QSERDES_TXRX_USB_V7_H_
+#define QCOM_PHY_QMP_QSERDES_TXRX_USB_V7_H_
+
+#define QSERDES_V7_TX_CLKBUF_ENABLE				0x08
+#define QSERDES_V7_TX_RESET_TSYNC_EN				0x1c
+#define QSERDES_V7_TX_PRE_STALL_LDO_BOOST_EN			0x20
+#define QSERDES_V7_TX_TX_BAND					0x24
+#define QSERDES_V7_TX_INTERFACE_SELECT				0x2c
+#define QSERDES_V7_TX_RES_CODE_LANE_TX				0x34
+#define QSERDES_V7_TX_RES_CODE_LANE_RX				0x38
+#define QSERDES_V7_TX_RES_CODE_LANE_OFFSET_TX			0x3c
+#define QSERDES_V7_TX_RES_CODE_LANE_OFFSET_RX			0x40
+#define QSERDES_V7_TX_PARRATE_REC_DETECT_IDLE_EN		0x60
+#define QSERDES_V7_TX_BIST_PATTERN7				0x7c
+#define QSERDES_V7_TX_LANE_MODE_1				0x84
+#define QSERDES_V7_TX_LANE_MODE_2				0x88
+#define QSERDES_V7_TX_LANE_MODE_3				0x8c
+#define QSERDES_V7_TX_LANE_MODE_4				0x90
+#define QSERDES_V7_TX_LANE_MODE_5				0x94
+#define QSERDES_V7_TX_RCV_DETECT_LVL_2				0xa4
+#define QSERDES_V7_TX_TRAN_DRVR_EMP_EN				0xc0
+#define QSERDES_V7_TX_TX_INTERFACE_MODE				0xc4
+#define QSERDES_V7_TX_VMODE_CTRL1				0xc8
+#define QSERDES_V7_TX_PI_QEC_CTRL				0xe4
+
+#define QSERDES_V7_RX_UCDR_FO_GAIN				0x08
+#define QSERDES_V7_RX_UCDR_SO_GAIN				0x14
+#define QSERDES_V7_RX_UCDR_FASTLOCK_FO_GAIN			0x30
+#define QSERDES_V7_RX_UCDR_SO_SATURATION_AND_ENABLE		0x34
+#define QSERDES_V7_RX_UCDR_FASTLOCK_COUNT_LOW			0x3c
+#define QSERDES_V7_RX_UCDR_FASTLOCK_COUNT_HIGH			0x40
+#define QSERDES_V7_RX_UCDR_PI_CONTROLS				0x44
+#define QSERDES_V7_RX_UCDR_SB2_THRESH1				0x4c
+#define QSERDES_V7_RX_UCDR_SB2_THRESH2				0x50
+#define QSERDES_V7_RX_UCDR_SB2_GAIN1				0x54
+#define QSERDES_V7_RX_UCDR_SB2_GAIN2				0x58
+#define QSERDES_V7_RX_AUX_DATA_TCOARSE_TFINE			0x60
+#define QSERDES_V7_RX_TX_ADAPT_POST_THRESH			0xcc
+#define QSERDES_V7_RX_VGA_CAL_CNTRL1				0xd4
+#define QSERDES_V7_RX_VGA_CAL_CNTRL2				0xd8
+#define QSERDES_V7_RX_GM_CAL					0xdc
+#define QSERDES_V7_RX_RX_EQU_ADAPTOR_CNTRL2			0xec
+#define QSERDES_V7_RX_RX_EQU_ADAPTOR_CNTRL3			0xf0
+#define QSERDES_V7_RX_RX_EQU_ADAPTOR_CNTRL4			0xf4
+#define QSERDES_V7_RX_RX_IDAC_TSETTLE_LOW			0xf8
+#define QSERDES_V7_RX_RX_IDAC_TSETTLE_HIGH			0xfc
+#define QSERDES_V7_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1		0x110
+#define QSERDES_V7_RX_SIDGET_ENABLES				0x118
+#define QSERDES_V7_RX_SIGDET_CNTRL				0x11c
+#define QSERDES_V7_RX_SIGDET_DEGLITCH_CNTRL			0x124
+#define QSERDES_V7_RX_RX_MODE_00_LOW				0x15c
+#define QSERDES_V7_RX_RX_MODE_00_HIGH				0x160
+#define QSERDES_V7_RX_RX_MODE_00_HIGH2				0x164
+#define QSERDES_V7_RX_RX_MODE_00_HIGH3				0x168
+#define QSERDES_V7_RX_RX_MODE_00_HIGH4				0x16c
+#define QSERDES_V7_RX_RX_MODE_01_LOW				0x170
+#define QSERDES_V7_RX_RX_MODE_01_HIGH				0x174
+#define QSERDES_V7_RX_RX_MODE_01_HIGH2				0x178
+#define QSERDES_V7_RX_RX_MODE_01_HIGH3				0x17c
+#define QSERDES_V7_RX_RX_MODE_01_HIGH4				0x180
+#define QSERDES_V7_RX_RX_MODE_10_LOW				0x184
+#define QSERDES_V7_RX_RX_MODE_10_HIGH				0x188
+#define QSERDES_V7_RX_RX_MODE_10_HIGH2				0x18c
+#define QSERDES_V7_RX_RX_MODE_10_HIGH3				0x190
+#define QSERDES_V7_RX_RX_MODE_10_HIGH4				0x194
+#define QSERDES_V7_RX_DFE_EN_TIMER				0x1a0
+#define QSERDES_V7_RX_DFE_CTLE_POST_CAL_OFFSET			0x1a4
+#define QSERDES_V7_RX_DCC_CTRL1					0x1a8
+#define QSERDES_V7_RX_VTH_CODE					0x1b0
+#define QSERDES_V7_RX_SIGDET_CAL_CTRL1				0x1e4
+#define QSERDES_V7_RX_SIGDET_CAL_TRIM				0x1f8
+
+#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
index 63b3cbfcb50f..6923496cbfee 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
@@ -28,6 +28,7 @@
 #include "phy-qcom-qmp-qserdes-ln-shrd-v6.h"
 
 #include "phy-qcom-qmp-qserdes-com-v7.h"
+#include "phy-qcom-qmp-qserdes-txrx-v7.h"
 
 #include "phy-qcom-qmp-qserdes-pll.h"
 

-- 
2.34.1

Re: [PATCH 1/7] phy: qcom-qmp: qserdes-com: Add some more v6 register offsets

[Dmitry Baryshkov]

On Wed, 22 Nov 2023 at 12:04, Abel Vesa <abel.vesa@linaro.org> wrote:
>
> Add some missing V6 registers offsets that are needed by the new
> Snapdragon X Elite (X1E80100) platform.
>
> Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
> ---
>  drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h  | 5 +++++
>  drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6.h | 1 +
>  2 files changed, 6 insertions(+)

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

--
With best wishes
Dmitry

Re: [PATCH 2/7] phy: qcom-qmp: qserdes-txrx: Add some more v6.20 register offsets

[Dmitry Baryshkov]

On Wed, 22 Nov 2023 at 12:04, Abel Vesa <abel.vesa@linaro.org> wrote:
>
> Add some missing v6.20 registers offsets that are needed by the new
> Snapdragon X Elite (X1E80100) platform.
>
> Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
> ---
>  drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_20.h | 4 ++++
>  1 file changed, 4 insertions(+)

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

-- 
With best wishes
Dmitry

Re: [PATCH 2/7] phy: qcom-qmp: qserdes-txrx: Add some more v6.20 register offsets

[Dmitry Baryshkov]

On Wed, 22 Nov 2023 at 12:04, Abel Vesa <abel.vesa@linaro.org> wrote:
>
> Add some missing v6.20 registers offsets that are needed by the new
> Snapdragon X Elite (X1E80100) platform.
>
> Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
> ---
>  drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_20.h | 4 ++++
>  1 file changed, 4 insertions(+)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_20.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_20.h
> index 5385a8b60970..7402a94d1be8 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_20.h
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_20.h
> @@ -14,11 +14,14 @@
>  #define QSERDES_V6_20_TX_LANE_MODE_3                           0x80
>
>  #define QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2                   0x08
> +#define QSERDES_V6_20_RX_UCDR_SO_GAIN_RATE_2                   0x18
>  #define QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3                   0x0c

As a side note, this should be probably 0x1c. Could you please verify
it and send a fix?

>  #define QSERDES_V6_20_RX_UCDR_PI_CONTROLS                      0x20
>  #define QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3         0x34
>  #define QSERDES_V6_20_RX_IVCM_CAL_CTRL2                                0x9c
>  #define QSERDES_V6_20_RX_IVCM_POSTCAL_OFFSET                   0xa0
> +#define QSERDES_V6_20_RX_DFE_1                                 0xac
> +#define QSERDES_V6_20_RX_DFE_2                                 0xb0
>  #define QSERDES_V6_20_RX_DFE_3                                 0xb4
>  #define QSERDES_V6_20_RX_VGA_CAL_MAN_VAL                       0xe8
>  #define QSERDES_V6_20_RX_GM_CAL                                        0x10c
> @@ -41,5 +44,6 @@
>  #define QSERDES_V6_20_RX_MODE_RATE3_B4                         0x220
>  #define QSERDES_V6_20_RX_MODE_RATE3_B5                         0x224
>  #define QSERDES_V6_20_RX_MODE_RATE3_B6                         0x228
> +#define QSERDES_V6_20_RX_BKUP_CTRL1                            0x22c
>
>  #endif
>
> --
> 2.34.1
>
>


-- 
With best wishes
Dmitry

Re: [PATCH 3/7] phy: qcom-qmp: pcs: Add v7 register offsets

[Dmitry Baryshkov]

On Wed, 22 Nov 2023 at 12:04, Abel Vesa <abel.vesa@linaro.org> wrote:
>
> The X1E80100 platform bumps the HW version of QMP phy to v7 for USB,
> and PCIe. Add the new PCS offsets in a dedicated header file.
>
> Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
> ---
>  drivers/phy/qualcomm/phy-qcom-qmp-pcs-v7.h | 28 ++++++++++++++++++++++++++++
>  drivers/phy/qualcomm/phy-qcom-qmp.h        |  2 ++
>  2 files changed, 30 insertions(+)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v7.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v7.h
> new file mode 100644
> index 000000000000..520f28d802f6
> --- /dev/null
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v7.h
> @@ -0,0 +1,28 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (c) 2023, Linaro Limited
> + */
> +
> +#ifndef QCOM_PHY_QMP_PCS_V7_H_
> +#define QCOM_PHY_QMP_PCS_V7_H_
> +
> +/* Only for QMP V6 PHY - USB/PCIe PCS registers */

V7

> +
> +#define QPHY_V7_PCS_LOCK_DETECT_CONFIG1                        0xc4
> +#define QPHY_V7_PCS_LOCK_DETECT_CONFIG2                        0xc8
> +#define QPHY_V7_PCS_LOCK_DETECT_CONFIG3                        0xcc
> +#define QPHY_V7_PCS_LOCK_DETECT_CONFIG6                        0xd8
> +#define QPHY_V7_PCS_REFGEN_REQ_CONFIG1                 0xdc
> +#define QPHY_V7_PCS_RX_SIGDET_LVL                      0x188
> +#define QPHY_V7_PCS_RCVR_DTCT_DLY_P1U2_L               0x190
> +#define QPHY_V7_PCS_RCVR_DTCT_DLY_P1U2_H               0x194
> +#define QPHY_V7_PCS_RATE_SLEW_CNTRL1                   0x198
> +#define QPHY_V7_PCS_RX_CONFIG                          0x1b0
> +#define QPHY_V7_PCS_ALIGN_DETECT_CONFIG1               0x1c0
> +#define QPHY_V7_PCS_ALIGN_DETECT_CONFIG2               0x1c4
> +#define QPHY_V7_PCS_PCS_TX_RX_CONFIG                   0x1d0
> +#define QPHY_V7_PCS_EQ_CONFIG1                         0x1dc
> +#define QPHY_V7_PCS_EQ_CONFIG2                         0x1e0
> +#define QPHY_V7_PCS_EQ_CONFIG5                         0x1ec
> +
> +#endif
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
> index 71f063f4a56e..21f6a56e7ae3 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp.h
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
> @@ -44,6 +44,8 @@
>
>  #include "phy-qcom-qmp-pcs-v6_20.h"
>
> +#include "phy-qcom-qmp-pcs-v7.h"
> +
>  /* Only for QMP V3 & V4 PHY - DP COM registers */
>  #define QPHY_V3_DP_COM_PHY_MODE_CTRL                   0x00
>  #define QPHY_V3_DP_COM_SW_RESET                                0x04
>
> --
> 2.34.1
>
>


-- 
With best wishes
Dmitry

Re: [PATCH 4/7] phy: qcom-qmp: pcs-usb: Add v7 register offsets

[Dmitry Baryshkov]

On Wed, 22 Nov 2023 at 12:04, Abel Vesa <abel.vesa@linaro.org> wrote:
>
> The X1E80100 platform bumps the HW version of QMP phy to v7 for USB.
> Add the new PCS USB specific offsets in a dedicated header file.
>
> Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
> ---
>  drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v7.h | 31 ++++++++++++++++++++++++++
>  1 file changed, 31 insertions(+)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v7.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v7.h
> new file mode 100644
> index 000000000000..dbb75964cef7
> --- /dev/null
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v7.h
> @@ -0,0 +1,31 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (c) 2023, Linaro Limited
> + */
> +
> +#ifndef QCOM_PHY_QMP_PCS_USB_V7_H_
> +#define QCOM_PHY_QMP_PCS_USB_V7_H_
> +
> +/* Only for QMP V6 PHY - USB3 have different offsets than V5 */

V7

> +#define QPHY_USB_V7_PCS_LOCK_DETECT_CONFIG1            0xc4
> +#define QPHY_USB_V7_PCS_LOCK_DETECT_CONFIG2            0xc8
> +#define QPHY_USB_V7_PCS_LOCK_DETECT_CONFIG3            0xcc
> +#define QPHY_USB_V7_PCS_LOCK_DETECT_CONFIG6            0xd8
> +#define QPHY_USB_V7_PCS_REFGEN_REQ_CONFIG1             0xdc
> +#define QPHY_USB_V7_PCS_USB3_POWER_STATE_CONFIG1       0x90
> +#define QPHY_USB_V7_PCS_RX_SIGDET_LVL                  0x188
> +#define QPHY_USB_V7_PCS_RCVR_DTCT_DLY_P1U2_L           0x190
> +#define QPHY_USB_V7_PCS_RCVR_DTCT_DLY_P1U2_H           0x194
> +#define QPHY_USB_V7_PCS_CDR_RESET_TIME                 0x1b0
> +#define QPHY_USB_V7_PCS_ALIGN_DETECT_CONFIG1           0x1c0
> +#define QPHY_USB_V7_PCS_ALIGN_DETECT_CONFIG2           0x1c4
> +#define QPHY_USB_V7_PCS_PCS_TX_RX_CONFIG               0x1d0
> +#define QPHY_USB_V7_PCS_EQ_CONFIG1                     0x1dc
> +#define QPHY_USB_V7_PCS_EQ_CONFIG5                     0x1ec

Some (most) of these registers do not belong here, they are the same
as the generic PCS register names. Please drop them.

> +
> +#define QPHY_USB_V7_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL   0x18
> +#define QPHY_USB_V7_PCS_USB3_RXEQTRAINING_DFE_TIME_S2  0x3c
> +#define QPHY_USB_V7_PCS_USB3_RCVR_DTCT_DLY_U3_L                0x40
> +#define QPHY_USB_V7_PCS_USB3_RCVR_DTCT_DLY_U3_H                0x44

Drop the _USB_ part, please, there is already PCS_USB3 prefix.

> +
> +#endif
>
> --
> 2.34.1
>
>


-- 
With best wishes
Dmitry

Re: [PATCH 5/7] phy: qcom-qmp: qserdes-com: Add v7 register offsets

[Dmitry Baryshkov]

On Wed, 22 Nov 2023 at 12:04, Abel Vesa <abel.vesa@linaro.org> wrote:
>
> The X1E80100 platform bumps the HW version of QMP phy to v7 for USB
> and PCIE g3x2. Add the new qserdes com offsets in a dedicated
> header file.
>
> Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
> ---
>  drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v7.h | 86 ++++++++++++++++++++++
>  drivers/phy/qualcomm/phy-qcom-qmp.h                |  2 +
>  2 files changed, 88 insertions(+)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v7.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v7.h
> new file mode 100644
> index 000000000000..c8775ca1ab6b
> --- /dev/null
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v7.h
> @@ -0,0 +1,86 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (c) 2023, Linaro Limited
> + */
> +
> +#ifndef QCOM_PHY_QMP_QSERDES_COM_V7_H_
> +#define QCOM_PHY_QMP_QSERDES_COM_V7_H_
> +
> +/* Only for QMP V6 PHY - QSERDES COM registers */

V7

> +
> +#define QSERDES_V7_COM_SSC_STEP_SIZE1_MODE1                    0x00
> +#define QSERDES_V7_COM_SSC_STEP_SIZE2_MODE1                    0x04
> +#define QSERDES_V7_COM_CP_CTRL_MODE1                           0x10
> +#define QSERDES_V7_COM_PLL_RCTRL_MODE1                         0x14
> +#define QSERDES_V7_COM_PLL_CCTRL_MODE1                         0x18
> +#define QSERDES_V7_COM_CORECLK_DIV_MODE1                       0x1c
> +#define QSERDES_V7_COM_LOCK_CMP1_MODE1                         0x20
> +#define QSERDES_V7_COM_LOCK_CMP2_MODE1                         0x24
> +#define QSERDES_V7_COM_DEC_START_MODE1                         0x28
> +#define QSERDES_V7_COM_DEC_START_MSB_MODE1                     0x2c
> +#define QSERDES_V7_COM_DIV_FRAC_START1_MODE1                   0x30
> +#define QSERDES_V7_COM_DIV_FRAC_START2_MODE1                   0x34
> +#define QSERDES_V7_COM_DIV_FRAC_START3_MODE1                   0x38
> +#define QSERDES_V7_COM_HSCLK_SEL_1                             0x3c
> +#define QSERDES_V7_COM_INTEGLOOP_GAIN0_MODE1                   0x40
> +#define QSERDES_V7_COM_INTEGLOOP_GAIN1_MODE1                   0x44
> +#define QSERDES_V7_COM_VCO_TUNE1_MODE1                         0x48
> +#define QSERDES_V7_COM_VCO_TUNE2_MODE1                         0x4c
> +#define QSERDES_V7_COM_BIN_VCOCAL_CMP_CODE1_MODE1              0x50
> +#define QSERDES_V7_COM_BIN_VCOCAL_CMP_CODE2_MODE1              0x54
> +#define QSERDES_V7_COM_BIN_VCOCAL_CMP_CODE1_MODE0              0x58
> +#define QSERDES_V7_COM_BIN_VCOCAL_CMP_CODE2_MODE0              0x5c
> +#define QSERDES_V7_COM_SSC_STEP_SIZE1_MODE0                    0x60
> +#define QSERDES_V7_COM_SSC_STEP_SIZE2_MODE0                    0x64
> +#define QSERDES_V7_COM_CP_CTRL_MODE0                           0x70
> +#define QSERDES_V7_COM_PLL_RCTRL_MODE0                         0x74
> +#define QSERDES_V7_COM_PLL_CCTRL_MODE0                         0x78
> +#define QSERDES_V7_COM_PLL_CORE_CLK_DIV_MODE0                  0x7c
> +#define QSERDES_V7_COM_LOCK_CMP1_MODE0                         0x80
> +#define QSERDES_V7_COM_LOCK_CMP2_MODE0                         0x84
> +#define QSERDES_V7_COM_DEC_START_MODE0                         0x88
> +#define QSERDES_V7_COM_DEC_START_MSB_MODE0                     0x8c
> +#define QSERDES_V7_COM_DIV_FRAC_START1_MODE0                   0x90
> +#define QSERDES_V7_COM_DIV_FRAC_START2_MODE0                   0x94
> +#define QSERDES_V7_COM_DIV_FRAC_START3_MODE0                   0x98
> +#define QSERDES_V7_COM_HSCLK_HS_SWITCH_SEL_1                   0x9c
> +#define QSERDES_V7_COM_INTEGLOOP_GAIN0_MODE0                   0xa0
> +#define QSERDES_V7_COM_INTEGLOOP_GAIN1_MODE0                   0xa4
> +#define QSERDES_V7_COM_VCO_TUNE1_MODE0                         0xa8
> +#define QSERDES_V7_COM_VCO_TUNE2_MODE0                         0xac
> +#define QSERDES_V7_COM_BG_TIMER                                        0xbc
> +#define QSERDES_V7_COM_SSC_EN_CENTER                           0xc0
> +#define QSERDES_V7_COM_SSC_PER1                                        0xcc
> +#define QSERDES_V7_COM_SSC_PER2                                        0xd0
> +#define QSERDES_V7_COM_PLL_POST_DIV_MUX                                0xd8
> +#define QSERDES_V7_COM_PLL_BIAS_EN_CLK_BUFLR_EN                        0xdc
> +#define QSERDES_V7_COM_CLK_ENABLE1                             0xe0
> +#define QSERDES_V7_COM_SYS_CLK_CTRL                            0xe4
> +#define QSERDES_V7_COM_SYSCLK_BUF_ENABLE                       0xe8
> +#define QSERDES_V7_COM_PLL_IVCO                                        0xf4
> +#define QSERDES_V7_COM_PLL_IVCO_MODE1                          0xf8
> +#define QSERDES_V7_COM_SYSCLK_EN_SEL                           0x110
> +#define QSERDES_V7_COM_RESETSM_CNTRL                           0x118
> +#define QSERDES_V7_COM_LOCK_CMP_EN                             0x120
> +#define QSERDES_V7_COM_LOCK_CMP_CFG                            0x124
> +#define QSERDES_V7_COM_VCO_TUNE_CTRL                           0x13c
> +#define QSERDES_V7_COM_VCO_TUNE_MAP                            0x140
> +#define QSERDES_V7_COM_VCO_TUNE_INITVAL2                       0x148
> +#define QSERDES_V7_COM_VCO_TUNE_MAXVAL2                                0x158
> +#define QSERDES_V7_COM_CLK_SELECT                              0x164
> +#define QSERDES_V7_COM_CORE_CLK_EN                             0x170
> +#define QSERDES_V7_COM_CMN_CONFIG_1                            0x174
> +#define QSERDES_V7_COM_SVS_MODE_CLK_SEL                                0x17c
> +#define QSERDES_V7_COM_CMN_MISC_1                              0x184
> +#define QSERDES_V7_COM_CMN_MODE                                        0x188
> +#define QSERDES_V7_COM_PLL_VCO_DC_LEVEL_CTRL                   0x198
> +#define QSERDES_V7_COM_AUTO_GAIN_ADJ_CTRL_1                    0x1a4
> +#define QSERDES_V7_COM_AUTO_GAIN_ADJ_CTRL_2                    0x1a8
> +#define QSERDES_V7_COM_AUTO_GAIN_ADJ_CTRL_3                    0x1ac
> +#define QSERDES_V7_COM_ADDITIONAL_MISC                         0x1b4
> +#define QSERDES_V7_COM_ADDITIONAL_MISC_2                       0x1b8
> +#define QSERDES_V7_COM_ADDITIONAL_MISC_3                       0x1bc
> +#define QSERDES_V7_COM_CMN_STATUS                              0x1d0
> +#define QSERDES_V7_COM_C_READY_STATUS                          0x1f8
> +
> +#endif
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
> index 21f6a56e7ae3..3a0512c3e07a 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp.h
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
> @@ -26,6 +26,8 @@
>  #include "phy-qcom-qmp-qserdes-txrx-v6_20.h"
>  #include "phy-qcom-qmp-qserdes-ln-shrd-v6.h"
>
> +#include "phy-qcom-qmp-qserdes-com-v7.h"
> +
>  #include "phy-qcom-qmp-qserdes-pll.h"
>
>  #include "phy-qcom-qmp-pcs-v2.h"
>
> --
> 2.34.1
>
>


-- 
With best wishes
Dmitry

Re: [PATCH 7/7] phy: qcom-qmp: qserdes-txrx: Add v7 register offsets

[Dmitry Baryshkov]

On Wed, 22 Nov 2023 at 12:04, Abel Vesa <abel.vesa@linaro.org> wrote:
>
> The X1E80100 platform bumps the HW version of QMP phy to v7 for USB and PCIE.
> Add the new qserdes TX RX offsets in a dedicated header file.
>
> Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
> ---
>  .../phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v7.h    | 78 ++++++++++++++++++++++
>  drivers/phy/qualcomm/phy-qcom-qmp.h                |  1 +
>  2 files changed, 79 insertions(+)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v7.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v7.h
> new file mode 100644
> index 000000000000..14023f47a95c
> --- /dev/null
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v7.h
> @@ -0,0 +1,78 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (c) 2023, Linaro Limited
> + */
> +
> +#ifndef QCOM_PHY_QMP_QSERDES_TXRX_USB_V7_H_
> +#define QCOM_PHY_QMP_QSERDES_TXRX_USB_V7_H_

s/_USB//

> +
> +#define QSERDES_V7_TX_CLKBUF_ENABLE                            0x08
> +#define QSERDES_V7_TX_RESET_TSYNC_EN                           0x1c
> +#define QSERDES_V7_TX_PRE_STALL_LDO_BOOST_EN                   0x20
> +#define QSERDES_V7_TX_TX_BAND                                  0x24
> +#define QSERDES_V7_TX_INTERFACE_SELECT                         0x2c
> +#define QSERDES_V7_TX_RES_CODE_LANE_TX                         0x34
> +#define QSERDES_V7_TX_RES_CODE_LANE_RX                         0x38
> +#define QSERDES_V7_TX_RES_CODE_LANE_OFFSET_TX                  0x3c
> +#define QSERDES_V7_TX_RES_CODE_LANE_OFFSET_RX                  0x40
> +#define QSERDES_V7_TX_PARRATE_REC_DETECT_IDLE_EN               0x60
> +#define QSERDES_V7_TX_BIST_PATTERN7                            0x7c
> +#define QSERDES_V7_TX_LANE_MODE_1                              0x84
> +#define QSERDES_V7_TX_LANE_MODE_2                              0x88
> +#define QSERDES_V7_TX_LANE_MODE_3                              0x8c
> +#define QSERDES_V7_TX_LANE_MODE_4                              0x90
> +#define QSERDES_V7_TX_LANE_MODE_5                              0x94
> +#define QSERDES_V7_TX_RCV_DETECT_LVL_2                         0xa4
> +#define QSERDES_V7_TX_TRAN_DRVR_EMP_EN                         0xc0
> +#define QSERDES_V7_TX_TX_INTERFACE_MODE                                0xc4
> +#define QSERDES_V7_TX_VMODE_CTRL1                              0xc8
> +#define QSERDES_V7_TX_PI_QEC_CTRL                              0xe4
> +
> +#define QSERDES_V7_RX_UCDR_FO_GAIN                             0x08
> +#define QSERDES_V7_RX_UCDR_SO_GAIN                             0x14
> +#define QSERDES_V7_RX_UCDR_FASTLOCK_FO_GAIN                    0x30
> +#define QSERDES_V7_RX_UCDR_SO_SATURATION_AND_ENABLE            0x34
> +#define QSERDES_V7_RX_UCDR_FASTLOCK_COUNT_LOW                  0x3c
> +#define QSERDES_V7_RX_UCDR_FASTLOCK_COUNT_HIGH                 0x40
> +#define QSERDES_V7_RX_UCDR_PI_CONTROLS                         0x44
> +#define QSERDES_V7_RX_UCDR_SB2_THRESH1                         0x4c
> +#define QSERDES_V7_RX_UCDR_SB2_THRESH2                         0x50
> +#define QSERDES_V7_RX_UCDR_SB2_GAIN1                           0x54
> +#define QSERDES_V7_RX_UCDR_SB2_GAIN2                           0x58
> +#define QSERDES_V7_RX_AUX_DATA_TCOARSE_TFINE                   0x60
> +#define QSERDES_V7_RX_TX_ADAPT_POST_THRESH                     0xcc
> +#define QSERDES_V7_RX_VGA_CAL_CNTRL1                           0xd4
> +#define QSERDES_V7_RX_VGA_CAL_CNTRL2                           0xd8
> +#define QSERDES_V7_RX_GM_CAL                                   0xdc
> +#define QSERDES_V7_RX_RX_EQU_ADAPTOR_CNTRL2                    0xec
> +#define QSERDES_V7_RX_RX_EQU_ADAPTOR_CNTRL3                    0xf0
> +#define QSERDES_V7_RX_RX_EQU_ADAPTOR_CNTRL4                    0xf4
> +#define QSERDES_V7_RX_RX_IDAC_TSETTLE_LOW                      0xf8
> +#define QSERDES_V7_RX_RX_IDAC_TSETTLE_HIGH                     0xfc
> +#define QSERDES_V7_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1              0x110
> +#define QSERDES_V7_RX_SIDGET_ENABLES                           0x118
> +#define QSERDES_V7_RX_SIGDET_CNTRL                             0x11c
> +#define QSERDES_V7_RX_SIGDET_DEGLITCH_CNTRL                    0x124
> +#define QSERDES_V7_RX_RX_MODE_00_LOW                           0x15c
> +#define QSERDES_V7_RX_RX_MODE_00_HIGH                          0x160
> +#define QSERDES_V7_RX_RX_MODE_00_HIGH2                         0x164
> +#define QSERDES_V7_RX_RX_MODE_00_HIGH3                         0x168
> +#define QSERDES_V7_RX_RX_MODE_00_HIGH4                         0x16c
> +#define QSERDES_V7_RX_RX_MODE_01_LOW                           0x170
> +#define QSERDES_V7_RX_RX_MODE_01_HIGH                          0x174
> +#define QSERDES_V7_RX_RX_MODE_01_HIGH2                         0x178
> +#define QSERDES_V7_RX_RX_MODE_01_HIGH3                         0x17c
> +#define QSERDES_V7_RX_RX_MODE_01_HIGH4                         0x180
> +#define QSERDES_V7_RX_RX_MODE_10_LOW                           0x184
> +#define QSERDES_V7_RX_RX_MODE_10_HIGH                          0x188
> +#define QSERDES_V7_RX_RX_MODE_10_HIGH2                         0x18c
> +#define QSERDES_V7_RX_RX_MODE_10_HIGH3                         0x190
> +#define QSERDES_V7_RX_RX_MODE_10_HIGH4                         0x194
> +#define QSERDES_V7_RX_DFE_EN_TIMER                             0x1a0
> +#define QSERDES_V7_RX_DFE_CTLE_POST_CAL_OFFSET                 0x1a4
> +#define QSERDES_V7_RX_DCC_CTRL1                                        0x1a8
> +#define QSERDES_V7_RX_VTH_CODE                                 0x1b0
> +#define QSERDES_V7_RX_SIGDET_CAL_CTRL1                         0x1e4
> +#define QSERDES_V7_RX_SIGDET_CAL_TRIM                          0x1f8
> +
> +#endif
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
> index 63b3cbfcb50f..6923496cbfee 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp.h
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
> @@ -28,6 +28,7 @@
>  #include "phy-qcom-qmp-qserdes-ln-shrd-v6.h"
>
>  #include "phy-qcom-qmp-qserdes-com-v7.h"
> +#include "phy-qcom-qmp-qserdes-txrx-v7.h"
>
>  #include "phy-qcom-qmp-qserdes-pll.h"
>
>
> --
> 2.34.1
>
>


-- 
With best wishes
Dmitry

Re: [PATCH 6/7] phy: qcom-qmp: qserdes-txrx: Add V6 N4 register offsets

[Dmitry Baryshkov]

On Wed, 22 Nov 2023 at 12:04, Abel Vesa <abel.vesa@linaro.org> wrote:
>
> There is a variant of V6 offsets that are different, the QMP PHY N4,
> and it is found on the X1E80100 platform.
>
> Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
> ---
>  .../phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_n4.h | 51 ++++++++++++++++++++++
>  drivers/phy/qualcomm/phy-qcom-qmp.h                |  1 +
>  2 files changed, 52 insertions(+)

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>


-- 
With best wishes
Dmitry

Re: [PATCH 2/7] phy: qcom-qmp: qserdes-txrx: Add some more v6.20 register offsets

[Abel Vesa]

On 23-11-22 12:12:00, Dmitry Baryshkov wrote:
> On Wed, 22 Nov 2023 at 12:04, Abel Vesa <abel.vesa@linaro.org> wrote:
> >
> > Add some missing v6.20 registers offsets that are needed by the new
> > Snapdragon X Elite (X1E80100) platform.
> >
> > Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
> > ---
> >  drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_20.h | 4 ++++
> >  1 file changed, 4 insertions(+)
> >
> > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_20.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_20.h
> > index 5385a8b60970..7402a94d1be8 100644
> > --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_20.h
> > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_20.h
> > @@ -14,11 +14,14 @@
> >  #define QSERDES_V6_20_TX_LANE_MODE_3                           0x80
> >
> >  #define QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2                   0x08
> > +#define QSERDES_V6_20_RX_UCDR_SO_GAIN_RATE_2                   0x18
> >  #define QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3                   0x0c
> 
> As a side note, this should be probably 0x1c. Could you please verify
> it and send a fix?
> 

Double checked. The values are correct. So I'll just put the
SO_GAIN_RATE_2 below FO_GAIN_RATE_3.

> >  #define QSERDES_V6_20_RX_UCDR_PI_CONTROLS                      0x20
> >  #define QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3         0x34
> >  #define QSERDES_V6_20_RX_IVCM_CAL_CTRL2                                0x9c
> >  #define QSERDES_V6_20_RX_IVCM_POSTCAL_OFFSET                   0xa0
> > +#define QSERDES_V6_20_RX_DFE_1                                 0xac
> > +#define QSERDES_V6_20_RX_DFE_2                                 0xb0
> >  #define QSERDES_V6_20_RX_DFE_3                                 0xb4
> >  #define QSERDES_V6_20_RX_VGA_CAL_MAN_VAL                       0xe8
> >  #define QSERDES_V6_20_RX_GM_CAL                                        0x10c
> > @@ -41,5 +44,6 @@
> >  #define QSERDES_V6_20_RX_MODE_RATE3_B4                         0x220
> >  #define QSERDES_V6_20_RX_MODE_RATE3_B5                         0x224
> >  #define QSERDES_V6_20_RX_MODE_RATE3_B6                         0x228
> > +#define QSERDES_V6_20_RX_BKUP_CTRL1                            0x22c
> >
> >  #endif
> >
> > --
> > 2.34.1
> >
> >
> 
> 
> -- 
> With best wishes
> Dmitry

Re: [PATCH 2/7] phy: qcom-qmp: qserdes-txrx: Add some more v6.20 register offsets

[Dmitry Baryshkov]

On Mon, 4 Dec 2023 at 13:29, Abel Vesa <abel.vesa@linaro.org> wrote:
>
> On 23-11-22 12:12:00, Dmitry Baryshkov wrote:
> > On Wed, 22 Nov 2023 at 12:04, Abel Vesa <abel.vesa@linaro.org> wrote:
> > >
> > > Add some missing v6.20 registers offsets that are needed by the new
> > > Snapdragon X Elite (X1E80100) platform.
> > >
> > > Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
> > > ---
> > >  drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_20.h | 4 ++++
> > >  1 file changed, 4 insertions(+)
> > >
> > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_20.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_20.h
> > > index 5385a8b60970..7402a94d1be8 100644
> > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_20.h
> > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_20.h
> > > @@ -14,11 +14,14 @@
> > >  #define QSERDES_V6_20_TX_LANE_MODE_3                           0x80
> > >
> > >  #define QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2                   0x08
> > > +#define QSERDES_V6_20_RX_UCDR_SO_GAIN_RATE_2                   0x18
> > >  #define QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3                   0x0c
> >
> > As a side note, this should be probably 0x1c. Could you please verify
> > it and send a fix?
> >
>
> Double checked. The values are correct. So I'll just put the
> SO_GAIN_RATE_2 below FO_GAIN_RATE_3.

SGTM

>
> > >  #define QSERDES_V6_20_RX_UCDR_PI_CONTROLS                      0x20
> > >  #define QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3         0x34
> > >  #define QSERDES_V6_20_RX_IVCM_CAL_CTRL2                                0x9c
> > >  #define QSERDES_V6_20_RX_IVCM_POSTCAL_OFFSET                   0xa0
> > > +#define QSERDES_V6_20_RX_DFE_1                                 0xac
> > > +#define QSERDES_V6_20_RX_DFE_2                                 0xb0
> > >  #define QSERDES_V6_20_RX_DFE_3                                 0xb4
> > >  #define QSERDES_V6_20_RX_VGA_CAL_MAN_VAL                       0xe8
> > >  #define QSERDES_V6_20_RX_GM_CAL                                        0x10c
> > > @@ -41,5 +44,6 @@
> > >  #define QSERDES_V6_20_RX_MODE_RATE3_B4                         0x220
> > >  #define QSERDES_V6_20_RX_MODE_RATE3_B5                         0x224
> > >  #define QSERDES_V6_20_RX_MODE_RATE3_B6                         0x228
> > > +#define QSERDES_V6_20_RX_BKUP_CTRL1                            0x22c
> > >
> > >  #endif
> > >
> > > --
> > > 2.34.1
> > >
> > >
> >
> >
> > --
> > With best wishes
> > Dmitry



-- 
With best wishes
Dmitry