* [PATCH 2/7] clk: qcom: gcc-ipq9574: Add PCIe pipe clocks
2024-04-02 19:25 [PATCH 1/7] dt-bindings: clock: Add PCIe pipe related clocks for IPQ9574 Alexandru Gagniuc
@ 2024-04-02 19:25 ` Alexandru Gagniuc
2024-04-02 19:25 ` [PATCH 3/7] dt-bindings: PCI: qcom: Add IPQ9574 PCIe controller Alexandru Gagniuc
` (5 subsequent siblings)
6 siblings, 0 replies; 18+ messages in thread
From: Alexandru Gagniuc @ 2024-04-02 19:25 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Michael Turquette, Stephen Boyd
Cc: ansuelsmth, robimarko, Alexandru Gagniuc, linux-arm-msm,
linux-clk, linux-kernel
The IPQ9574 has four PCIe "pipe" clocks. These clocks are required by
PCIe PHYs. Port the pipe clocks from the downstream kernel.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
---
drivers/clk/qcom/gcc-ipq9574.c | 76 ++++++++++++++++++++++++++++++++++
1 file changed, 76 insertions(+)
diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c
index 0a3f846695b8..c748d2f124f3 100644
--- a/drivers/clk/qcom/gcc-ipq9574.c
+++ b/drivers/clk/qcom/gcc-ipq9574.c
@@ -1569,6 +1569,24 @@ static struct clk_regmap_phy_mux pcie0_pipe_clk_src = {
},
};
+static struct clk_branch gcc_pcie0_pipe_clk = {
+ .halt_reg = 0x28044,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x28044,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_pcie0_pipe_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &pcie0_pipe_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
static struct clk_regmap_phy_mux pcie1_pipe_clk_src = {
.reg = 0x29064,
.clkr = {
@@ -1583,6 +1601,24 @@ static struct clk_regmap_phy_mux pcie1_pipe_clk_src = {
},
};
+static struct clk_branch gcc_pcie1_pipe_clk = {
+ .halt_reg = 0x29044,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x29044,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_pcie1_pipe_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &pcie1_pipe_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
static struct clk_regmap_phy_mux pcie2_pipe_clk_src = {
.reg = 0x2a064,
.clkr = {
@@ -1597,6 +1633,24 @@ static struct clk_regmap_phy_mux pcie2_pipe_clk_src = {
},
};
+static struct clk_branch gcc_pcie2_pipe_clk = {
+ .halt_reg = 0x2a044,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x2a044,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_pcie2_pipe_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &pcie2_pipe_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
static struct clk_regmap_phy_mux pcie3_pipe_clk_src = {
.reg = 0x2b064,
.clkr = {
@@ -1611,6 +1665,24 @@ static struct clk_regmap_phy_mux pcie3_pipe_clk_src = {
},
};
+static struct clk_branch gcc_pcie3_pipe_clk = {
+ .halt_reg = 0x2b044,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x2b044,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data) {
+ .name = "gcc_pcie3_pipe_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &pcie3_pipe_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
static const struct freq_tbl ftbl_pcie_rchng_clk_src[] = {
F(24000000, P_XO, 1, 0, 0),
F(100000000, P_GPLL0, 8, 0, 0),
@@ -4141,6 +4213,10 @@ static struct clk_regmap *gcc_ipq9574_clks[] = {
[GCC_SNOC_PCIE1_1LANE_S_CLK] = &gcc_snoc_pcie1_1lane_s_clk.clkr,
[GCC_SNOC_PCIE2_2LANE_S_CLK] = &gcc_snoc_pcie2_2lane_s_clk.clkr,
[GCC_SNOC_PCIE3_2LANE_S_CLK] = &gcc_snoc_pcie3_2lane_s_clk.clkr,
+ [GCC_PCIE0_PIPE_CLK] = &gcc_pcie0_pipe_clk.clkr,
+ [GCC_PCIE1_PIPE_CLK] = &gcc_pcie1_pipe_clk.clkr,
+ [GCC_PCIE2_PIPE_CLK] = &gcc_pcie2_pipe_clk.clkr,
+ [GCC_PCIE3_PIPE_CLK] = &gcc_pcie3_pipe_clk.clkr,
};
static const struct qcom_reset_map gcc_ipq9574_resets[] = {
--
2.40.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 3/7] dt-bindings: PCI: qcom: Add IPQ9574 PCIe controller
2024-04-02 19:25 [PATCH 1/7] dt-bindings: clock: Add PCIe pipe related clocks for IPQ9574 Alexandru Gagniuc
2024-04-02 19:25 ` [PATCH 2/7] clk: qcom: gcc-ipq9574: Add PCIe pipe clocks Alexandru Gagniuc
@ 2024-04-02 19:25 ` Alexandru Gagniuc
2024-04-03 7:14 ` Krzysztof Kozlowski
2024-04-02 19:25 ` [PATCH 4/7] PCI: qcom: Add support for IPQ9574 Alexandru Gagniuc
` (4 subsequent siblings)
6 siblings, 1 reply; 18+ messages in thread
From: Alexandru Gagniuc @ 2024-04-02 19:25 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Bjorn Helgaas, Lorenzo Pieralisi,
Krzysztof Wilczyński, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Manivannan Sadhasivam
Cc: ansuelsmth, robimarko, Alexandru Gagniuc, linux-arm-msm,
linux-pci, devicetree, linux-kernel
IPQ9574 has PCIe controllers which are almost identical to IPQ6018.
The only difference is that the "iface" clock is not required.
Document this difference along with the compatible string.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
---
.../devicetree/bindings/pci/qcom,pcie.yaml | 32 +++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
index cf9a6910b542..6eb29547c18e 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
@@ -26,6 +26,7 @@ properties:
- qcom,pcie-ipq8064-v2
- qcom,pcie-ipq8074
- qcom,pcie-ipq8074-gen3
+ - qcom,pcie-ipq9574
- qcom,pcie-msm8996
- qcom,pcie-qcs404
- qcom,pcie-sdm845
@@ -383,6 +384,35 @@ allOf:
- const: axi_s # AXI Slave clock
- const: axi_bridge # AXI bridge clock
- const: rchng
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,pcie-ipq9574
+ then:
+ properties:
+ clocks:
+ minItems: 4
+ maxItems: 4
+ clock-names:
+ items:
+ - const: axi_m # AXI Master clock
+ - const: axi_s # AXI Slave clock
+ - const: axi_bridge # AXI bridge clock
+ - const: rchng
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,pcie-ipq6018
+ - qcom,pcie-ipq8074-gen3
+ - qcom,pcie-ipq9574
+ then:
+ properties:
resets:
minItems: 8
maxItems: 8
@@ -507,6 +537,7 @@ allOf:
- qcom,pcie-ipq8064v2
- qcom,pcie-ipq8074
- qcom,pcie-ipq8074-gen3
+ - qcom,pcie-ipq9574
- qcom,pcie-qcs404
then:
required:
@@ -566,6 +597,7 @@ allOf:
- qcom,pcie-ipq8064-v2
- qcom,pcie-ipq8074
- qcom,pcie-ipq8074-gen3
+ - qcom,pcie-ipq9574
- qcom,pcie-qcs404
then:
properties:
--
2.40.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [PATCH 3/7] dt-bindings: PCI: qcom: Add IPQ9574 PCIe controller
2024-04-02 19:25 ` [PATCH 3/7] dt-bindings: PCI: qcom: Add IPQ9574 PCIe controller Alexandru Gagniuc
@ 2024-04-03 7:14 ` Krzysztof Kozlowski
2024-04-03 18:05 ` mr.nuke.me
0 siblings, 1 reply; 18+ messages in thread
From: Krzysztof Kozlowski @ 2024-04-03 7:14 UTC (permalink / raw)
To: Alexandru Gagniuc, Bjorn Andersson, Konrad Dybcio, Bjorn Helgaas,
Lorenzo Pieralisi, Krzysztof Wilczyński, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Manivannan Sadhasivam
Cc: ansuelsmth, robimarko, linux-arm-msm, linux-pci, devicetree,
linux-kernel
On 02/04/2024 21:25, Alexandru Gagniuc wrote:
> IPQ9574 has PCIe controllers which are almost identical to IPQ6018.
> The only difference is that the "iface" clock is not required.
> Document this difference along with the compatible string.
>
> Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
> ---
> .../devicetree/bindings/pci/qcom,pcie.yaml | 32 +++++++++++++++++++
> 1 file changed, 32 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> index cf9a6910b542..6eb29547c18e 100644
> --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> @@ -26,6 +26,7 @@ properties:
> - qcom,pcie-ipq8064-v2
> - qcom,pcie-ipq8074
> - qcom,pcie-ipq8074-gen3
> + - qcom,pcie-ipq9574
> - qcom,pcie-msm8996
> - qcom,pcie-qcs404
> - qcom,pcie-sdm845
> @@ -383,6 +384,35 @@ allOf:
> - const: axi_s # AXI Slave clock
> - const: axi_bridge # AXI bridge clock
> - const: rchng
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - qcom,pcie-ipq9574
> + then:
> + properties:
> + clocks:
> + minItems: 4
> + maxItems: 4
> + clock-names:
> + items:
> + - const: axi_m # AXI Master clock
> + - const: axi_s # AXI Slave clock
> + - const: axi_bridge # AXI bridge clock
> + - const: rchng
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - qcom,pcie-ipq6018
> + - qcom,pcie-ipq8074-gen3
> + - qcom,pcie-ipq9574
> + then:
Do not introduce inconsistent style. All if:then: define both clocks and
resets, right? And after your patch not anymore?
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 3/7] dt-bindings: PCI: qcom: Add IPQ9574 PCIe controller
2024-04-03 7:14 ` Krzysztof Kozlowski
@ 2024-04-03 18:05 ` mr.nuke.me
2024-04-04 6:18 ` Krzysztof Kozlowski
0 siblings, 1 reply; 18+ messages in thread
From: mr.nuke.me @ 2024-04-03 18:05 UTC (permalink / raw)
To: Krzysztof Kozlowski, Bjorn Andersson, Konrad Dybcio,
Bjorn Helgaas, Lorenzo Pieralisi, Krzysztof Wilczyński,
Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Manivannan Sadhasivam
Cc: ansuelsmth, robimarko, linux-arm-msm, linux-pci, devicetree,
linux-kernel
On 4/3/24 02:14, Krzysztof Kozlowski wrote:
> On 02/04/2024 21:25, Alexandru Gagniuc wrote:
>> IPQ9574 has PCIe controllers which are almost identical to IPQ6018.
>> The only difference is that the "iface" clock is not required.
>> Document this difference along with the compatible string.
>>
>> Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
>> ---
>> .../devicetree/bindings/pci/qcom,pcie.yaml | 32 +++++++++++++++++++
>> 1 file changed, 32 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
>> index cf9a6910b542..6eb29547c18e 100644
>> --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
>> +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
>> @@ -26,6 +26,7 @@ properties:
>> - qcom,pcie-ipq8064-v2
>> - qcom,pcie-ipq8074
>> - qcom,pcie-ipq8074-gen3
>> + - qcom,pcie-ipq9574
>> - qcom,pcie-msm8996
>> - qcom,pcie-qcs404
>> - qcom,pcie-sdm845
>> @@ -383,6 +384,35 @@ allOf:
>> - const: axi_s # AXI Slave clock
>> - const: axi_bridge # AXI bridge clock
>> - const: rchng
>> +
>> + - if:
>> + properties:
>> + compatible:
>> + contains:
>> + enum:
>> + - qcom,pcie-ipq9574
>> + then:
>> + properties:
>> + clocks:
>> + minItems: 4
>> + maxItems: 4
>> + clock-names:
>> + items:
>> + - const: axi_m # AXI Master clock
>> + - const: axi_s # AXI Slave clock
>> + - const: axi_bridge # AXI bridge clock
>> + - const: rchng
>> +
>> + - if:
>> + properties:
>> + compatible:
>> + contains:
>> + enum:
>> + - qcom,pcie-ipq6018
>> + - qcom,pcie-ipq8074-gen3
>> + - qcom,pcie-ipq9574
>> + then:
>
> Do not introduce inconsistent style. All if:then: define both clocks and
> resets, right? And after your patch not anymore?
>
I kept the resets in one place because they are the same cross the ipq*
variants.
Do I understand correctly that you wish me to split up the resets as well?
if ipq8074 ipq6018
clocks
resets
if ipq9754
clocks
resets
Alex
> Best regards,
> Krzysztof
>
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH 3/7] dt-bindings: PCI: qcom: Add IPQ9574 PCIe controller
2024-04-03 18:05 ` mr.nuke.me
@ 2024-04-04 6:18 ` Krzysztof Kozlowski
0 siblings, 0 replies; 18+ messages in thread
From: Krzysztof Kozlowski @ 2024-04-04 6:18 UTC (permalink / raw)
To: mr.nuke.me, Bjorn Andersson, Konrad Dybcio, Bjorn Helgaas,
Lorenzo Pieralisi, Krzysztof Wilczyński, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Manivannan Sadhasivam
Cc: ansuelsmth, robimarko, linux-arm-msm, linux-pci, devicetree,
linux-kernel
On 03/04/2024 20:05, mr.nuke.me@gmail.com wrote:
>
>
> On 4/3/24 02:14, Krzysztof Kozlowski wrote:
>> On 02/04/2024 21:25, Alexandru Gagniuc wrote:
>>> IPQ9574 has PCIe controllers which are almost identical to IPQ6018.
>>> The only difference is that the "iface" clock is not required.
>>> Document this difference along with the compatible string.
>>>
>>> Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
>>> ---
>>> .../devicetree/bindings/pci/qcom,pcie.yaml | 32 +++++++++++++++++++
>>> 1 file changed, 32 insertions(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
>>> index cf9a6910b542..6eb29547c18e 100644
>>> --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
>>> +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
>>> @@ -26,6 +26,7 @@ properties:
>>> - qcom,pcie-ipq8064-v2
>>> - qcom,pcie-ipq8074
>>> - qcom,pcie-ipq8074-gen3
>>> + - qcom,pcie-ipq9574
>>> - qcom,pcie-msm8996
>>> - qcom,pcie-qcs404
>>> - qcom,pcie-sdm845
>>> @@ -383,6 +384,35 @@ allOf:
>>> - const: axi_s # AXI Slave clock
>>> - const: axi_bridge # AXI bridge clock
>>> - const: rchng
>>> +
>>> + - if:
>>> + properties:
>>> + compatible:
>>> + contains:
>>> + enum:
>>> + - qcom,pcie-ipq9574
>>> + then:
>>> + properties:
>>> + clocks:
>>> + minItems: 4
>>> + maxItems: 4
>>> + clock-names:
>>> + items:
>>> + - const: axi_m # AXI Master clock
>>> + - const: axi_s # AXI Slave clock
>>> + - const: axi_bridge # AXI bridge clock
>>> + - const: rchng
>>> +
>>> + - if:
>>> + properties:
>>> + compatible:
>>> + contains:
>>> + enum:
>>> + - qcom,pcie-ipq6018
>>> + - qcom,pcie-ipq8074-gen3
>>> + - qcom,pcie-ipq9574
>>> + then:
>>
>> Do not introduce inconsistent style. All if:then: define both clocks and
>> resets, right? And after your patch not anymore?
>>
> I kept the resets in one place because they are the same cross the ipq*
> variants.
>
> Do I understand correctly that you wish me to split up the resets as well?
>
> if ipq8074 ipq6018
> clocks
> resets
>
> if ipq9754
> clocks
> resets
Yes, keep it consistent with all other cases.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 4/7] PCI: qcom: Add support for IPQ9574
2024-04-02 19:25 [PATCH 1/7] dt-bindings: clock: Add PCIe pipe related clocks for IPQ9574 Alexandru Gagniuc
2024-04-02 19:25 ` [PATCH 2/7] clk: qcom: gcc-ipq9574: Add PCIe pipe clocks Alexandru Gagniuc
2024-04-02 19:25 ` [PATCH 3/7] dt-bindings: PCI: qcom: Add IPQ9574 PCIe controller Alexandru Gagniuc
@ 2024-04-02 19:25 ` Alexandru Gagniuc
2024-04-02 19:25 ` [PATCH 5/7] dt-bindings: phy: qcom,ipq8074-qmp-pcie: add ipq9574 gen3x2 PHY Alexandru Gagniuc
` (3 subsequent siblings)
6 siblings, 0 replies; 18+ messages in thread
From: Alexandru Gagniuc @ 2024-04-02 19:25 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Manivannan Sadhasivam,
Lorenzo Pieralisi, Krzysztof Wilczyński, Rob Herring,
Bjorn Helgaas
Cc: ansuelsmth, robimarko, Alexandru Gagniuc, linux-pci,
linux-arm-msm, linux-kernel
Add support for the PCIe on IPQ9574. The main difference from ipq6018
is that the "iface" clock is not necessarry. Add a special case in
qcom_pcie_get_resources_2_9_0() to handle this.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
---
drivers/pci/controller/dwc/pcie-qcom.c | 13 +++++++++----
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 14772edcf0d3..10560d6d6336 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -1101,15 +1101,19 @@ static int qcom_pcie_get_resources_2_9_0(struct qcom_pcie *pcie)
struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0;
struct dw_pcie *pci = pcie->pci;
struct device *dev = pci->dev;
- int ret;
+ int ret, num_clks = ARRAY_SIZE(res->clks) - 1;
- res->clks[0].id = "iface";
+ res->clks[0].id = "rchng";
res->clks[1].id = "axi_m";
res->clks[2].id = "axi_s";
res->clks[3].id = "axi_bridge";
- res->clks[4].id = "rchng";
- ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks);
+ if (!of_device_is_compatible(dev->of_node, "qcom,pcie-ipq9574")) {
+ res->clks[4].id = "iface";
+ num_clks++;
+ }
+
+ ret = devm_clk_bulk_get(dev, num_clks, res->clks);
if (ret < 0)
return ret;
@@ -1664,6 +1668,7 @@ static const struct of_device_id qcom_pcie_match[] = {
{ .compatible = "qcom,pcie-ipq8064-v2", .data = &cfg_2_1_0 },
{ .compatible = "qcom,pcie-ipq8074", .data = &cfg_2_3_3 },
{ .compatible = "qcom,pcie-ipq8074-gen3", .data = &cfg_2_9_0 },
+ { .compatible = "qcom,pcie-ipq9574", .data = &cfg_2_9_0 },
{ .compatible = "qcom,pcie-msm8996", .data = &cfg_2_3_2 },
{ .compatible = "qcom,pcie-qcs404", .data = &cfg_2_4_0 },
{ .compatible = "qcom,pcie-sa8540p", .data = &cfg_sc8280xp },
--
2.40.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 5/7] dt-bindings: phy: qcom,ipq8074-qmp-pcie: add ipq9574 gen3x2 PHY
2024-04-02 19:25 [PATCH 1/7] dt-bindings: clock: Add PCIe pipe related clocks for IPQ9574 Alexandru Gagniuc
` (2 preceding siblings ...)
2024-04-02 19:25 ` [PATCH 4/7] PCI: qcom: Add support for IPQ9574 Alexandru Gagniuc
@ 2024-04-02 19:25 ` Alexandru Gagniuc
2024-04-02 19:56 ` Rafał Miłecki
2024-04-03 7:15 ` Krzysztof Kozlowski
2024-04-02 19:25 ` [PATCH 6/7] phy: qcom-qmp-pcie: add support for " Alexandru Gagniuc
` (2 subsequent siblings)
6 siblings, 2 replies; 18+ messages in thread
From: Alexandru Gagniuc @ 2024-04-02 19:25 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: ansuelsmth, robimarko, Alexandru Gagniuc, linux-arm-msm,
linux-phy, devicetree, linux-kernel
The IPQ9574 gen3x2 PHY is very similar to IPQ6018. It requires two
extra clocks named "anoc" and "snoc". Document this, and add a
new compatible string for this PHY.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
---
.../phy/qcom,ipq8074-qmp-pcie-phy.yaml | 47 +++++++++++++++++--
1 file changed, 42 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml
index 634cec5d57ea..b0dbd2726acd 100644
--- a/Documentation/devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml
@@ -19,19 +19,19 @@ properties:
- qcom,ipq6018-qmp-pcie-phy
- qcom,ipq8074-qmp-gen3-pcie-phy
- qcom,ipq8074-qmp-pcie-phy
+ - qcom,ipq9574-qmp-gen3x2-pcie-phy
reg:
items:
- description: serdes
clocks:
- maxItems: 3
+ minItems: 3
+ maxItems: 5
clock-names:
- items:
- - const: aux
- - const: cfg_ahb
- - const: pipe
+ minItems: 3
+ maxItems: 5
resets:
maxItems: 2
@@ -61,6 +61,43 @@ required:
- clock-output-names
- "#phy-cells"
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,ipq6018-qmp-pcie-phy
+ - qcom,ipq8074-qmp-gen3-pcie-phy
+ - qcom,ipq8074-qmp-pcie-phy
+ then:
+ properties:
+ clocks:
+ maxItems: 3
+ clock-names:
+ items:
+ - const: aux
+ - const: cfg_ahb
+ - const: pipe
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,ipq9574-qmp-gen3x2-pcie-phy
+ then:
+ properties:
+ clocks:
+ maxItems: 5
+ clock-names:
+ items:
+ - const: aux
+ - const: cfg_ahb
+ - const: pipe
+ - const: anoc
+ - const: snoc
+
additionalProperties: false
examples:
--
2.40.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [PATCH 5/7] dt-bindings: phy: qcom,ipq8074-qmp-pcie: add ipq9574 gen3x2 PHY
2024-04-02 19:25 ` [PATCH 5/7] dt-bindings: phy: qcom,ipq8074-qmp-pcie: add ipq9574 gen3x2 PHY Alexandru Gagniuc
@ 2024-04-02 19:56 ` Rafał Miłecki
2024-04-03 7:15 ` Krzysztof Kozlowski
1 sibling, 0 replies; 18+ messages in thread
From: Rafał Miłecki @ 2024-04-02 19:56 UTC (permalink / raw)
To: Alexandru Gagniuc, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: ansuelsmth, robimarko, linux-arm-msm, linux-phy, devicetree,
linux-kernel
One minor mistake (I believe)
On 2.04.2024 21:25, Alexandru Gagniuc wrote:
> @@ -61,6 +61,43 @@ required:
> - clock-output-names
> - "#phy-cells"
>
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - qcom,ipq6018-qmp-pcie-phy
> + - qcom,ipq8074-qmp-gen3-pcie-phy
> + - qcom,ipq8074-qmp-pcie-phy
> + then:
> + properties:
> + clocks:
> + maxItems: 3
> + clock-names:
> + items:
> + - const: aux
> + - const: cfg_ahb
> + - const: pipe
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - qcom,ipq9574-qmp-gen3x2-pcie-phy
> + then:
> + properties:
> + clocks:
> + maxItems: 5
This should probably be minItems: 5.
You already have maxItems: 5 at global property.
> + clock-names:
> + items:
> + - const: aux
> + - const: cfg_ahb
> + - const: pipe
> + - const: anoc
> + - const: snoc
> +
> additionalProperties: false
>
> examples:
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 5/7] dt-bindings: phy: qcom,ipq8074-qmp-pcie: add ipq9574 gen3x2 PHY
2024-04-02 19:25 ` [PATCH 5/7] dt-bindings: phy: qcom,ipq8074-qmp-pcie: add ipq9574 gen3x2 PHY Alexandru Gagniuc
2024-04-02 19:56 ` Rafał Miłecki
@ 2024-04-03 7:15 ` Krzysztof Kozlowski
1 sibling, 0 replies; 18+ messages in thread
From: Krzysztof Kozlowski @ 2024-04-03 7:15 UTC (permalink / raw)
To: Alexandru Gagniuc, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: ansuelsmth, robimarko, linux-arm-msm, linux-phy, devicetree,
linux-kernel
On 02/04/2024 21:25, Alexandru Gagniuc wrote:
> The IPQ9574 gen3x2 PHY is very similar to IPQ6018. It requires two
> extra clocks named "anoc" and "snoc". Document this, and add a
> new compatible string for this PHY.
>
> Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
> ---
> .../phy/qcom,ipq8074-qmp-pcie-phy.yaml | 47 +++++++++++++++++--
> 1 file changed, 42 insertions(+), 5 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml
> index 634cec5d57ea..b0dbd2726acd 100644
> --- a/Documentation/devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml
> +++ b/Documentation/devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml
> @@ -19,19 +19,19 @@ properties:
> - qcom,ipq6018-qmp-pcie-phy
> - qcom,ipq8074-qmp-gen3-pcie-phy
> - qcom,ipq8074-qmp-pcie-phy
> + - qcom,ipq9574-qmp-gen3x2-pcie-phy
>
> reg:
> items:
> - description: serdes
>
> clocks:
> - maxItems: 3
> + minItems: 3
> + maxItems: 5
>
> clock-names:
> - items:
> - - const: aux
> - - const: cfg_ahb
> - - const: pipe
> + minItems: 3
> + maxItems: 5
Just grow the list here to match ipq9574 and keep minItems: 3
>
> resets:
> maxItems: 2
> @@ -61,6 +61,43 @@ required:
> - clock-output-names
> - "#phy-cells"
>
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - qcom,ipq6018-qmp-pcie-phy
> + - qcom,ipq8074-qmp-gen3-pcie-phy
> + - qcom,ipq8074-qmp-pcie-phy
> + then:
> + properties:
> + clocks:
> + maxItems: 3
> + clock-names:
> + items:
> + - const: aux
> + - const: cfg_ahb
> + - const: pipe
Only maxItems: 3
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - qcom,ipq9574-qmp-gen3x2-pcie-phy
> + then:
> + properties:
> + clocks:
> + maxItems: 5
> + clock-names:
> + items:
> + - const: aux
> + - const: cfg_ahb
> + - const: pipe
> + - const: anoc
> + - const: snoc
minItems: 5
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 6/7] phy: qcom-qmp-pcie: add support for ipq9574 gen3x2 PHY
2024-04-02 19:25 [PATCH 1/7] dt-bindings: clock: Add PCIe pipe related clocks for IPQ9574 Alexandru Gagniuc
` (3 preceding siblings ...)
2024-04-02 19:25 ` [PATCH 5/7] dt-bindings: phy: qcom,ipq8074-qmp-pcie: add ipq9574 gen3x2 PHY Alexandru Gagniuc
@ 2024-04-02 19:25 ` Alexandru Gagniuc
2024-04-06 8:47 ` Vinod Koul
2024-04-02 19:25 ` [PATCH 7/7] arm64: dts: qcom: ipq9574: add PCIe2 nodes Alexandru Gagniuc
2024-04-03 7:10 ` [PATCH 1/7] dt-bindings: clock: Add PCIe pipe related clocks for IPQ9574 Krzysztof Kozlowski
6 siblings, 1 reply; 18+ messages in thread
From: Alexandru Gagniuc @ 2024-04-02 19:25 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I
Cc: ansuelsmth, robimarko, Alexandru Gagniuc, linux-arm-msm,
linux-phy, linux-kernel
Add support for the gen3x2 PCIe PHY on IPQ9574, ported form downstream
5.4 kernel. Only the serdes and pcs_misc tables are new, the others
being reused from IPQ8074 and IPQ6018 PHYs.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
---
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 136 +++++++++++++++++-
.../phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h | 14 ++
2 files changed, 149 insertions(+), 1 deletion(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
index 8836bb1ff0cc..f07bd27e3b7a 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
@@ -487,6 +487,100 @@ static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_pcs_misc_tbl[] = {
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
};
+static const struct qmp_phy_init_tbl ipq9574_gen3x2_pcie_serdes_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x31),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0F),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0F),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_MAP, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER1, 0xFF),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER2, 0x3F),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x30),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x21),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xAA),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xAB),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xD4),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE0, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xA0),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV, 0x0A),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TIMER, 0x0A),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xAA),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE1, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xA0),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xB4),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08),
+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7D),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0A),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE0, 0x19),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE1, 0x28),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x89),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x10),
+};
+
+static const struct qmp_phy_init_tbl ipq9574_gen3x2_pcie_pcs_misc_tbl[] = {
+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG2, 0x1d),
+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H, 0x00),
+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H, 0x00),
+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG1, 0x14),
+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG1, 0x10),
+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0b),
+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_PRESET_P10_PRE, 0x00),
+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_PRESET_P10_POST, 0x58),
+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG1, 0x00),
+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG2, 0x52),
+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG4, 0x19),
+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2, 0x49),
+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4, 0x2a),
+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x02),
+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG6, 0x03),
+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
+};
+
static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = {
QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
@@ -2448,7 +2542,7 @@ static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
/* list of clocks required by phy */
static const char * const qmp_pciephy_clk_l[] = {
- "aux", "cfg_ahb", "ref", "refgen", "rchng", "phy_aux",
+ "aux", "cfg_ahb", "ref", "refgen", "rchng", "phy_aux", "anoc", "snoc"
};
/* list of regulators */
@@ -2499,6 +2593,16 @@ static const struct qmp_pcie_offsets qmp_pcie_offsets_v4x1 = {
.rx = 0x0400,
};
+static const struct qmp_pcie_offsets qmp_pcie_offsets_ipq9574 = {
+ .serdes = 0,
+ .pcs = 0x1000,
+ .pcs_misc = 0x1400,
+ .tx = 0x0200,
+ .rx = 0x0400,
+ .tx2 = 0x0600,
+ .rx2 = 0x0800,
+};
+
static const struct qmp_pcie_offsets qmp_pcie_offsets_v4x2 = {
.serdes = 0,
.pcs = 0x0a00,
@@ -2728,6 +2832,33 @@ static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = {
.phy_status = PHYSTATUS,
};
+static const struct qmp_phy_cfg ipq9574_pciephy_gen3x2_cfg = {
+ .lanes = 2,
+
+ .offsets = &qmp_pcie_offsets_ipq9574,
+
+ .tbls = {
+ .serdes = ipq9574_gen3x2_pcie_serdes_tbl,
+ .serdes_num = ARRAY_SIZE(ipq9574_gen3x2_pcie_serdes_tbl),
+ .tx = ipq8074_pcie_gen3_tx_tbl,
+ .tx_num = ARRAY_SIZE(ipq8074_pcie_gen3_tx_tbl),
+ .rx = ipq6018_pcie_rx_tbl,
+ .rx_num = ARRAY_SIZE(ipq6018_pcie_rx_tbl),
+ .pcs = ipq6018_pcie_pcs_tbl,
+ .pcs_num = ARRAY_SIZE(ipq6018_pcie_pcs_tbl),
+ .pcs_misc = ipq9574_gen3x2_pcie_pcs_misc_tbl,
+ .pcs_misc_num = ARRAY_SIZE(ipq9574_gen3x2_pcie_pcs_misc_tbl),
+ },
+ .reset_list = ipq8074_pciephy_reset_l,
+ .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
+ .vreg_list = NULL,
+ .num_vregs = 0,
+ .regs = pciephy_v4_regs_layout,
+
+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
+ .phy_status = PHYSTATUS,
+};
+
static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = {
.lanes = 2,
@@ -3935,6 +4066,9 @@ static const struct of_device_id qmp_pcie_of_match_table[] = {
}, {
.compatible = "qcom,ipq8074-qmp-pcie-phy",
.data = &ipq8074_pciephy_cfg,
+ }, {
+ .compatible = "qcom,ipq9574-qmp-gen3x2-pcie-phy",
+ .data = &ipq9574_pciephy_gen3x2_cfg,
}, {
.compatible = "qcom,msm8998-qmp-pcie-phy",
.data = &msm8998_pciephy_cfg,
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h
index a469ae2a10a1..fa15a03055de 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h
@@ -11,8 +11,22 @@
#define QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG2 0x0c
#define QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG4 0x14
#define QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x20
+#define QPHY_V5_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L 0x44
+#define QPHY_V5_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H 0x48
+#define QPHY_V5_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L 0x4c
+#define QPHY_V5_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H 0x50
#define QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x54
+#define QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG1 0x5c
+#define QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG2 0x60
+#define QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG4 0x68
+#define QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2 0x7c
+#define QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4 0x84
+#define QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5 0x88
+#define QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG6 0x8c
#define QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS 0x94
+#define QPHY_V5_PCS_PCIE_EQ_CONFIG1 0xa4
#define QPHY_V5_PCS_PCIE_EQ_CONFIG2 0xa8
+#define QPHY_V5_PCS_PCIE_PRESET_P10_PRE 0xc0
+#define QPHY_V5_PCS_PCIE_PRESET_P10_POST 0xe4
#endif
--
2.40.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [PATCH 6/7] phy: qcom-qmp-pcie: add support for ipq9574 gen3x2 PHY
2024-04-02 19:25 ` [PATCH 6/7] phy: qcom-qmp-pcie: add support for " Alexandru Gagniuc
@ 2024-04-06 8:47 ` Vinod Koul
2024-04-06 14:37 ` Dmitry Baryshkov
0 siblings, 1 reply; 18+ messages in thread
From: Vinod Koul @ 2024-04-06 8:47 UTC (permalink / raw)
To: Alexandru Gagniuc
Cc: Bjorn Andersson, Konrad Dybcio, Kishon Vijay Abraham I,
ansuelsmth, robimarko, linux-arm-msm, linux-phy, linux-kernel
On 02-04-24, 14:25, Alexandru Gagniuc wrote:
> Add support for the gen3x2 PCIe PHY on IPQ9574, ported form downstream
> 5.4 kernel. Only the serdes and pcs_misc tables are new, the others
> being reused from IPQ8074 and IPQ6018 PHYs.
>
> Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
> ---
> drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 136 +++++++++++++++++-
> .../phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h | 14 ++
> 2 files changed, 149 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> index 8836bb1ff0cc..f07bd27e3b7a 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> @@ -487,6 +487,100 @@ static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_pcs_misc_tbl[] = {
> QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
> };
>
> +static const struct qmp_phy_init_tbl ipq9574_gen3x2_pcie_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x31),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0F),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0F),
Lower case here and everywhere please
> + QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_MAP, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER1, 0xFF),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER2, 0x3F),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x21),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xAA),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xAB),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xD4),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xA0),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV, 0x0A),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TIMER, 0x0A),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xAA),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xA0),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xB4),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7D),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0A),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE0, 0x19),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE1, 0x28),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x89),
> + QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x10),
> +};
> +
> +static const struct qmp_phy_init_tbl ipq9574_gen3x2_pcie_pcs_misc_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG2, 0x1d),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG1, 0x14),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG1, 0x10),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0b),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_PRESET_P10_PRE, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_PRESET_P10_POST, 0x58),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG1, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG2, 0x52),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG4, 0x19),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2, 0x49),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4, 0x2a),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x02),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG6, 0x03),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
> +};
> +
> static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = {
> QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
> QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
> @@ -2448,7 +2542,7 @@ static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
>
> /* list of clocks required by phy */
> static const char * const qmp_pciephy_clk_l[] = {
> - "aux", "cfg_ahb", "ref", "refgen", "rchng", "phy_aux",
> + "aux", "cfg_ahb", "ref", "refgen", "rchng", "phy_aux", "anoc", "snoc"
How about older platforms which dont have these clocks
> };
>
> /* list of regulators */
> @@ -2499,6 +2593,16 @@ static const struct qmp_pcie_offsets qmp_pcie_offsets_v4x1 = {
> .rx = 0x0400,
> };
>
> +static const struct qmp_pcie_offsets qmp_pcie_offsets_ipq9574 = {
> + .serdes = 0,
> + .pcs = 0x1000,
> + .pcs_misc = 0x1400,
> + .tx = 0x0200,
> + .rx = 0x0400,
> + .tx2 = 0x0600,
> + .rx2 = 0x0800,
> +};
> +
> static const struct qmp_pcie_offsets qmp_pcie_offsets_v4x2 = {
> .serdes = 0,
> .pcs = 0x0a00,
> @@ -2728,6 +2832,33 @@ static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = {
> .phy_status = PHYSTATUS,
> };
>
> +static const struct qmp_phy_cfg ipq9574_pciephy_gen3x2_cfg = {
> + .lanes = 2,
> +
> + .offsets = &qmp_pcie_offsets_ipq9574,
> +
> + .tbls = {
> + .serdes = ipq9574_gen3x2_pcie_serdes_tbl,
> + .serdes_num = ARRAY_SIZE(ipq9574_gen3x2_pcie_serdes_tbl),
> + .tx = ipq8074_pcie_gen3_tx_tbl,
> + .tx_num = ARRAY_SIZE(ipq8074_pcie_gen3_tx_tbl),
> + .rx = ipq6018_pcie_rx_tbl,
> + .rx_num = ARRAY_SIZE(ipq6018_pcie_rx_tbl),
> + .pcs = ipq6018_pcie_pcs_tbl,
> + .pcs_num = ARRAY_SIZE(ipq6018_pcie_pcs_tbl),
> + .pcs_misc = ipq9574_gen3x2_pcie_pcs_misc_tbl,
> + .pcs_misc_num = ARRAY_SIZE(ipq9574_gen3x2_pcie_pcs_misc_tbl),
> + },
> + .reset_list = ipq8074_pciephy_reset_l,
> + .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
> + .vreg_list = NULL,
> + .num_vregs = 0,
> + .regs = pciephy_v4_regs_layout,
> +
> + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
> + .phy_status = PHYSTATUS,
> +};
> +
> static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = {
> .lanes = 2,
>
> @@ -3935,6 +4066,9 @@ static const struct of_device_id qmp_pcie_of_match_table[] = {
> }, {
> .compatible = "qcom,ipq8074-qmp-pcie-phy",
> .data = &ipq8074_pciephy_cfg,
> + }, {
> + .compatible = "qcom,ipq9574-qmp-gen3x2-pcie-phy",
> + .data = &ipq9574_pciephy_gen3x2_cfg,
> }, {
> .compatible = "qcom,msm8998-qmp-pcie-phy",
> .data = &msm8998_pciephy_cfg,
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h
> index a469ae2a10a1..fa15a03055de 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h
> @@ -11,8 +11,22 @@
> #define QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG2 0x0c
> #define QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG4 0x14
> #define QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x20
> +#define QPHY_V5_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L 0x44
> +#define QPHY_V5_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H 0x48
> +#define QPHY_V5_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L 0x4c
> +#define QPHY_V5_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H 0x50
> #define QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x54
> +#define QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG1 0x5c
> +#define QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG2 0x60
> +#define QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG4 0x68
> +#define QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2 0x7c
> +#define QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4 0x84
> +#define QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5 0x88
> +#define QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG6 0x8c
> #define QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS 0x94
> +#define QPHY_V5_PCS_PCIE_EQ_CONFIG1 0xa4
> #define QPHY_V5_PCS_PCIE_EQ_CONFIG2 0xa8
> +#define QPHY_V5_PCS_PCIE_PRESET_P10_PRE 0xc0
> +#define QPHY_V5_PCS_PCIE_PRESET_P10_POST 0xe4
>
> #endif
> --
> 2.40.1
--
~Vinod
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH 6/7] phy: qcom-qmp-pcie: add support for ipq9574 gen3x2 PHY
2024-04-06 8:47 ` Vinod Koul
@ 2024-04-06 14:37 ` Dmitry Baryshkov
2024-04-06 16:48 ` Alex G.
0 siblings, 1 reply; 18+ messages in thread
From: Dmitry Baryshkov @ 2024-04-06 14:37 UTC (permalink / raw)
To: Vinod Koul
Cc: Alexandru Gagniuc, Bjorn Andersson, Konrad Dybcio,
Kishon Vijay Abraham I, ansuelsmth, robimarko, linux-arm-msm,
linux-phy, linux-kernel
On Sat, 6 Apr 2024 at 11:47, Vinod Koul <vkoul@kernel.org> wrote:
>
> On 02-04-24, 14:25, Alexandru Gagniuc wrote:
> > Add support for the gen3x2 PCIe PHY on IPQ9574, ported form downstream
> > 5.4 kernel. Only the serdes and pcs_misc tables are new, the others
> > being reused from IPQ8074 and IPQ6018 PHYs.
> >
> > Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
> > ---
> > drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 136 +++++++++++++++++-
> > .../phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h | 14 ++
> > 2 files changed, 149 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> > index 8836bb1ff0cc..f07bd27e3b7a 100644
> > --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> > @@ -487,6 +487,100 @@ static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_pcs_misc_tbl[] = {
> > QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
> > };
> >
> > +static const struct qmp_phy_init_tbl ipq9574_gen3x2_pcie_serdes_tbl[] = {
> > + QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18),
> > + QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01),
> > + QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x31),
> > + QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0F),
> > + QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0F),
>
> Lower case here and everywhere please
For hex values
>
> > + QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06),
> > + QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42),
> > + QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20),
> > + QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x01),
> > + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_MAP, 0x04),
> > + QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
> > + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER1, 0xFF),
> > + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER2, 0x3F),
> > + QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x30),
> > + QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x21),
> > + QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68),
> > + QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02),
> > + QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xAA),
> > + QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xAB),
> > + QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14),
> > + QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xD4),
> > + QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09),
> > + QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16),
> > + QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28),
> > + QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE0, 0x00),
> > + QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xA0),
> > + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02),
> > + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24),
> > + QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
> > + QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00),
> > + QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV, 0x0A),
> > + QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32),
> > + QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02),
> > + QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07),
> > + QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08),
> > + QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TIMER, 0x0A),
> > + QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01),
> > + QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53),
> > + QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05),
> > + QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55),
> > + QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55),
> > + QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29),
> > + QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xAA),
> > + QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09),
> > + QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16),
> > + QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28),
> > + QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE1, 0x00),
> > + QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xA0),
> > + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03),
> > + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xB4),
> > + QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
> > + QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00),
> > + QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08),
> > + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
> > + QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7D),
> > + QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01),
> > + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
> > + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
> > + QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0A),
> > + QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05),
> > + QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08),
> > + QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04),
> > + QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE0, 0x19),
> > + QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE1, 0x28),
> > + QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
> > + QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x89),
> > + QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x10),
> > +};
> > +
> > +static const struct qmp_phy_init_tbl ipq9574_gen3x2_pcie_pcs_misc_tbl[] = {
> > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
> > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG2, 0x1d),
> > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H, 0x00),
> > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
> > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H, 0x00),
> > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
> > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG1, 0x14),
> > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG1, 0x10),
> > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0b),
> > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_PRESET_P10_PRE, 0x00),
> > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_PRESET_P10_POST, 0x58),
> > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
> > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG1, 0x00),
> > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG2, 0x52),
> > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG4, 0x19),
> > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
> > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2, 0x49),
> > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4, 0x2a),
> > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x02),
> > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG6, 0x03),
> > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
> > +};
> > +
> > static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = {
> > QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
> > QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
> > @@ -2448,7 +2542,7 @@ static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
> >
> > /* list of clocks required by phy */
> > static const char * const qmp_pciephy_clk_l[] = {
> > - "aux", "cfg_ahb", "ref", "refgen", "rchng", "phy_aux",
> > + "aux", "cfg_ahb", "ref", "refgen", "rchng", "phy_aux", "anoc", "snoc"
>
> How about older platforms which dont have these clocks
The driver uses devm_clk_bulk_get_optional(), so it should be fine.
But the more important question should be why the platform needs
anoc/snoc clocks here.
>
> > };
> >
> > /* list of regulators */
> > @@ -2499,6 +2593,16 @@ static const struct qmp_pcie_offsets qmp_pcie_offsets_v4x1 = {
> > .rx = 0x0400,
> > };
> >
> > +static const struct qmp_pcie_offsets qmp_pcie_offsets_ipq9574 = {
> > + .serdes = 0,
> > + .pcs = 0x1000,
> > + .pcs_misc = 0x1400,
> > + .tx = 0x0200,
> > + .rx = 0x0400,
> > + .tx2 = 0x0600,
> > + .rx2 = 0x0800,
> > +};
> > +
> > static const struct qmp_pcie_offsets qmp_pcie_offsets_v4x2 = {
> > .serdes = 0,
> > .pcs = 0x0a00,
> > @@ -2728,6 +2832,33 @@ static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = {
> > .phy_status = PHYSTATUS,
> > };
> >
> > +static const struct qmp_phy_cfg ipq9574_pciephy_gen3x2_cfg = {
> > + .lanes = 2,
> > +
> > + .offsets = &qmp_pcie_offsets_ipq9574,
> > +
> > + .tbls = {
> > + .serdes = ipq9574_gen3x2_pcie_serdes_tbl,
> > + .serdes_num = ARRAY_SIZE(ipq9574_gen3x2_pcie_serdes_tbl),
> > + .tx = ipq8074_pcie_gen3_tx_tbl,
> > + .tx_num = ARRAY_SIZE(ipq8074_pcie_gen3_tx_tbl),
> > + .rx = ipq6018_pcie_rx_tbl,
> > + .rx_num = ARRAY_SIZE(ipq6018_pcie_rx_tbl),
> > + .pcs = ipq6018_pcie_pcs_tbl,
> > + .pcs_num = ARRAY_SIZE(ipq6018_pcie_pcs_tbl),
> > + .pcs_misc = ipq9574_gen3x2_pcie_pcs_misc_tbl,
> > + .pcs_misc_num = ARRAY_SIZE(ipq9574_gen3x2_pcie_pcs_misc_tbl),
> > + },
> > + .reset_list = ipq8074_pciephy_reset_l,
> > + .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
> > + .vreg_list = NULL,
> > + .num_vregs = 0,
> > + .regs = pciephy_v4_regs_layout,
> > +
> > + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
> > + .phy_status = PHYSTATUS,
> > +};
> > +
> > static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = {
> > .lanes = 2,
> >
> > @@ -3935,6 +4066,9 @@ static const struct of_device_id qmp_pcie_of_match_table[] = {
> > }, {
> > .compatible = "qcom,ipq8074-qmp-pcie-phy",
> > .data = &ipq8074_pciephy_cfg,
> > + }, {
> > + .compatible = "qcom,ipq9574-qmp-gen3x2-pcie-phy",
> > + .data = &ipq9574_pciephy_gen3x2_cfg,
> > }, {
> > .compatible = "qcom,msm8998-qmp-pcie-phy",
> > .data = &msm8998_pciephy_cfg,
> > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h
> > index a469ae2a10a1..fa15a03055de 100644
> > --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h
> > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h
> > @@ -11,8 +11,22 @@
> > #define QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG2 0x0c
> > #define QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG4 0x14
> > #define QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x20
> > +#define QPHY_V5_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L 0x44
> > +#define QPHY_V5_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H 0x48
> > +#define QPHY_V5_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L 0x4c
> > +#define QPHY_V5_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H 0x50
> > #define QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x54
> > +#define QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG1 0x5c
> > +#define QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG2 0x60
> > +#define QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG4 0x68
> > +#define QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2 0x7c
> > +#define QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4 0x84
> > +#define QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5 0x88
> > +#define QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG6 0x8c
> > #define QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS 0x94
> > +#define QPHY_V5_PCS_PCIE_EQ_CONFIG1 0xa4
> > #define QPHY_V5_PCS_PCIE_EQ_CONFIG2 0xa8
> > +#define QPHY_V5_PCS_PCIE_PRESET_P10_PRE 0xc0
> > +#define QPHY_V5_PCS_PCIE_PRESET_P10_POST 0xe4
> >
> > #endif
> > --
> > 2.40.1
>
> --
> ~Vinod
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH 6/7] phy: qcom-qmp-pcie: add support for ipq9574 gen3x2 PHY
2024-04-06 14:37 ` Dmitry Baryshkov
@ 2024-04-06 16:48 ` Alex G.
0 siblings, 0 replies; 18+ messages in thread
From: Alex G. @ 2024-04-06 16:48 UTC (permalink / raw)
To: Dmitry Baryshkov, Vinod Koul
Cc: Bjorn Andersson, Konrad Dybcio, Kishon Vijay Abraham I,
ansuelsmth, robimarko, linux-arm-msm, linux-phy, linux-kernel
On 4/6/24 09:37, Dmitry Baryshkov wrote:
> On Sat, 6 Apr 2024 at 11:47, Vinod Koul <vkoul@kernel.org> wrote:
>>
>> On 02-04-24, 14:25, Alexandru Gagniuc wrote:
>>> Add support for the gen3x2 PCIe PHY on IPQ9574, ported form downstream
>>> 5.4 kernel. Only the serdes and pcs_misc tables are new, the others
>>> being reused from IPQ8074 and IPQ6018 PHYs.
>>>
>>> Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
>>> ---
>>> drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 136 +++++++++++++++++-
>>> .../phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h | 14 ++
>>> 2 files changed, 149 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
>>> index 8836bb1ff0cc..f07bd27e3b7a 100644
>>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
>>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
>>> @@ -487,6 +487,100 @@ static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_pcs_misc_tbl[] = {
>>> QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
>>> };
>>>
>>> +static const struct qmp_phy_init_tbl ipq9574_gen3x2_pcie_serdes_tbl[] = {
>>> + QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18),
>>> + QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01),
>>> + QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x31),
>>> + QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0F),
>>> + QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0F),
>>
>> Lower case here and everywhere please
>
> For hex values
I will these updated in V2. Thanks!
>>> static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = {
>>> QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
>>> QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
>>> @@ -2448,7 +2542,7 @@ static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
>>>
>>> /* list of clocks required by phy */
>>> static const char * const qmp_pciephy_clk_l[] = {
>>> - "aux", "cfg_ahb", "ref", "refgen", "rchng", "phy_aux",
>>> + "aux", "cfg_ahb", "ref", "refgen", "rchng", "phy_aux", "anoc", "snoc"
>>
>> How about older platforms which dont have these clocks
>
> The driver uses devm_clk_bulk_get_optional(), so it should be fine.
> But the more important question should be why the platform needs
> anoc/snoc clocks here.
>
I got the info from the downstream 5.4 kernel. While I don't know why
these new clocks are required, they are needed. Omitting them will cause
the boot to hang.
I could rename them to "snoc_lane" and "anoc_lane", if you think that
makes more sense.
Alex
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 7/7] arm64: dts: qcom: ipq9574: add PCIe2 nodes
2024-04-02 19:25 [PATCH 1/7] dt-bindings: clock: Add PCIe pipe related clocks for IPQ9574 Alexandru Gagniuc
` (4 preceding siblings ...)
2024-04-02 19:25 ` [PATCH 6/7] phy: qcom-qmp-pcie: add support for " Alexandru Gagniuc
@ 2024-04-02 19:25 ` Alexandru Gagniuc
2024-04-03 7:11 ` Krzysztof Kozlowski
2024-04-03 7:10 ` [PATCH 1/7] dt-bindings: clock: Add PCIe pipe related clocks for IPQ9574 Krzysztof Kozlowski
6 siblings, 1 reply; 18+ messages in thread
From: Alexandru Gagniuc @ 2024-04-02 19:25 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: ansuelsmth, robimarko, Alexandru Gagniuc, linux-arm-msm,
devicetree, linux-kernel
On ipq9574, there are 4 PCIe controllers. Describe the pcie2 node, and
its PHY in devicetree.
Only pcie2 is described, because only hardware using that controller
was available for testing.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
---
arch/arm64/boot/dts/qcom/ipq9574.dtsi | 93 ++++++++++++++++++++++++++-
1 file changed, 92 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
index 7f2e5cbf3bbb..626d6359d750 100644
--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
@@ -300,7 +300,7 @@ gcc: clock-controller@1800000 {
<0>,
<0>,
<0>,
- <0>,
+ <&pcie2_qmp_phy>,
<0>,
<0>;
#clock-cells = <1>;
@@ -745,6 +745,97 @@ frame@b128000 {
status = "disabled";
};
};
+
+ pcie2_qmp_phy: phy@8c000 {
+ compatible = "qcom,ipq9574-qmp-gen3x2-pcie-phy";
+ reg = <0x0008c000 0x14f4>;
+
+ clocks = <&gcc GCC_PCIE2_AUX_CLK>,
+ <&gcc GCC_PCIE2_AHB_CLK>,
+ <&gcc GCC_PCIE2_PIPE_CLK>,
+ <&gcc GCC_ANOC_PCIE2_2LANE_M_CLK>,
+ <&gcc GCC_SNOC_PCIE2_2LANE_S_CLK>;
+ clock-names = "aux",
+ "cfg_ahb",
+ "pipe",
+ "anoc",
+ "snoc";
+
+ clock-output-names = "pcie_phy2_pipe_clk";
+ #clock-cells = <0>;
+ #phy-cells = <0>;
+
+ resets = <&gcc GCC_PCIE2_PHY_BCR>,
+ <&gcc GCC_PCIE2PHY_PHY_BCR>;
+ reset-names = "phy",
+ "common";
+ status = "disabled";
+ };
+
+ pcie2: pcie@20000000 {
+ compatible = "qcom,pcie-ipq9574";
+ reg = <0x20000000 0xf1d>,
+ <0x20000f20 0xa8>,
+ <0x20001000 0x1000>,
+ <0x00088000 0x4000>,
+ <0x20100000 0x1000>;
+ reg-names = "dbi", "elbi", "atu", "parf", "config";
+ device_type = "pci";
+ linux,pci-domain = <3>;
+ bus-range = <0x00 0xff>;
+ num-lanes = <2>;
+ max-link-speed = <3>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ phys = <&pcie2_qmp_phy>;
+ phy-names = "pciephy";
+
+ ranges = <0x81000000 0x0 0x20200000 0x20200000 0x0 0x00100000>, /* I/O */
+ <0x82000000 0x0 0x20300000 0x20300000 0x0 0x07d00000>; /* MEM */
+
+ interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
+ msi-parent = <&v2m0>;
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 0 164
+ IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc 0 0 165
+ IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc 0 0 186
+ IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc 0 0 187
+ IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+ clocks = <&gcc GCC_PCIE2_AXI_M_CLK>,
+ <&gcc GCC_PCIE2_AXI_S_CLK>,
+ <&gcc GCC_PCIE2_AXI_S_BRIDGE_CLK>,
+ <&gcc GCC_PCIE2_RCHNG_CLK>;
+ clock-names = "axi_m",
+ "axi_s",
+ "axi_bridge",
+ "rchng";
+
+ resets = <&gcc GCC_PCIE2_PIPE_ARES>,
+ <&gcc GCC_PCIE2_CORE_STICKY_ARES>,
+ <&gcc GCC_PCIE2_AXI_S_STICKY_ARES>,
+ <&gcc GCC_PCIE2_AXI_S_ARES>,
+ <&gcc GCC_PCIE2_AXI_M_STICKY_ARES>,
+ <&gcc GCC_PCIE2_AXI_M_ARES>,
+ <&gcc GCC_PCIE2_AUX_ARES>,
+ <&gcc GCC_PCIE2_AHB_ARES>;
+ reset-names = "pipe",
+ "sticky",
+ "axi_s_sticky",
+ "axi_s",
+ "axi_m_sticky",
+ "axi_m",
+ "aux",
+ "ahb";
+ status = "disabled";
+ };
};
thermal-zones {
--
2.40.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [PATCH 7/7] arm64: dts: qcom: ipq9574: add PCIe2 nodes
2024-04-02 19:25 ` [PATCH 7/7] arm64: dts: qcom: ipq9574: add PCIe2 nodes Alexandru Gagniuc
@ 2024-04-03 7:11 ` Krzysztof Kozlowski
0 siblings, 0 replies; 18+ messages in thread
From: Krzysztof Kozlowski @ 2024-04-03 7:11 UTC (permalink / raw)
To: Alexandru Gagniuc, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: ansuelsmth, robimarko, linux-arm-msm, devicetree, linux-kernel
On 02/04/2024 21:25, Alexandru Gagniuc wrote:
> On ipq9574, there are 4 PCIe controllers. Describe the pcie2 node, and
> its PHY in devicetree.
>
> Only pcie2 is described, because only hardware using that controller
> was available for testing.
>
> Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
> ---
> arch/arm64/boot/dts/qcom/ipq9574.dtsi | 93 ++++++++++++++++++++++++++-
> 1 file changed, 92 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> index 7f2e5cbf3bbb..626d6359d750 100644
> --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> @@ -300,7 +300,7 @@ gcc: clock-controller@1800000 {
> <0>,
> <0>,
> <0>,
> - <0>,
> + <&pcie2_qmp_phy>,
> <0>,
> <0>;
> #clock-cells = <1>;
> @@ -745,6 +745,97 @@ frame@b128000 {
> status = "disabled";
> };
> };
> +
> + pcie2_qmp_phy: phy@8c000 {
> + compatible = "qcom,ipq9574-qmp-gen3x2-pcie-phy";
> + reg = <0x0008c000 0x14f4>;
> +
> + clocks = <&gcc GCC_PCIE2_AUX_CLK>,
> + <&gcc GCC_PCIE2_AHB_CLK>,
> + <&gcc GCC_PCIE2_PIPE_CLK>,
> + <&gcc GCC_ANOC_PCIE2_2LANE_M_CLK>,
> + <&gcc GCC_SNOC_PCIE2_2LANE_S_CLK>;
> + clock-names = "aux",
> + "cfg_ahb",
> + "pipe",
> + "anoc",
> + "snoc";
> +
> + clock-output-names = "pcie_phy2_pipe_clk";
> + #clock-cells = <0>;
> + #phy-cells = <0>;
> +
> + resets = <&gcc GCC_PCIE2_PHY_BCR>,
> + <&gcc GCC_PCIE2PHY_PHY_BCR>;
> + reset-names = "phy",
> + "common";
> + status = "disabled";
> + };
> +
> + pcie2: pcie@20000000 {
> + compatible = "qcom,pcie-ipq9574";
> + reg = <0x20000000 0xf1d>,
> + <0x20000f20 0xa8>,
> + <0x20001000 0x1000>,
> + <0x00088000 0x4000>,
> + <0x20100000 0x1000>;
> + reg-names = "dbi", "elbi", "atu", "parf", "config";
Put ranges here.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 1/7] dt-bindings: clock: Add PCIe pipe related clocks for IPQ9574
2024-04-02 19:25 [PATCH 1/7] dt-bindings: clock: Add PCIe pipe related clocks for IPQ9574 Alexandru Gagniuc
` (5 preceding siblings ...)
2024-04-02 19:25 ` [PATCH 7/7] arm64: dts: qcom: ipq9574: add PCIe2 nodes Alexandru Gagniuc
@ 2024-04-03 7:10 ` Krzysztof Kozlowski
2024-04-03 17:58 ` mr.nuke.me
6 siblings, 1 reply; 18+ messages in thread
From: Krzysztof Kozlowski @ 2024-04-03 7:10 UTC (permalink / raw)
To: Alexandru Gagniuc, Bjorn Andersson, Konrad Dybcio,
Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: ansuelsmth, robimarko, linux-arm-msm, linux-clk, devicetree,
linux-kernel
On 02/04/2024 21:25, Alexandru Gagniuc wrote:
> Add defines for the missing PCIe PIPE clocks.
>
> Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
> ---
> include/dt-bindings/clock/qcom,ipq9574-gcc.h | 4 ++++
> 1 file changed, 4 insertions(+)
I did not get half of this patchset. Are you sure you are CC-ing everyone?
For this one:
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH 1/7] dt-bindings: clock: Add PCIe pipe related clocks for IPQ9574
2024-04-03 7:10 ` [PATCH 1/7] dt-bindings: clock: Add PCIe pipe related clocks for IPQ9574 Krzysztof Kozlowski
@ 2024-04-03 17:58 ` mr.nuke.me
0 siblings, 0 replies; 18+ messages in thread
From: mr.nuke.me @ 2024-04-03 17:58 UTC (permalink / raw)
To: Krzysztof Kozlowski, Bjorn Andersson, Konrad Dybcio,
Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: ansuelsmth, robimarko, linux-arm-msm, linux-clk, devicetree,
linux-kernel
On 4/3/24 02:10, Krzysztof Kozlowski wrote:
> On 02/04/2024 21:25, Alexandru Gagniuc wrote:
>> Add defines for the missing PCIe PIPE clocks.
>>
>> Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
>> ---
>> include/dt-bindings/clock/qcom,ipq9574-gcc.h | 4 ++++
>> 1 file changed, 4 insertions(+)
>
> I did not get half of this patchset. Are you sure you are CC-ing everyone?
The other changes are driver code that implements these DT bindings. I
used --cc-cmd of git send-email to find the maintainers. I'll manually
CC you to the other patches in V2.
Alex
> For this one:
>
> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>
>
>
> Best regards,
> Krzysztof
>
^ permalink raw reply [flat|nested] 18+ messages in thread