Re: [PATCH v5 1/4] dt-bindings: rtc: add schema for NXP S32G2/S32G3 SoCs

[Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>]

On 11/26/2024 9:08 PM, Krzysztof Kozlowski wrote:
> On 26/11/2024 12:49, Ciprian Costea wrote:
>> +
>> +title: NXP S32G2/S32G3 Real Time Clock (RTC)
>> +
>> +maintainers:
>> +  - Bogdan Hamciuc <bogdan.hamciuc@nxp.com>
>> +  - Ciprian Marian Costea <ciprianmarian.costea@nxp.com>
>> +
>> +description:
>> +  RTC hardware module present on S32G2/S32G3 SoCs is used as a wakeup source.
>> +  It is not kept alive during system reset and it is not battery-powered.
> 
> Does this mean that this is not a standard RTC thus standard RTC schema
> does not apply?
> 

Hello Krzysztof,

I would say the standard RTC schema does apply but indeed you bring up a 
valid point in the fact that I forgot to reference 'rtc.yaml' schema.
I will fix this in V6, by adding:

allOf:
   - $ref: rtc.yaml#

>> +
>> +properties:
>> +  compatible:
>> +    oneOf:
>> +      - enum:
>> +          - nxp,s32g2-rtc
>> +      - items:
>> +          - const: nxp,s32g3-rtc
>> +          - const: nxp,s32g2-rtc
>> +
>> +  reg:
>> +    maxItems: 1
>> +
>> +  interrupts:
>> +    maxItems: 1
>> +
>> +  clocks:
>> +    items:
>> +      - description: ipg clock drives the access to the RTC iomapped registers
>> +      - description: Clock source for the RTC module. Can be selected between
>> +          4 different clock sources using an integrated hardware mux.
>> +          On S32G2/S32G3 SoCs, 'source0' is the SIRC clock (~32KHz) and it is
>> +          available during standby and runtime. 'source1' is reserved and cannot
> 
> I am not sure what are the benefits of allowing to choose a clock which
> cannot be used. I think source1 should be dropped.
> 

The current RTC support targets S32G2/S32G3 SoCs where 'source1' clock 
source cannot be used. The reasoning for allowing to choose it is that 
on future SoCs from S32 family the same RTC module may be integrated and 
'source1' may become available.

>> +          be used. 'source2' is the FIRC clock and it is only available during
>> +          runtime providing a better resolution (~48MHz). 'source3' is an external
>> +          RTC clock source which can be additionally added in hardware.
>> +
>> +  clock-names:
>> +    items:
>> +      - const: ipg
>> +      - enum: [ source0, source1, source2, source3 ]
>> +
> Best regards,
> Krzysztof

Best Regards,
Ciprian