Re: [RFC PATCH v2 4/6] x86/boot: Set 5-level paging CPU cap before entering C code

[Ingo Molnar <mingo@kernel.org>]

* Ard Biesheuvel <ardb+git@google.com> wrote:

> diff --git a/arch/x86/kernel/asm-offsets.c b/arch/x86/kernel/asm-offsets.c
> index ad4ea6fb3b6c..6259b474073b 100644
> --- a/arch/x86/kernel/asm-offsets.c
> +++ b/arch/x86/kernel/asm-offsets.c
> @@ -33,6 +33,14 @@
>  
>  static void __used common(void)
>  {
> +	OFFSET(CPUINFO_x86, cpuinfo_x86, x86);
> +	OFFSET(CPUINFO_x86_vendor, cpuinfo_x86, x86_vendor);
> +	OFFSET(CPUINFO_x86_model, cpuinfo_x86, x86_model);
> +	OFFSET(CPUINFO_x86_stepping, cpuinfo_x86, x86_stepping);
> +	OFFSET(CPUINFO_cpuid_level, cpuinfo_x86, cpuid_level);
> +	OFFSET(CPUINFO_x86_capability, cpuinfo_x86, x86_capability);
> +	OFFSET(CPUINFO_x86_vendor_id, cpuinfo_x86, x86_vendor_id);
> +
>  	BLANK();
>  	OFFSET(TASK_threadsp, task_struct, thread.sp);
>  #ifdef CONFIG_STACKPROTECTOR
> diff --git a/arch/x86/kernel/asm-offsets_32.c b/arch/x86/kernel/asm-offsets_32.c
> index 2b411cd00a4e..e0a292db97b2 100644
> --- a/arch/x86/kernel/asm-offsets_32.c
> +++ b/arch/x86/kernel/asm-offsets_32.c
> @@ -12,15 +12,6 @@ void foo(void);
>  
>  void foo(void)
>  {
> -	OFFSET(CPUINFO_x86, cpuinfo_x86, x86);
> -	OFFSET(CPUINFO_x86_vendor, cpuinfo_x86, x86_vendor);
> -	OFFSET(CPUINFO_x86_model, cpuinfo_x86, x86_model);
> -	OFFSET(CPUINFO_x86_stepping, cpuinfo_x86, x86_stepping);
> -	OFFSET(CPUINFO_cpuid_level, cpuinfo_x86, cpuid_level);
> -	OFFSET(CPUINFO_x86_capability, cpuinfo_x86, x86_capability);
> -	OFFSET(CPUINFO_x86_vendor_id, cpuinfo_x86, x86_vendor_id);
> -	BLANK();
> -

This is needed so that we can run (well, build) the setup_force_cpu_cap 
macro on x86-64 too, right?

Could you please split out this portion into a separate patch, to 
simplify the more dangerous half of the patch?

> -	if (IS_ENABLED(CONFIG_X86_5LEVEL) && (native_read_cr4() & X86_CR4_LA57))
> -		setup_force_cpu_cap(X86_FEATURE_5LEVEL_PAGING);

> +#ifdef CONFIG_X86_5LEVEL
> +	/*
> +	 * Set the X86_FEATURE_5LEVEL_PAGING capability before calling into the
> +	 * C code, so that it is guaranteed to have a consistent view of any
> +	 * global pseudo-constants that are derived from pgtable_l5_enabled().
> +	 */
> +	mov	%cr4, %rax
> +	btl	$X86_CR4_LA57_BIT, %eax
> +	jnc	0f
> +
> +	setup_force_cpu_cap X86_FEATURE_5LEVEL_PAGING
> +0:
> +#endif

Nice!

Thanks,

	Ingo