From: "Ahmed S. Darwish" <darwi@linutronix.de>
To: David Woodhouse <dwmw2@infradead.org>
Cc: Dave Hansen <dave.hansen@intel.com>,
Borislav Petkov <bp@alien8.de>, Ingo Molnar <mingo@redhat.com>,
Dave Hansen <dave.hansen@linux.intel.com>,
Thomas Gleixner <tglx@linutronix.de>,
Andrew Cooper <andrew.cooper3@citrix.com>,
"H. Peter Anvin" <hpa@zytor.com>,
Sean Christopherson <seanjc@google.com>,
Peter Zijlstra <peterz@infradead.org>,
Sohil Mehta <sohil.mehta@intel.com>,
John Ogness <john.ogness@linutronix.de>,
x86@kernel.org, x86-cpuid@lists.linux.dev,
LKML <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v4 28/34] x86/cacheinfo: Use parsed CPUID(0x80000005) and CPUID(0x80000006)
Date: Mon, 18 Aug 2025 19:00:03 +0200 [thread overview]
Message-ID: <aKNcE7D_s9D7spvR@lx-t490> (raw)
In-Reply-To: <e9620899cc52cd45c090c939898be8787ff84df6.camel@infradead.org>
Hi!
On Mon, 18 Aug 2025, David Woodhouse wrote:
>
> How about automatically building the cast into the macro invocation...
>
> #define cpuid_leaf(c, l) ((struct cpuid_leaf_ ## l *)__cpuid_leaf(c, l)
> #define cpuid_lead_index(c, l, i) ((struct cpuid_leaf_ ## l ## _ ## i) __cpuid_leaf_index(c, l, i)
>
There are zero casts needed by this model. From patch 07/34 ("x86/cpuid:
Introduce a centralized CPUID data model"), the access CPUID parser APIs
just dissolve into:
const struct leaf_0x7_0 *l7_0;
const struct leaf_0x7_1 *l7_1;
l7_0 = cpuid_subleaf(c, 0x7, 0);
| | └────────┐
| └─────────┐ |
* * *
&c.cpuid.leaf_0x7_0[0]
l7_1 = cpuid_subleaf(c, 0x7, 1);
| | └────────┐
| └─────────┐ |
* * *
&c.cpuid.leaf_0x7_1[0]
where, for example, the data type of 'c.cpuid.leaf_0x7_0[0]' is native
'struct leaf_0x7_0', and so on.
The per-CPU CPUID table(s) are built in a /fully-typed/ form:
struct leaf_0x0_0 leaf_0x0_0[1];
struct leaf_0x1_0 leaf_0x1_0[1];
struct leaf_0x2_0 leaf_0x2_0[1];
struct leaf_0x4_0 leaf_0x4_0[8];
struct leaf_0x16_0 leaf_0x16_0[1];
struct leaf_0x80000000_0 leaf_0x80000000_0[1];
struct leaf_0x80000005_0 leaf_0x80000005_0[1];
struct leaf_0x80000006_0 leaf_0x80000006_0[1];
struct leaf_0x8000001d_0 leaf_0x8000001d_0[8];
Then, the exported CPUID parser APIs do some CPP tokenization magic to
access such fully-typed data -- no casting needed.
The only exception is raw EAX->EDX register access:
/**
* cpuid_leaf_regs() - Access parsed CPUID data in raw format
* @_cpuinfo: CPU capability structure reference ('struct cpuinfo_x86')
* @_leaf: CPUID leaf, in compile-time 0xN format
*
* Similar to cpuid_leaf(), but returns a raw 'struct cpuid_regs' pointer to
* the parsed CPUID data instead of a "typed" <cpuid/leaf_types.h> pointer.
*/
#define cpuid_leaf_regs(_cpuinfo, _leaf) \
((struct cpuid_regs *)(cpuid_leaf(_cpuinfo, _leaf)))
But the usage of this raw-access API is very limited. This is by design,
as one of the purpose of this work was to ensure type safety and avoid
call-site bit fiddling.
Thanks!
--
Ahmed S. Darwish
Linutronix GmbH
next prev parent reply other threads:[~2025-08-18 17:00 UTC|newest]
Thread overview: 55+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-15 7:01 [PATCH v4 00/34] x86: Introduce a centralized CPUID data model Ahmed S. Darwish
2025-08-15 7:01 ` [PATCH v4 01/34] x86/cpuid: Remove transitional <asm/cpuid.h> header Ahmed S. Darwish
2025-08-15 10:11 ` [tip: x86/urgent] " tip-bot2 for Ahmed S. Darwish
2025-08-15 15:22 ` tip-bot2 for Ahmed S. Darwish
2025-08-15 7:01 ` [PATCH v4 02/34] ASoC: Intel: avs: Include CPUID header at file scope Ahmed S. Darwish
2025-08-18 14:56 ` Borislav Petkov
2025-08-18 15:14 ` Ahmed S. Darwish
2025-08-15 7:01 ` [PATCH v4 03/34] treewide: Explicitly include the x86 CPUID headers Ahmed S. Darwish
2025-08-15 7:01 ` [PATCH v4 04/34] x86/cpu: <asm/processor.h>: Do not include the CPUID API header Ahmed S. Darwish
2025-08-15 7:01 ` [PATCH v4 05/34] x86/cpuid: Rename cpuid_leaf()/cpuid_subleaf() APIs Ahmed S. Darwish
2025-08-15 7:01 ` [PATCH v4 06/34] x86/cpuid: Introduce <asm/cpuid/leaf_types.h> Ahmed S. Darwish
2025-08-25 14:18 ` Borislav Petkov
2025-08-25 14:56 ` Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 07/34] x86/cpuid: Introduce a centralized CPUID data model Ahmed S. Darwish
2025-08-15 15:34 ` Sean Christopherson
2025-08-18 13:49 ` Ahmed S. Darwish
2025-08-18 18:44 ` Sean Christopherson
2025-08-18 19:54 ` Ahmed S. Darwish
2025-08-18 21:29 ` Sean Christopherson
2025-08-19 13:10 ` Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 08/34] x86/cpuid: Introduce a centralized CPUID parser Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 09/34] x86/cpu: Use parsed CPUID(0x0) Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 10/34] x86/lib: Add CPUID(0x1) CPU family and model calculation Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 11/34] x86/cpu: Use parsed CPUID(0x1) Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 12/34] x86/cpuid: Parse CPUID(0x80000000) Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 13/34] x86/cpu: Use parsed CPUID(0x80000000) Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 14/34] x86/cpuid: Introduce a CPUID leaf x86 vendor table Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 15/34] x86/cpuid: Introduce CPUID parser debugfs interface Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 16/34] x86/cpuid: Parse CPUID(0x2) Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 17/34] x86/cpuid: Warn once on invalid CPUID(0x2) iteration count Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 18/34] x86/cpuid: Introduce parsed CPUID(0x2) API Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 19/34] x86/cpu: Use parsed CPUID(0x2) Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 20/34] x86/cacheinfo: " Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 21/34] x86/cpuid: Remove direct CPUID(0x2) query API Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 22/34] x86/cpuid: Parse 'deterministic cache parameters' CPUID leaves Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 23/34] x86/cacheinfo: Pass a 'struct cpuinfo_x86' refrence to CPUID(0x4) code Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 24/34] x86/cacheinfo: Use parsed CPUID(0x4) Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 25/34] x86/cacheinfo: Use parsed CPUID(0x8000001d) Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 26/34] x86/cpuid: Parse CPUID(0x80000005) and CPUID(0x80000006) Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 27/34] x86/cacheinfo: Use auto-generated data types Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 28/34] x86/cacheinfo: Use parsed CPUID(0x80000005) and CPUID(0x80000006) Ahmed S. Darwish
2025-08-15 15:25 ` Dave Hansen
2025-08-18 15:38 ` Ahmed S. Darwish
2025-08-18 15:52 ` David Woodhouse
2025-08-18 17:00 ` Ahmed S. Darwish [this message]
2025-08-15 7:02 ` [PATCH v4 29/34] x86/amd_nb: Trickle down 'struct cpuinfo_x86' reference Ahmed S. Darwish
2025-08-18 2:54 ` kernel test robot
2025-08-18 14:47 ` Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 30/34] x86/cpuid: Use parsed CPUID(0x80000006) Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 31/34] x86/cpu: Rescan CPUID table after PSN disable Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 32/34] x86/cpu: Rescan CPUID table after unlocking full CPUID range Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 33/34] x86/cpuid: Parse CPUID(0x16) Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 34/34] x86/tsc: Use parsed CPUID(0x16) Ahmed S. Darwish
2025-08-16 9:59 ` [PATCH v4 00/34] x86: Introduce a centralized CPUID data model David Woodhouse
2025-08-18 16:37 ` Ahmed S. Darwish
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