From: "Ahmed S. Darwish" <darwi@linutronix.de>
To: Sean Christopherson <seanjc@google.com>
Cc: Borislav Petkov <bp@alien8.de>, Ingo Molnar <mingo@redhat.com>,
Dave Hansen <dave.hansen@linux.intel.com>,
Thomas Gleixner <tglx@linutronix.de>,
Andrew Cooper <andrew.cooper3@citrix.com>,
"H. Peter Anvin" <hpa@zytor.com>,
David Woodhouse <dwmw2@infradead.org>,
Peter Zijlstra <peterz@infradead.org>,
Sohil Mehta <sohil.mehta@intel.com>,
John Ogness <john.ogness@linutronix.de>,
x86@kernel.org, x86-cpuid@lists.linux.dev,
LKML <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v4 07/34] x86/cpuid: Introduce a centralized CPUID data model
Date: Mon, 18 Aug 2025 21:54:32 +0200 [thread overview]
Message-ID: <aKOE-FzHy0JatC8I@lx-t490> (raw)
In-Reply-To: <aKN0debsio7ocitW@google.com>
Hi,
On Mon, 18 Aug 2025, Sean Christopherson wrote:
>
> Why not? Like C structs, there can only be one variable sized array, i.e. there
> can't be multiple "n" subleafs. If the concern is calling __cpuid_subleaf_n()
> with i < start, then I don't see how embedding start in the structure name helps
> in any way, since 'i' isn't a compile-time constant and so needs to be checked at
> runtime no matter what.
>
Hmmm...
I can indeed find the offset of the dynamic 'leaf_0x.._n' subleaf storage
by CPP tokenization, since the CPUID table will be in the form:
struct leaf_0x0_0 leaf_0x0_0[1];
struct leaf_0x1_0 leaf_0x1_0[1];
struct leaf_0x2_0 leaf_0x2_0[1];
struct leaf_0x4_0 leaf_0x4_0[8];
struct leaf_0xd_0 leaf_0xd_0[1];
struct leaf_0xd_1 leaf_0xd_1[1];
struct leaf_0xd_n leaf_0xd_n[62];
struct leaf_0x16_0 leaf_0x16_0[1];
struct leaf_0x80000000_0 leaf_0x80000000_0[1];
struct leaf_0x80000005_0 leaf_0x80000005_0[1];
struct leaf_0x80000006_0 leaf_0x80000006_0[1];
struct leaf_0x8000001d_0 leaf_0x8000001d_0[8];
I was also kinda worried about the different subleaf semantics:
struct leaf_0x4_n => starts from subleaf 0
struct leaf_0xd_n => starts from subleaf 2
But, hopefully it would be clear when looking at the generated header in
total.
Still: for the API you're proposing, I'll need to generate an error for
things like:
cpuid_subleaf_n(c, 0xd, 0);
cpuid_subleaf_n(c, 0xd, 1);
which could not have happened in the API I proposed earlier. But... I
can let the XML files generate some symbols in the form:
LEAF_0x4_n_MIN_SUBLEAF 0
LEAF_0xd_n_MIN_SUBLEAF 2
and generate an error (once) if the passed subleaf is less than the
minimum. I can also generate that error (once) at compile-time if the
given subleaf was a compile-time constant.
Maybe there's a cleaner way for detecting this subleaf lower-bound error,
I will see; what's important now is the API implementation feasibility...
=> Then, we can have:
API Summary
~~~~~~~~~~~
For CPUID leaves with static subleaves:
cpuid_leaf(_cpuinfo, _leaf)
cpuid_subleaf(_cpuinfo, _leaf, _subleaf)
For CPUID leaves with dynamic subleaves:
cpuid_subleaf_n(_cpuinfo, _leaf, _idx)
New SGX snippet
~~~~~~~~~~~~~~~
At arch/x86/kernel/cpu/sgx/main.c:
const struct leaf_0x12_n *l;
for (int i = 0; i < ARRAY_SIZE(sgx_epc_sections); i++) {
l = cpuid_subleaf_n(0x12, i + SGX_CPUID_EPC);
// Use l->subleaf_type, etc. as appropriate
}
New KVM snippet
~~~~~~~~~~~~~~~
At arch/x86/kvm/cpuid.c:
const struct leaf_0xd_n *l;
for (int i = XFEATURE_YMM; i < ARRAY_SIZE(xstate_sizes); i++) {
l = cpuid_subleaf_n(c, 0xd, i);
// Use l->xsave_sz, l->xsave_offset, etc. as appropriate
}
This looks much better indeed; for both KVM and SGX :-)
Thanks a lot!
--
Ahmed S. Darwish
Linutronix GmbH
next prev parent reply other threads:[~2025-08-18 19:54 UTC|newest]
Thread overview: 55+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-15 7:01 [PATCH v4 00/34] x86: Introduce a centralized CPUID data model Ahmed S. Darwish
2025-08-15 7:01 ` [PATCH v4 01/34] x86/cpuid: Remove transitional <asm/cpuid.h> header Ahmed S. Darwish
2025-08-15 10:11 ` [tip: x86/urgent] " tip-bot2 for Ahmed S. Darwish
2025-08-15 15:22 ` tip-bot2 for Ahmed S. Darwish
2025-08-15 7:01 ` [PATCH v4 02/34] ASoC: Intel: avs: Include CPUID header at file scope Ahmed S. Darwish
2025-08-18 14:56 ` Borislav Petkov
2025-08-18 15:14 ` Ahmed S. Darwish
2025-08-15 7:01 ` [PATCH v4 03/34] treewide: Explicitly include the x86 CPUID headers Ahmed S. Darwish
2025-08-15 7:01 ` [PATCH v4 04/34] x86/cpu: <asm/processor.h>: Do not include the CPUID API header Ahmed S. Darwish
2025-08-15 7:01 ` [PATCH v4 05/34] x86/cpuid: Rename cpuid_leaf()/cpuid_subleaf() APIs Ahmed S. Darwish
2025-08-15 7:01 ` [PATCH v4 06/34] x86/cpuid: Introduce <asm/cpuid/leaf_types.h> Ahmed S. Darwish
2025-08-25 14:18 ` Borislav Petkov
2025-08-25 14:56 ` Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 07/34] x86/cpuid: Introduce a centralized CPUID data model Ahmed S. Darwish
2025-08-15 15:34 ` Sean Christopherson
2025-08-18 13:49 ` Ahmed S. Darwish
2025-08-18 18:44 ` Sean Christopherson
2025-08-18 19:54 ` Ahmed S. Darwish [this message]
2025-08-18 21:29 ` Sean Christopherson
2025-08-19 13:10 ` Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 08/34] x86/cpuid: Introduce a centralized CPUID parser Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 09/34] x86/cpu: Use parsed CPUID(0x0) Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 10/34] x86/lib: Add CPUID(0x1) CPU family and model calculation Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 11/34] x86/cpu: Use parsed CPUID(0x1) Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 12/34] x86/cpuid: Parse CPUID(0x80000000) Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 13/34] x86/cpu: Use parsed CPUID(0x80000000) Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 14/34] x86/cpuid: Introduce a CPUID leaf x86 vendor table Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 15/34] x86/cpuid: Introduce CPUID parser debugfs interface Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 16/34] x86/cpuid: Parse CPUID(0x2) Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 17/34] x86/cpuid: Warn once on invalid CPUID(0x2) iteration count Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 18/34] x86/cpuid: Introduce parsed CPUID(0x2) API Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 19/34] x86/cpu: Use parsed CPUID(0x2) Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 20/34] x86/cacheinfo: " Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 21/34] x86/cpuid: Remove direct CPUID(0x2) query API Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 22/34] x86/cpuid: Parse 'deterministic cache parameters' CPUID leaves Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 23/34] x86/cacheinfo: Pass a 'struct cpuinfo_x86' refrence to CPUID(0x4) code Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 24/34] x86/cacheinfo: Use parsed CPUID(0x4) Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 25/34] x86/cacheinfo: Use parsed CPUID(0x8000001d) Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 26/34] x86/cpuid: Parse CPUID(0x80000005) and CPUID(0x80000006) Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 27/34] x86/cacheinfo: Use auto-generated data types Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 28/34] x86/cacheinfo: Use parsed CPUID(0x80000005) and CPUID(0x80000006) Ahmed S. Darwish
2025-08-15 15:25 ` Dave Hansen
2025-08-18 15:38 ` Ahmed S. Darwish
2025-08-18 15:52 ` David Woodhouse
2025-08-18 17:00 ` Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 29/34] x86/amd_nb: Trickle down 'struct cpuinfo_x86' reference Ahmed S. Darwish
2025-08-18 2:54 ` kernel test robot
2025-08-18 14:47 ` Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 30/34] x86/cpuid: Use parsed CPUID(0x80000006) Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 31/34] x86/cpu: Rescan CPUID table after PSN disable Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 32/34] x86/cpu: Rescan CPUID table after unlocking full CPUID range Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 33/34] x86/cpuid: Parse CPUID(0x16) Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 34/34] x86/tsc: Use parsed CPUID(0x16) Ahmed S. Darwish
2025-08-16 9:59 ` [PATCH v4 00/34] x86: Introduce a centralized CPUID data model David Woodhouse
2025-08-18 16:37 ` Ahmed S. Darwish
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