Re: [PATCH v2 2/3] pwm: rp1: Add RP1 PWM controller driver

[Andrea della Porta <andrea.porta@suse.com>]

Hi Uwe,

On 12:50 Fri 17 Apr     , Uwe Kleine-König wrote:
> Hello Andrea,
>
 
<...snip...>
 
> > I stand corrected here: after some more investigation it seems that only the
> > enable/disable (plus osme other not currently used registers) depends on the
> > global update flag, while the period and duty per-channel registers are
> > independtly updatable while they are latched on the end of (specific channel)
> > period strobe.
> > I'd say that this should avoid any cross-channel glitches since they are managed
> > independently. Unfortunately I'm not able to test this with my current (and
> > rather old) equipment, this would require at least an external trigger channel.
> > Regarding the setup of a new value exactly during the strobe: I think this is
> > quite hard to achieve.
> 
> To sum up: period and duty_cycle changes might result in glitches unless
> the channel is disabled. This is ok, please just document it.

Maybe the glitch can occur if we're changing period and duty exactly during
the strobe, unless the register writing is somehow in sync with the PWM clock.
Disabling the channel immediately stops any execution and the line goes suddenly
low (if polarity is normal, otherwise stays high). See also next.

> 
> The purpose of the update flag then is only to start several channels in
> sync?

Citing the datasheet:

"To prevent mis-sampling of multi-bit bus signals in the PWM clock domain,
this bit (SET_UPDATE) should be used to trigger a settings update. This
ensures that all PWM channel settings update on the same PWM clock cycle."

From my testing though, channels can be started in sync only if they have the
same period. I'll add a comment for all this, and other edge cases.

> What happens if sync is asserted while a disabled channel didn't
> complete the last period yet?

The output stops immediately without waiting for the current period to finish.

> 
> Maybe it's worth to test the following procedure for updating duty and
> period:
> 
> 	disable channel
> 	configure duty
> 	configure period
> 	enable
> 	set update flag
> 
> Assumint disable is delayed until the end of the currently running
> period, the effect of this procedure might be that no glitch happens if
> the update flag is asserted before the currently running period ends and
> the anormality is reduced to a longer inactive state if the updates are
> not that lucky (in contrast to more severe glitches).

The disable isn't delayed as explained above. Setting just the new period/duty
(which do not depend on the sync bit) correctly waits for the end of the current
period without noticeable glitches (tested with a scope).

> 
> If you can configure a short and a long period that is distinguishable
> "manually" with an LED I think this should be testable even without
> further equipment.
> 
> > > > > > +	if (ticks > U32_MAX)
> > > > > > +		ticks = U32_MAX;
> > > > > > +	wfhw->period_ticks = ticks;
> > > > > 
> > > > > What happens if wf->period_length_ns > 0 but ticks == 0?
> > > > 
> > > > I've added a check, returning 1 to signal teh round-up, and a minimum tick of 1
> > > > in this case.
> > > 
> > > Sounds good. Are you able to verify that there is no +1 missing in the
> > > calculation, e.g. using 1 as register value really gives you a period of
> > > 1 tick and not 2?
> > 
> > You are right. The scope reveals there's always one extra (low signal) tick at the
> > end of each period.
> 
> So the hardware cannot do 100% relative duty, right? Please document
> that.
> 
> > Let's say that teh user want 10 tick period, we have to use
> > 9 instead to account for the extra tick at the end, so that the complete period
> > contains that extra tick?
> 
> I would describe that a bit differently, but in general: yes.
> 
> The more straight forward description is that setting
> 
> 	RP1_PWM_RANGE(pwm->hwpwm) := x
> 
> results in a period of x + 1 ticks.

Exactly. So whatever the user request I have to subtract one from the value
to be written to the RANGE register.

> 
> > This also means that if we ask for 100% duty cycle, the output waveform will
> > have the high part of the signal lasting one tick less than expected.a I guess
> > this is the accepted compromise.
> 
> I assume you considered something like:
> 
> 	RP1_PWM_RANGE(pwm->hwpwm) := 17
> 	RP1_PWM_DUTY(pwm->hwpwm) := 18
> 
> to get a 100% relative duty?

Ah right! It's working fine and I've got 100% duty. So at hw register level
the duty can be greater that the period.

> 
> If this doesn't work that means that this has to be formalized in the
> callbacks. That is the fromhw function has to always report
> duty_length_ns less than period_length_ns.

No need, it's working indeed.

> 
> > OTOH, the minimum tick period would be 2 tick, less than that will otherwise
> > degenerate in a disabled channel.
> 
> It's expected that in general for a period_length of 1 tick you can only
> have 0% and 100% relative duty. IIUC for this hardware you cannot do the
> 100% case so there is only a single valid duty_length for period_length
> = 1 tick.

Minimum tick confirmed to be 1.

> 
> I think it would be more complicated to consistently filter out
> period_length = 1 tick in the driver than to just accept the conceptual
> limitations. (Otherwise: What would you report in the fromhw callback if
> period_length = 1 tick is configured in wfhw? Would you refuse to commit
> that wfhw to hardware in .write_waveform()? The pwm core handles that
> just fine and consumers have all the means to detect and prevent that if
> they care enough.)
> 
> > > > > On remove you miss to balance the call to clk_prepare_enable() (if no
> > > > > failed call to clk_prepare_enable() in rp1_pwm_resume() happend).
> > > > 
> > > > Since this driver now exports a syscon, it's only builtin (=Y) so
> > > > it cannot be unloaded.
> > > > I've also avoided the .remove callback via .suppress_bind_attrs.
> > > 
> > > Oh no, please work cleanly here and make the driver unbindable. This
> > > yields better code quality and also helps during development and
> > > debugging.
> > 
> > I wish to, but the issue here is that this driver exports a syscon via 
> > of_syscon_register_regmap() which I think doesn't have the unregister
> > counterpart. So the consumer will break in case we can unbind/unload
> > the module and the syscon will leak. 
> > If you have any alternative I'll be glad to discuss.
> 
> My (not so well articulated) point is: Please be stringent about clock
> handling to not bank up technical dept more than necessary and such that
> the driver can be made unbindable if and when syscons grow
> that feature. Optionally wail at the syscon guys :-)

Hmmm not sure I've understood your point: is it a requirement that the driver
must be unbindable? In this case I should avoid registering the syscon. Or
should I just provide a .remove callback in case there will be a way to
unregister the syscon (even if this callback will not be called as of now)?

Many thanks,
Andrea

> 
> Best regards
> Uwe