Re: [PATCH v2 1/5] KVM: SVM: Disable x2AVIC RDMSR interception for MSRs KVM actually supports

[Naveen N Rao <naveen@kernel.org>]

On Thu, May 07, 2026 at 07:27:11AM -0700, Sean Christopherson wrote:
> On Thu, May 07, 2026, Naveen N Rao wrote:
> > On Wed, May 06, 2026 at 11:47:42AM -0700, Sean Christopherson wrote:
> 
> > LVTT reads will now be allowed and should be returned from the backing page.  
> > I'm guessing this is fine and that the hardware won't validate it as 
> > LVTT may have TSC Deadline enabled (for emulation).
> 
> Ya, confirmed via the KUT test:
> 
> diff --git x86/apic.c x86/apic.c
> index 0a52e9a4..b91e8500 100644
> --- x86/apic.c
> +++ x86/apic.c
> @@ -569,6 +569,9 @@ static inline void apic_change_mode(unsigned long new_mode)
>  
>         lvtt = apic_read(APIC_LVTT);
>         apic_write(APIC_LVTT, (lvtt & ~APIC_LVT_TIMER_MASK) | new_mode);
> +
> +       lvtt = apic_read(APIC_LVTT);
> +       report((lvtt & APIC_LVT_TIMER_MASK) == new_mode, "LVTT mode switch");
>  }
>  
>  static void test_apic_change_mode(void)
> 
> And given that AVIC (!x2APIC mode) says that reads are allowed, I don't see how
> hardware could do anything differently.

Indeed, I additionally did:

diff --git a/x86/apic.c b/x86/apic.c
index b45fc9c1..b0902b2d 100644
--- a/x86/apic.c
+++ b/x86/apic.c
@@ -42,11 +42,13 @@ static void __test_tsc_deadline_timer(void)

 static int enable_tsc_deadline_timer(void)
 {
-       uint32_t lvtt;
+       uint32_t lvtt, new_mode;

        if (this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) {
                lvtt = APIC_LVT_TIMER_TSCDEADLINE | TSC_DEADLINE_TIMER_VECTOR;
                apic_write(APIC_LVTT, lvtt);
+               new_mode = apic_read(APIC_LVTT);
+               report((new_mode & APIC_LVT_TIMER_MASK) == (lvtt & APIC_LVT_TIMER_MASK), "LVTT TSC Deadline mode");
                return 1;
        } else {
                return 0;


... and that works fine.


Thanks,
Naveen