Re: [PATCH] iommu/arm-smmu-v3-sva: Enable Hardware Access and Hardware Dirty bits

[Nicolin Chen <nicolinc@nvidia.com>]

On Fri, May 08, 2026 at 03:24:32PM +0100, Robin Murphy wrote:
> On 2026-05-08 2:57 pm, Pranjal Shrivastava wrote:
> > I see, so IIUC, you mean if IS_ENABLED(CONFIG_ARM64_HW_AFDBM) but CPU
> > doesn't enable HTTU, it is perfectly safe to let the SMMU do HTT updates,
> > Since the fault handlers are already expecting HW-triggered updates?
> > 
> > Which means our check would be something like:
> > 
> >     if (IS_ENABLED(CONFIG_ARM64_HW_AFDBM) {
> >     	if (smmu->features & FEAT_HA)
> > 	 ...
> >     }
> > 
> > instead of cpu_has_hw_af()?
> 
> Hmm, looking closer, cpu_has_hw_af() is the thing which actually influences
> mm behaviour (via arch_has_hw_pte_young and arch_wants_old_prefaulted_pte),
> and that can still be false at runtime if ARM64_HW_AFDBM is enabled but any
> CPU doesn't support HAFDBS, so perhaps you were right the first time :)

IIUIC, v2 should be:

+		/*
+		 * Enable Hardware Access and Dirty updates (DBM) if supported by
+		 * both the SMMU and the CPU. It is unsafe to enable SMMU's HTTU,
+		 * if the CPU does not support it as it bypasses mm page aging.
+		 */
+		if (cpu_has_hw_af()) {
+			if (master->smmu->features & ARM_SMMU_FEAT_HA)
+				target->data[0] |= cpu_to_le64(CTXDESC_CD_0_TCR_HA);
+			if (master->smmu->features & ARM_SMMU_FEAT_HD)
+				target->data[0] |= cpu_to_le64(CTXDESC_CD_0_TCR_HD);
+		}

Thanks
Nicolin