[PATCH RFC 0/2] regulator: raa215300: add support for configurable 32kHz clock output

[PATCH RFC 0/2] regulator: raa215300: add support for configurable 32kHz clock output

[Josua Mayer]

Add driver support and extend bindings for Renesas RAA215300 PMIC 32kHz
clock output feature on pin MPIO2.

Signed-off-by: Josua Mayer <josua@solid-run.com>
---
Josua Mayer (2):
      regulator: dt-bindings: raa215300: add clock output
      regulator: raa215300: add support for configurable 32kHz clock output

 .../bindings/regulator/renesas,raa215300.yaml      |   6 +
 drivers/regulator/raa215300.c                      | 132 +++++++++++++++++++++
 2 files changed, 138 insertions(+)
---
base-commit: 254f49634ee16a731174d2ae34bc50bd5f45e731
change-id: 20260502-raa215300-clkout-c3ed84024888

Best regards,
-- 
Josua Mayer <josua@solid-run.com>

[PATCH RFC 1/2] regulator: dt-bindings: raa215300: add clock output

[Josua Mayer]

Renesas RAA215300 can generate a 32kHz clock on MPIO2 pin.

MPIO2 is a multi-function pin, with clkout being one of the functions
and exclusively available on this pin.

It supports prepare, unprepare and set rate (32k divide by powers of 2).

Add clock-cells and clock-output-names properties so that other dt nodes
can consume this clock.

Signed-off-by: Josua Mayer <josua@solid-run.com>
---
 Documentation/devicetree/bindings/regulator/renesas,raa215300.yaml | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/regulator/renesas,raa215300.yaml b/Documentation/devicetree/bindings/regulator/renesas,raa215300.yaml
index 97cff71d29677..b6b6b76b16d30 100644
--- a/Documentation/devicetree/bindings/regulator/renesas,raa215300.yaml
+++ b/Documentation/devicetree/bindings/regulator/renesas,raa215300.yaml
@@ -40,6 +40,12 @@ properties:
   interrupts:
     maxItems: 1
 
+  "#clock-cells":
+    const: 0
+
+  clock-output-names:
+    maxItems: 1
+
   clocks:
     description: |
       The clocks are optional. The RTC is disabled, if no clocks are

-- 
2.51.0

Re: [PATCH RFC 1/2] regulator: dt-bindings: raa215300: add clock output

[Mark Brown]

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On Sat, May 02, 2026 at 06:07:04PM +0200, Josua Mayer wrote:

> +  "#clock-cells":
> +    const: 0
> +
> +  clock-output-names:
> +    maxItems: 1
> +
>    clocks:
>      description: |
>        The clocks are optional. The RTC is disabled, if no clocks are

Should there be a requirement for an input clock if a clock output is
specified?

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Re: [PATCH RFC 1/2] regulator: dt-bindings: raa215300: add clock output

[Josua Mayer]

Am 03.05.26 um 02:57 schrieb Mark Brown:
> On Sat, May 02, 2026 at 06:07:04PM +0200, Josua Mayer wrote:
>
>> +  "#clock-cells":
>> +    const: 0
>> +
>> +  clock-output-names:
>> +    maxItems: 1
>> +
>>    clocks:
>>      description: |
>>        The clocks are optional. The RTC is disabled, if no clocks are
> Should there be a requirement for an input clock if a clock output is
> specified?

The input clock is same as for RTC, so I suppose yes.

In that case, which property should the dependency be based on?
#clock-cells ?
clock-output-names?

clock-output-names is optional, so I think #clock-cells is the only option.

Is it important to model this dependency?
Or is it sufficient that driver returns an error when clock is missing?

Re: [PATCH RFC 1/2] regulator: dt-bindings: raa215300: add clock output

[Geert Uytterhoeven]

Hi Josua,

On Sat, 2 May 2026 at 18:07, Josua Mayer <josua@solid-run.com> wrote:
> Renesas RAA215300 can generate a 32kHz clock on MPIO2 pin.
>
> MPIO2 is a multi-function pin, with clkout being one of the functions
> and exclusively available on this pin.
>
> It supports prepare, unprepare and set rate (32k divide by powers of 2).
>
> Add clock-cells and clock-output-names properties so that other dt nodes
> can consume this clock.
>
> Signed-off-by: Josua Mayer <josua@solid-run.com>

Thanks for your patch!

> --- a/Documentation/devicetree/bindings/regulator/renesas,raa215300.yaml
> +++ b/Documentation/devicetree/bindings/regulator/renesas,raa215300.yaml
> @@ -40,6 +40,12 @@ properties:
>    interrupts:
>      maxItems: 1
>
> +  "#clock-cells":
> +    const: 0
> +
> +  clock-output-names:
> +    maxItems: 1

Please no more new clock-output-names.

> +
>    clocks:
>      description: |
>        The clocks are optional. The RTC is disabled, if no clocks are
>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH RFC 2/2] regulator: raa215300: add support for configurable 32kHz clock output

[Josua Mayer]

Renesas RA215300 PMIC can be configured to output a 32kHz clock on its
multi-purpose MPIO2 pin.

There are in total 6 configurable multi-purpose pins, however only one
of them supports outputting a clock in one specific configuration.

Register this clock with common clock framework, implementing prepare,
unprepare and set_rate.

Signed-off-by: Josua Mayer <josua@solid-run.com>
---
 drivers/regulator/raa215300.c | 132 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 132 insertions(+)

diff --git a/drivers/regulator/raa215300.c b/drivers/regulator/raa215300.c
index 6982565c8aa4c..e66bd0404421b 100644
--- a/drivers/regulator/raa215300.c
+++ b/drivers/regulator/raa215300.c
@@ -27,6 +27,24 @@
 #define RAA215300_INT_MASK_6	0x68
 
 #define RAA215300_REG_BLOCK_EN	0x6c
+#define RAA215300_REG_MPIO2_POWER_OFF			0x77
+#define RAA215300_MPIO2_POWER_OFF_DELAY			GENMASK(6, 0)
+#define RAA215300_REG_MPIO2_CONFIG			0x8c
+#define RAA215300_MPIO2_CONFIG_POLARITY_ACTIVE_HIGH	BIT(5)
+#define RAA215300_MPIO2_CONFIG_TYPE			GENMASK(4, 3)
+#define RAA215300_MPIO2_CONFIG_TYPE_HIGH_IMPEDANCE	(0 << 3)
+#define RAA215300_MPIO2_CONFIG_TYPE_OPEN_DRAIN		(1 << 1)
+#define RAA215300_MPIO2_CONFIG_TYPE_OPEN_SOURCE		(2 << 2)
+#define RAA215300_MPIO2_CONFIG_TYPE_CMOS		(3 << 3)
+#define RAA215300_MPIO2_CONFIG_FUNCTION			GENMASK(2, 0)
+#define RAA215300_MPIO2_CONFIG_FUNCTION_NONE		0
+#define RAA215300_MPIO2_CONFIG_FUNCTION_CLKOUT		1
+#define RAA215300_MPIO2_CONFIG_FUNCTION_EXT_VR_PGOOD	2
+#define RAA215300_MPIO2_CONFIG_FUNCTION_GPI		3
+#define RAA215300_MPIO2_CONFIG_FUNCTION_GPI_PGOOD	4
+#define RAA215300_MPIO2_CONFIG_FUNCTION_RESETOUT	5
+#define RAA215300_MPIO2_CONFIG_FUNCTION_EXT_VR_EN	6
+#define RAA215300_MPIO2_CONFIG_FUNCTION_GPO		7
 #define RAA215300_HW_REV	0xf8
 
 #define RAA215300_INT_MASK_1_ALL	GENMASK(5, 0)
@@ -49,6 +67,117 @@ static void raa215300_rtc_unregister_device(void *data)
 	i2c_unregister_device(data);
 }
 
+struct raa215300_clk {
+	struct clk_hw hw;
+	struct regmap *regmap;
+};
+
+#define to_raa215300_clk(_hw) container_of(_hw, struct raa215300_clk, hw)
+
+static int raa215300_clk_prepare(struct clk_hw *hw)
+{
+	struct raa215300_clk *clk = to_raa215300_clk(hw);
+	/* clkout function must configure mpio2 as full cmos output */
+	const u8 ena_val = RAA215300_MPIO2_CONFIG_TYPE_CMOS |
+			   RAA215300_MPIO2_CONFIG_FUNCTION_CLKOUT;
+
+	return regmap_write(clk->regmap, RAA215300_REG_MPIO2_CONFIG, ena_val);
+}
+
+static void raa215300_clk_unprepare(struct clk_hw *hw)
+{
+	struct raa215300_clk *clk = to_raa215300_clk(hw);
+	const u8 dis_val = RAA215300_MPIO2_CONFIG_TYPE_HIGH_IMPEDANCE |
+			   RAA215300_MPIO2_CONFIG_FUNCTION_NONE;
+
+	regmap_write(clk->regmap, RAA215300_REG_MPIO2_CONFIG, dis_val);
+}
+
+static unsigned long raa215300_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
+{
+	struct raa215300_clk *clk = to_raa215300_clk(hw);
+	unsigned int val;
+
+	regmap_read(clk->regmap, RAA215300_REG_MPIO2_POWER_OFF, &val);
+	val &= RAA215300_MPIO2_POWER_OFF_DELAY;
+
+	return 32768 >> val;
+}
+
+static int raa215300_clk_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
+{
+	unsigned long r = 32768;
+
+	while (r > req->rate)
+		r >>= 1;
+
+	/* clamp at minimum rate 256Hz */
+	if (r < 256)
+		r = 256;
+
+	req->rate = r;
+	return 0;
+}
+
+static int raa215300_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate)
+{
+	struct raa215300_clk *clk = to_raa215300_clk(hw);
+	unsigned int val = 0;
+	unsigned long r = 32768;
+
+	while (r > rate) {
+		r >>= 1;
+		val++;
+	}
+
+	/* clamp at minimum rate 256Hz */
+	if (r < 256) {
+		r = 256;
+		val = 7;
+	}
+
+	return regmap_update_bits(clk->regmap, RAA215300_REG_MPIO2_POWER_OFF,
+				  RAA215300_MPIO2_POWER_OFF_DELAY, val);
+}
+
+static const struct clk_ops raa215300_clk_ops = {
+	.prepare = raa215300_clk_prepare,
+	.unprepare = raa215300_clk_unprepare,
+	.recalc_rate = raa215300_clk_recalc_rate,
+	.determine_rate = raa215300_clk_determine_rate,
+	.set_rate = raa215300_clk_set_rate,
+};
+
+static int raa215300_register_clk(struct device *dev, struct regmap *regmap)
+{
+	struct raa215300_clk *clk;
+	struct clk_init_data init;
+	int ret;
+
+	clk = devm_kzalloc(dev, sizeof(*clk), GFP_KERNEL);
+	if (!clk)
+		return -ENOMEM;
+
+	clk->hw.init = &init;
+	clk->regmap = regmap;
+
+	init.name = "raa215300-clkout";
+	init.ops = &raa215300_clk_ops;
+	init.flags = 0;
+	init.parent_names = NULL;
+	init.num_parents = 0;
+
+	/* optional override of the clockname */
+	of_property_read_string(dev->of_node, "clock-output-names", &init.name);
+
+	/* register the clock */
+	ret = devm_clk_hw_register(dev, &clk->hw);
+	if (ret)
+		return ret;
+
+	return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, &clk->hw);
+}
+
 static int raa215300_clk_present(struct i2c_client *client, const char *name)
 {
 	struct clk *clk;
@@ -166,6 +295,9 @@ static int raa215300_i2c_probe(struct i2c_client *client)
 					       rtc_client);
 		if (ret < 0)
 			return ret;
+
+		/* register mpio2 32k clkout in common clk framework */
+		raa215300_register_clk(dev, regmap);
 	}
 
 	return 0;

-- 
2.51.0

Re: [PATCH RFC 2/2] regulator: raa215300: add support for configurable 32kHz clock output

[Mark Brown]

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On Sat, May 02, 2026 at 06:07:05PM +0200, Josua Mayer wrote:
> Renesas RA215300 PMIC can be configured to output a 32kHz clock on its
> multi-purpose MPIO2 pin.

> There are in total 6 configurable multi-purpose pins, however only one
> of them supports outputting a clock in one specific configuration.

So there should be some pinmux support here then?  This is starting to
sound like a MFD...

> +#define RAA215300_MPIO2_POWER_OFF_DELAY			GENMASK(6, 0)

> +static unsigned long raa215300_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
> +{
> +	struct raa215300_clk *clk = to_raa215300_clk(hw);
> +	unsigned int val;
> +
> +	regmap_read(clk->regmap, RAA215300_REG_MPIO2_POWER_OFF, &val);
> +	val &= RAA215300_MPIO2_POWER_OFF_DELAY;
> +
> +	return 32768 >> val;
> +}

Given the mask above val could be up to 127?  If nothing else it'd be
good to have some validation.

> +		/* register mpio2 32k clkout in common clk framework */
> +		raa215300_register_clk(dev, regmap);

You should check the return value here.

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Re: [PATCH RFC 2/2] regulator: raa215300: add support for configurable 32kHz clock output

[Josua Mayer]

Am 03.05.26 um 02:57 schrieb Mark Brown:
> On Sat, May 02, 2026 at 06:07:05PM +0200, Josua Mayer wrote:
>> Renesas RA215300 PMIC can be configured to output a 32kHz clock on its
>> multi-purpose MPIO2 pin.
>> There are in total 6 configurable multi-purpose pins, however only one
>> of them supports outputting a clock in one specific configuration.
> So there should be some pinmux support here then?  This is starting to
> sound like a MFD...

If we want to treat it like an MFD, then the logical sub-devices would be:

1. pinmux/pinconf
2. clock
3. gpi, gpo

Then there is the RTC, which is not a sub-device because it has its own i2c
bus address, but its power controls inside the raa215300.

And there are some more complex regulator status and configuration registers.

Implemented is only the RTC ... and I would like to add the clock,
as it is used for Bluetooth on a SolidRun board.

My own particular use-case would also be satisfied by implementing
pinmux instead, as I need the 32kHz rate which is default.

>
>> +#define RAA215300_MPIO2_POWER_OFF_DELAY			GENMASK(6, 0)
>> +#define RAA215300_REG_MPIO2_CONFIG			0x8c
>
>> +static void raa215300_clk_unprepare(struct clk_hw *hw)
>> +{
>> +	struct raa215300_clk *clk = to_raa215300_clk(hw);
>> +	const u8 dis_val = RAA215300_MPIO2_CONFIG_TYPE_HIGH_IMPEDANCE |
>> +			   RAA215300_MPIO2_CONFIG_FUNCTION_NONE;
>> +
>> +	regmap_write(clk->regmap, RAA215300_REG_MPIO2_CONFIG, dis_val);
>> +}
Considering I use the pin configuration register to enable and disable the clock,
one might argue that if a pinmux driver exists, then the clock is always on
and does not support prepare/unprepare.

This would allow me to skip implemeting a clock subdevice,
and instead only implement a pinconf/mux driver.

Any opinions?

>> +static unsigned long raa215300_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
>> +{
>> +	struct raa215300_clk *clk = to_raa215300_clk(hw);
>> +	unsigned int val;
>> +
>> +	regmap_read(clk->regmap, RAA215300_REG_MPIO2_POWER_OFF, &val);
>> +	val &= RAA215300_MPIO2_POWER_OFF_DELAY;
>> +
>> +	return 32768 >> val;
>> +}
> Given the mask above val could be up to 127?  If nothing else it'd be
> good to have some validation.
Does it need validation if the mask is good?
>
>> +		/* register mpio2 32k clkout in common clk framework */
>> +		raa215300_register_clk(dev, regmap);
> You should check the return value here.
Ack.

Re: [PATCH RFC 2/2] regulator: raa215300: add support for configurable 32kHz clock output

[Josua Mayer]

Am 03.05.26 um 16:49 schrieb Josua Mayer:
> Am 03.05.26 um 02:57 schrieb Mark Brown:
>> On Sat, May 02, 2026 at 06:07:05PM +0200, Josua Mayer wrote:
>>> Renesas RA215300 PMIC can be configured to output a 32kHz clock on its
>>> multi-purpose MPIO2 pin.
>>> There are in total 6 configurable multi-purpose pins, however only one
>>> of them supports outputting a clock in one specific configuration.
>> So there should be some pinmux support here then?  This is starting to
>> sound like a MFD...
> If we want to treat it like an MFD, then the logical sub-devices would be:
>
> 1. pinmux/pinconf
> 2. clock
> 3. gpi, gpo

I forgot about two more functions:

4. reset: software trigger to reset system (reset-output), e.g. for reboot
5. poweroff: software trigger for power button, e.g. for shutdown

>
> Then there is the RTC, which is not a sub-device because it has its own i2c
> bus address, but its power controls inside the raa215300.
>
> And there are some more complex regulator status and configuration registers.
>
> Implemented is only the RTC ... and I would like to add the clock,
> as it is used for Bluetooth on a SolidRun board.
>
> My own particular use-case would also be satisfied by implementing
> pinmux instead, as I need the 32kHz rate which is default.
>
>>> +#define RAA215300_MPIO2_POWER_OFF_DELAY			GENMASK(6, 0)
>>> +#define RAA215300_REG_MPIO2_CONFIG			0x8c
>>> +static void raa215300_clk_unprepare(struct clk_hw *hw)
>>> +{
>>> +	struct raa215300_clk *clk = to_raa215300_clk(hw);
>>> +	const u8 dis_val = RAA215300_MPIO2_CONFIG_TYPE_HIGH_IMPEDANCE |
>>> +			   RAA215300_MPIO2_CONFIG_FUNCTION_NONE;
>>> +
>>> +	regmap_write(clk->regmap, RAA215300_REG_MPIO2_CONFIG, dis_val);
>>> +}
> Considering I use the pin configuration register to enable and disable the clock,
> one might argue that if a pinmux driver exists, then the clock is always on
> and does not support prepare/unprepare.
>
> This would allow me to skip implemeting a clock subdevice,
> and instead only implement a pinconf/mux driver.
>
> Any opinions?
>
>>> +static unsigned long raa215300_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
>>> +{
>>> +	struct raa215300_clk *clk = to_raa215300_clk(hw);
>>> +	unsigned int val;
>>> +
>>> +	regmap_read(clk->regmap, RAA215300_REG_MPIO2_POWER_OFF, &val);
>>> +	val &= RAA215300_MPIO2_POWER_OFF_DELAY;
>>> +
>>> +	return 32768 >> val;
>>> +}
>> Given the mask above val could be up to 127?  If nothing else it'd be
>> good to have some validation.
> Does it need validation if the mask is good?
>>> +		/* register mpio2 32k clkout in common clk framework */
>>> +		raa215300_register_clk(dev, regmap);
>> You should check the return value here.
> Ack.

RE: [PATCH RFC 0/2] regulator: raa215300: add support for configurable 32kHz clock output

[Biju Das]

Hi Josua Mayer,

> -----Original Message-----
> From: Josua Mayer <josua@solid-run.com>
> Sent: 02 May 2026 17:07
> Subject: [PATCH RFC 0/2] regulator: raa215300: add support for configurable 32kHz clock output
> 
> Add driver support and extend bindings for Renesas RAA215300 PMIC 32kHz clock output feature on pin
> MPIO2.


Snippet from hardware MANUAL [1]

Not sure, does it need to be part of a raa215300 pincontrol driver?

From [1] this clock generator depending up on the pinmux selection of
MPIO2?


[1] 

000: Disabled
001: 32K_CLK
010: External VR PGood input
011: Input to I2C register
100: PGood output
101: Reset output
110: External VR EN output
111: Output from I2C output

32kHz Clock (32K_CLK)

Only MPIO2 supports this function. The function provides a driven clock signal output for external devices. The
clock frequency is programmable with a maximum setting of 32.768kHz, which is the RTC crystal oscillator
frequency. The RTC needs to be enabled by the RTC_EN bit to output this clock signal. If the user does not have
an external pull-up voltage, the MPIO2 needs to be configured as a Full CMOS output.
When this function is selected, the MPIO2 Power-Off Delay register Bits [3:0] are used to select the clock
frequency. In this case, Bits [6:0] in this register are no longer used as a power-off delay.

Cheers,
Biju


> 
> Signed-off-by: Josua Mayer <josua@solid-run.com>
> ---
> Josua Mayer (2):
>       regulator: dt-bindings: raa215300: add clock output
>       regulator: raa215300: add support for configurable 32kHz clock output
> 
>  .../bindings/regulator/renesas,raa215300.yaml      |   6 +
>  drivers/regulator/raa215300.c                      | 132 +++++++++++++++++++++
>  2 files changed, 138 insertions(+)
> ---
> base-commit: 254f49634ee16a731174d2ae34bc50bd5f45e731
> change-id: 20260502-raa215300-clkout-c3ed84024888
> 
> Best regards,
> --
> Josua Mayer <josua@solid-run.com>