From: Bjorn Andersson <andersson@kernel.org>
To: Alexander Koskovich <akoskovich@pm.me>
Cc: Linus Walleij <linusw@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Abel Vesa <abel.vesa@oss.qualcomm.com>,
Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>,
linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3 4/4] pinctrl: qcom: eliza: Split QUP1_SE4 lanes
Date: Mon, 11 May 2026 13:04:31 -0500 [thread overview]
Message-ID: <agIZOAa6nYSb5PWX@baldur> (raw)
In-Reply-To: <20260423-fix-eliza-pinctrl-v3-4-68b24893ae63@pm.me>
On Thu, Apr 23, 2026 at 04:43:46AM +0000, Alexander Koskovich wrote:
> QUP1_SE4 shares GPIO_36 & GPIO_37 for both L0/L1 and L3/L2 so the
> function name cannot be the same or the alternate function cannot
> be selected.
>
> Split them up into individual lane functions so boards can specify.
>
This works, but it forces the DeviceTree source author to write a state
per pin even though these are typically configured in pairs.
What we did for hawi was to use the naming: qup1_se4_01 and qup1_se4_23
to express the two possible function pairs.
I don't have any strong opinions on how to proceed with this platform
(eliza), but I'm hoping we can follow the pair-wise scheme going
forward.
Regards,
Bjorn
> Signed-off-by: Alexander Koskovich <akoskovich@pm.me>
> ---
> drivers/pinctrl/qcom/pinctrl-eliza.c | 30 ++++++++++++++++++++++++------
> 1 file changed, 24 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/pinctrl/qcom/pinctrl-eliza.c b/drivers/pinctrl/qcom/pinctrl-eliza.c
> index 8f74756771b8..40e263e35b45 100644
> --- a/drivers/pinctrl/qcom/pinctrl-eliza.c
> +++ b/drivers/pinctrl/qcom/pinctrl-eliza.c
> @@ -568,7 +568,10 @@ enum eliza_functions {
> msm_mux_qup1_se2_l3_mira,
> msm_mux_qup1_se2_l3_mirb,
> msm_mux_qup1_se3,
> - msm_mux_qup1_se4,
> + msm_mux_qup1_se4_l0,
> + msm_mux_qup1_se4_l1,
> + msm_mux_qup1_se4_l2,
> + msm_mux_qup1_se4_l3,
> msm_mux_qup1_se5,
> msm_mux_qup1_se6,
> msm_mux_qup1_se6_l1_mira,
> @@ -1017,8 +1020,20 @@ static const char *const qup1_se3_groups[] = {
> "gpio44", "gpio45", "gpio46", "gpio47",
> };
>
> -static const char *const qup1_se4_groups[] = {
> - "gpio36", "gpio37", "gpio37", "gpio36",
> +static const char *const qup1_se4_l0_groups[] = {
> + "gpio36",
> +};
> +
> +static const char *const qup1_se4_l1_groups[] = {
> + "gpio37",
> +};
> +
> +static const char *const qup1_se4_l2_groups[] = {
> + "gpio37",
> +};
> +
> +static const char *const qup1_se4_l3_groups[] = {
> + "gpio36",
> };
>
> static const char *const qup1_se5_groups[] = {
> @@ -1321,7 +1336,10 @@ static const struct pinfunction eliza_functions[] = {
> MSM_PIN_FUNCTION(qup1_se2_l3_mira),
> MSM_PIN_FUNCTION(qup1_se2_l3_mirb),
> MSM_PIN_FUNCTION(qup1_se3),
> - MSM_PIN_FUNCTION(qup1_se4),
> + MSM_PIN_FUNCTION(qup1_se4_l0),
> + MSM_PIN_FUNCTION(qup1_se4_l1),
> + MSM_PIN_FUNCTION(qup1_se4_l2),
> + MSM_PIN_FUNCTION(qup1_se4_l3),
> MSM_PIN_FUNCTION(qup1_se5),
> MSM_PIN_FUNCTION(qup1_se6),
> MSM_PIN_FUNCTION(qup1_se6_l1_mira),
> @@ -1418,8 +1436,8 @@ static const struct msm_pingroup eliza_groups[] = {
> [33] = PINGROUP(33, qup1_se1, ibi_i3c, host2wlan_sol, gcc_gp3, _, _, _, _, _, _, _),
> [34] = PINGROUP(34, qup1_se1, qup1_se5, tb_trig_sdc1, ddr_bist_start, qdss_gpio_tracedata, _, _, _, _, _, _),
> [35] = PINGROUP(35, qup1_se1, qup1_se5, tb_trig_sdc2, gcc_gp2, qdss_gpio_tracedata, _, _, _, _, _, _),
> - [36] = PINGROUP(36, qup1_se4, qup1_se4, ibi_i3c, _, _, _, _, _, _, _, _),
> - [37] = PINGROUP(37, qup1_se4, qup1_se4, ibi_i3c, _, _, _, _, _, _, _, _),
> + [36] = PINGROUP(36, qup1_se4_l0, qup1_se4_l3, ibi_i3c, _, _, _, _, _, _, _, _),
> + [37] = PINGROUP(37, qup1_se4_l1, qup1_se4_l2, ibi_i3c, _, _, _, _, _, _, _, _),
> [38] = PINGROUP(38, _, _, _, _, _, _, _, _, _, _, _),
> [39] = PINGROUP(39, _, _, _, _, _, _, _, _, _, _, _),
> [40] = PINGROUP(40, qup1_se6, qup1_se2, qup1_se6_l3_mira, _, qdss_gpio_tracedata, gnss_adc1, ddr_pxi1, _, _, _, _),
>
> --
> 2.53.0
>
>
parent reply other threads:[~2026-05-11 18:04 UTC|newest]
Thread overview: expand[flat|nested] mbox.gz Atom feed
[parent not found: <20260423-fix-eliza-pinctrl-v3-4-68b24893ae63@pm.me>]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=agIZOAa6nYSb5PWX@baldur \
--to=andersson@kernel.org \
--cc=abel.vesa@oss.qualcomm.com \
--cc=akoskovich@pm.me \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=konrad.dybcio@oss.qualcomm.com \
--cc=krzk+dt@kernel.org \
--cc=linusw@kernel.org \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-gpio@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=robh@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox