Re: [PATCH v2 0/2] x86/tdx: Port I/O emulation fixes

Re: [PATCH v2 0/2] x86/tdx: Port I/O emulation fixes

[Kiryl Shutsemau]

On Tue, Apr 28, 2026 at 01:56:30PM +0100, Kiryl Shutsemau (Meta) wrote:
> Kiryl Shutsemau (Meta) (2):
>   x86/tdx: Fix off-by-one in port I/O handling
>   x86/tdx: Fix zero-extension for 32-bit port I/O

Dave, could get them applied?

-- 
  Kiryl Shutsemau / Kirill A. Shutemov

Re: [PATCH v2 0/2] x86/tdx: Port I/O emulation fixes

[Dave Hansen]

On 5/8/26 15:52, Kiryl Shutsemau wrote:
> On Tue, Apr 28, 2026 at 01:56:30PM +0100, Kiryl Shutsemau (Meta) wrote:
>> Kiryl Shutsemau (Meta) (2):
>>   x86/tdx: Fix off-by-one in port I/O handling
>>   x86/tdx: Fix zero-extension for 32-bit port I/O
> Dave, could get them applied?

I'll look on Monday. Thanks for the reminder.

Re: [PATCH v2 2/2] x86/tdx: Fix zero-extension for 32-bit port I/O

[Dave Hansen]

On 4/28/26 05:56, Kiryl Shutsemau (Meta) wrote:
> +	if (size == 4)
> +		regs->ax = 0;
> +	else
> +		regs->ax &= ~mask;

I haven't thought about this _that_ much, but this feels wrong. Why is
is 4 so special cased?

Also, what _are_ the limits on the registers that 'in' can be used on?

RAX - n/a, no 64-bit I/O
EAX - size=4
AX  - size=2
AH  - n/a no encoding for inb
AL  - size=1

I'd find this much easier to grasp if there was a nice table of what the
registers, sizes, and masks ended up being usable. As usual, x86 is
"fun" here.

Re: [PATCH v2 2/2] x86/tdx: Fix zero-extension for 32-bit port I/O

[H. Peter Anvin]

On May 12, 2026 6:14:13 PM PDT, Dave Hansen <dave.hansen@intel.com> wrote:
>On 4/28/26 05:56, Kiryl Shutsemau (Meta) wrote:
>> +	if (size == 4)
>> +		regs->ax = 0;
>> +	else
>> +		regs->ax &= ~mask;
>
>I haven't thought about this _that_ much, but this feels wrong. Why is
>is 4 so special cased?
>
>Also, what _are_ the limits on the registers that 'in' can be used on?
>
>RAX - n/a, no 64-bit I/O
>EAX - size=4
>AX  - size=2
>AH  - n/a no encoding for inb
>AL  - size=1
>
>I'd find this much easier to grasp if there was a nice table of what the
>registers, sizes, and masks ended up being usable. As usual, x86 is
>"fun" here.

Because zero extension only applies to dwords.

x86-64 has three subregisters per GPR:

Bits 7-0
Bits 15-8
Bits 63-16

Re: [PATCH v2 2/2] x86/tdx: Fix zero-extension for 32-bit port I/O

[Sean Christopherson]

On Tue, May 12, 2026, H. Peter Anvin wrote:
> On May 12, 2026 6:14:13 PM PDT, Dave Hansen <dave.hansen@intel.com> wrote:
> >On 4/28/26 05:56, Kiryl Shutsemau (Meta) wrote:
> >> +	if (size == 4)
> >> +		regs->ax = 0;
> >> +	else
> >> +		regs->ax &= ~mask;
> >
> >I haven't thought about this _that_ much, but this feels wrong. Why is
> >is 4 so special cased?
> >
> >Also, what _are_ the limits on the registers that 'in' can be used on?
> >
> >RAX - n/a, no 64-bit I/O
> >EAX - size=4
> >AX  - size=2
> >AH  - n/a no encoding for inb
> >AL  - size=1
> >
> >I'd find this much easier to grasp if there was a nice table of what the
> >registers, sizes, and masks ended up being usable. As usual, x86 is
> >"fun" here.
> 
> Because zero extension only applies to dwords.
> 
> x86-64 has three subregisters per GPR:

Aren't there four?  The fourth being 31:0, which is the one that is zero-extended
and so "clobbers" 63:32.

> Bits 7-0
> Bits 15-8
> Bits 63-16

I assume you mean 15:0?  63:16 isn't addressable.  And these are the ones that
aren't zero-extended, i.e. don't "clobber" other bits.