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From: Brian Masney <bmasney@redhat.com>
To: Christian Marangi <ansuelsmth@gmail.com>
Cc: Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>,
	linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] clk: en7523: reset PCIE HB on init for AN7581
Date: Thu, 9 Jul 2026 10:24:02 -0400	[thread overview]
Message-ID: <ak-vAqKlJ0pFx9J6@redhat.com> (raw)
In-Reply-To: <6a4fa6ab.b2781ae3.385c0f.d696@mx.google.com>

On Thu, Jul 09, 2026 at 03:48:26PM +0200, Christian Marangi wrote:
> On Wed, Jul 08, 2026 at 12:52:49PM -0400, Brian Masney wrote:
> > Hi Christian,
> > 
> > Thanks for the patch.
> > 
> > On Wed, Jul 08, 2026 at 10:40:44AM +0200, Christian Marangi wrote:
> > > It was reported that PCIE HB should be reset for AN7581 or some instability
> > > or link training issue will be present on warm boot scenario.
> > > 
> > > Reset PCIE HB on clk HW init to handle warm boot problem with PCIe.
> > > 
> > > Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
> > > ---
> > >  drivers/clk/clk-en7523.c | 7 +++++++
> > >  1 file changed, 7 insertions(+)
> > > 
> > > diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c
> > > index 1ab0e2eca5d3..c450d89bfa96 100644
> > > --- a/drivers/clk/clk-en7523.c
> > > +++ b/drivers/clk/clk-en7523.c
> > > @@ -57,6 +57,7 @@
> > >  
> > >  #define REG_RST_CTRL2			0x830
> > >  #define REG_RST_CTRL1			0x834
> > > +#define   REG_PCIE_HB_RST		BIT(29)
> > >  #define EN751221_REG_RST_DMT		0x84
> > >  #define EN751221_REG_RST_USB		0xec
> > >  
> > > @@ -853,6 +854,12 @@ static int en7581_clk_hw_init(struct platform_device *pdev,
> > >  	val = readl(base + REG_NP_SCU_PCIC);
> > >  	writel(val | 3, base + REG_NP_SCU_PCIC);
> > >  
> > > +	val = readl(base + REG_RST_CTRL1);
> > > +	val |= REG_PCIE_HB_RST;
> > > +	writel(val, base + REG_RST_CTRL1);
> > > +	val &= ~REG_PCIE_HB_RST;
> > > +	writel(val, base + REG_RST_CTRL1);
> > > +
> > 
> > Sashiko has a question about whether or not a delay or a flush is needed
> > between the writel() calls?
> > 
> > https://sashiko.dev/#/patchset/20260708084045.8380-1-ansuelsmth%40gmail.com
> >
> 
> Hi Brian, from the test done by me and Airoha with their CI on 10000 test,
> no delay is needed. If we want to be on the save side I can add it anyway
> for consistency with the other code. What do you think?

10,000 test is probably good enough then.

Reviewed-by: Brian Masney <bmasney@redhat.com>


      reply	other threads:[~2026-07-09 14:24 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-08  8:40 [PATCH] clk: en7523: reset PCIE HB on init for AN7581 Christian Marangi
2026-07-08 16:52 ` Brian Masney
2026-07-09 13:48   ` Christian Marangi
2026-07-09 14:24     ` Brian Masney [this message]

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