* [PATCH] drm/xe/nvm: fix writable override for CRI
@ 2026-07-08 15:00 Alexander Usyskin
2026-07-08 19:53 ` Rodrigo Vivi
0 siblings, 1 reply; 2+ messages in thread
From: Alexander Usyskin @ 2026-07-08 15:00 UTC (permalink / raw)
To: Matthew Brost, Thomas Hellström, Rodrigo Vivi, David Airlie,
Simona Vetter
Cc: intel-xe, dri-devel, linux-kernel, stable, Alexander Usyskin
The witable override should be set when FDO_MODE bit is enabled.
Fix the comparison to distingush this case from legacy systems
where bit should be disabled to have override.
Cc: stable@vger.kernel.org
Fixes: 9dde74fd9e65 ("drm/xe/nvm: enable cri platform")
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
---
drivers/gpu/drm/xe/xe_nvm.c | 10 +++++++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_nvm.c b/drivers/gpu/drm/xe/xe_nvm.c
index 33487e91f366..d50ee414e83e 100644
--- a/drivers/gpu/drm/xe/xe_nvm.c
+++ b/drivers/gpu/drm/xe/xe_nvm.c
@@ -60,35 +60,39 @@ static bool xe_nvm_writable_override(struct xe_device *xe)
struct xe_mmio *mmio = xe_root_tile_mmio(xe);
bool writable_override;
struct xe_reg reg;
- u32 test_bit;
+ u32 test_bit, test_val;
switch (xe->info.platform) {
case XE_CRESCENTISLAND:
reg = PCODE_SCRATCH(0);
- test_bit = FDO_MODE;
+ test_val = test_bit = FDO_MODE;
break;
case XE_BATTLEMAGE:
reg = HECI_FWSTS2(DG2_GSC_HECI2_BASE);
test_bit = HECI_FW_STATUS_2_NVM_ACCESS_MODE;
+ test_val = 0;
break;
case XE_PVC:
reg = HECI_FWSTS2(PVC_GSC_HECI2_BASE);
test_bit = HECI_FW_STATUS_2_NVM_ACCESS_MODE;
+ test_val = 0;
break;
case XE_DG2:
reg = HECI_FWSTS2(DG2_GSC_HECI2_BASE);
test_bit = HECI_FW_STATUS_2_NVM_ACCESS_MODE;
+ test_val = 0;
break;
case XE_DG1:
reg = HECI_FWSTS2(DG1_GSC_HECI2_BASE);
test_bit = HECI_FW_STATUS_2_NVM_ACCESS_MODE;
+ test_val = 0;
break;
default:
drm_err(&xe->drm, "Unknown platform\n");
return true;
}
- writable_override = !(xe_mmio_read32(mmio, reg) & test_bit);
+ writable_override = (xe_mmio_read32(mmio, reg) & test_bit) == test_val;
if (writable_override)
drm_info(&xe->drm, "NVM access overridden by jumper\n");
return writable_override;
---
base-commit: 8cdeaa50eae8dad34885515f62559ee83e7e8dda
change-id: 20260708-cri_nvm_fdo_flip-333b545e1dd8
Best regards,
--
Alexander Usyskin <alexander.usyskin@intel.com>
^ permalink raw reply related [flat|nested] 2+ messages in thread* Re: [PATCH] drm/xe/nvm: fix writable override for CRI
2026-07-08 15:00 [PATCH] drm/xe/nvm: fix writable override for CRI Alexander Usyskin
@ 2026-07-08 19:53 ` Rodrigo Vivi
0 siblings, 0 replies; 2+ messages in thread
From: Rodrigo Vivi @ 2026-07-08 19:53 UTC (permalink / raw)
To: Alexander Usyskin
Cc: Matthew Brost, Thomas Hellström, David Airlie, Simona Vetter,
intel-xe, dri-devel, linux-kernel, stable
On Wed, Jul 08, 2026 at 06:00:17PM +0300, Alexander Usyskin wrote:
> The witable override should be set when FDO_MODE bit is enabled.
> Fix the comparison to distingush this case from legacy systems
> where bit should be disabled to have override.
>
> Cc: stable@vger.kernel.org
> Fixes: 9dde74fd9e65 ("drm/xe/nvm: enable cri platform")
> Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
> ---
> drivers/gpu/drm/xe/xe_nvm.c | 10 +++++++---
> 1 file changed, 7 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_nvm.c b/drivers/gpu/drm/xe/xe_nvm.c
> index 33487e91f366..d50ee414e83e 100644
> --- a/drivers/gpu/drm/xe/xe_nvm.c
> +++ b/drivers/gpu/drm/xe/xe_nvm.c
> @@ -60,35 +60,39 @@ static bool xe_nvm_writable_override(struct xe_device *xe)
> struct xe_mmio *mmio = xe_root_tile_mmio(xe);
> bool writable_override;
> struct xe_reg reg;
> - u32 test_bit;
> + u32 test_bit, test_val;
>
> switch (xe->info.platform) {
> case XE_CRESCENTISLAND:
> reg = PCODE_SCRATCH(0);
> - test_bit = FDO_MODE;
> + test_val = test_bit = FDO_MODE;
-:31: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#31: FILE: drivers/gpu/drm/xe/xe_nvm.c:68:
+ test_val = test_bit = FDO_MODE;
total: 0 errors, 0 warnings, 1 checks, 42 lines checked
> break;
> case XE_BATTLEMAGE:
> reg = HECI_FWSTS2(DG2_GSC_HECI2_BASE);
> test_bit = HECI_FW_STATUS_2_NVM_ACCESS_MODE;
> + test_val = 0;
> break;
> case XE_PVC:
> reg = HECI_FWSTS2(PVC_GSC_HECI2_BASE);
> test_bit = HECI_FW_STATUS_2_NVM_ACCESS_MODE;
> + test_val = 0;
> break;
> case XE_DG2:
> reg = HECI_FWSTS2(DG2_GSC_HECI2_BASE);
> test_bit = HECI_FW_STATUS_2_NVM_ACCESS_MODE;
> + test_val = 0;
> break;
> case XE_DG1:
> reg = HECI_FWSTS2(DG1_GSC_HECI2_BASE);
> test_bit = HECI_FW_STATUS_2_NVM_ACCESS_MODE;
> + test_val = 0;
> break;
> default:
> drm_err(&xe->drm, "Unknown platform\n");
> return true;
> }
>
> - writable_override = !(xe_mmio_read32(mmio, reg) & test_bit);
> + writable_override = (xe_mmio_read32(mmio, reg) & test_bit) == test_val;
> if (writable_override)
> drm_info(&xe->drm, "NVM access overridden by jumper\n");
> return writable_override;
>
> ---
> base-commit: 8cdeaa50eae8dad34885515f62559ee83e7e8dda
> change-id: 20260708-cri_nvm_fdo_flip-333b545e1dd8
>
> Best regards,
> --
> Alexander Usyskin <alexander.usyskin@intel.com>
>
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