TSC as clocksource

TSC as clocksource

[Rob]

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Want to use TSC as clocksource
have a Intel Core2 Duo with constant_tsc flag
TSC should be stable at C1 + C2, it is debatable whether C3 is stable

Using processor.max_cstate=2 to use only C1 + C2 changes nothing, still get
Monitor-Mwait will be used to enter C-3 state
there should be checks before this is forced

Please CC answers, comments to my email.

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Want to use TSC as clocksource
have a Intel Core2 Duo with constant_tsc flag
TSC should be stable at C1 + C2, it is debatable whether C3 is stable

Using processor.max_cstate=2 to use only C1 + C2 changes nothing, still get
Monitor-Mwait will be used to enter C-3 state
there should be checks before this is forced

Please CC answers, comments to my email.


[    0.000000] hpet clockevent registered
[    0.000000] Fast TSC calibration using PIT
...
...
[    0.012931] CPU0: Thermal monitoring enabled (TM2)
[    0.012980] using mwait in idle threads.
...
...
[    0.461731] HPET: 4 timers in total, 0 timers will be used for per-cpu timer
[    0.461786] hpet0: at MMIO 0xfed00000, IRQs 2, 8, 0, 0
[    0.461990] hpet0: 4 comparators, 64-bit 14.318180 MHz counter
[    0.470034] Switching to clocksource tsc
...
...
[    0.575163] ACPI: acpi_idle registered with cpuidle
[    0.577772] Monitor-Mwait will be used to enter C-1 state
[    0.589800] Monitor-Mwait will be used to enter C-2 state
[    0.589843] Monitor-Mwait will be used to enter C-3 state
[    0.589876] Marking TSC unstable due to TSC halts in idle
[    0.591120] Switching to clocksource hpet


processor	: 0
vendor_id	: GenuineIntel
cpu family	: 6
model		: 23
model name	: Intel(R) Core(TM)2 Duo CPU     P8600  @ 2.40GHz
stepping	: 6
cpu MHz		: 800.000
cache size	: 3072 KB
physical id	: 0
siblings	: 2
core id		: 0
cpu cores	: 2
apicid		: 0
initial apicid	: 0
fpu		: yes
fpu_exception	: yes
cpuid level	: 10
wp		: yes
flags		: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr
   sse sse2 ss ht tm pbe syscall nx lm constant_tsc arch_perfmon pebs bts rep_good aperfmperf pni dtes64 monitor
   ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm sse4_1 lahf_lm dts tpr_shadow vnmi flexpriority
bogomips	: 4787.86
clflush size	: 64
cache_alignment	: 64
address sizes	: 36 bits physical, 48 bits virtual
power management:

Re: TSC as clocksource

[Peter Zijlstra]

On Mon, 2011-01-10 at 09:54 +1100, Rob wrote:
> Want to use TSC as clocksource
> have a Intel Core2 Duo with constant_tsc flag
> TSC should be stable at C1 + C2, it is debatable whether C3 is stable
> 
> Using processor.max_cstate=2 to use only C1 + C2 changes nothing, still get
> Monitor-Mwait will be used to enter C-3 state
> there should be checks before this is forced
> 
> Please CC answers, comments to my email.

Len, Thomas?

Re: TSC as clocksource

[Thomas Gleixner]

On Mon, 10 Jan 2011, Peter Zijlstra wrote:

> On Mon, 2011-01-10 at 09:54 +1100, Rob wrote:
> > Want to use TSC as clocksource
> > have a Intel Core2 Duo with constant_tsc flag
> > TSC should be stable at C1 + C2, it is debatable whether C3 is stable
> > 
> > Using processor.max_cstate=2 to use only C1 + C2 changes nothing, still get
> > Monitor-Mwait will be used to enter C-3 state
> > there should be checks before this is forced

We unconditinally set TSC unstable for anything > C1. The reason is
that we had a lot of troubles with BIOSes which advertise C2, but in
fact implement C3. Unfortunately we can't verify that.

Thanks,

	tglx

Re: TSC as clocksource

[Len Brown]

> > On Mon, 2011-01-10 at 09:54 +1100, Rob wrote:
> > > Want to use TSC as clocksource
> > > have a Intel Core2 Duo with constant_tsc flag
> > > TSC should be stable at C1 + C2, it is debatable whether C3 is stable

no debate, TSC on Core2 stops in C3.

> > > Using processor.max_cstate=2 to use only C1 + C2 changes nothing, still get
> > > Monitor-Mwait will be used to enter C-3 state
> > > there should be checks before this is forced
> 
> We unconditinally set TSC unstable for anything > C1. The reason is
> that we had a lot of troubles with BIOSes which advertise C2, but in
> fact implement C3. Unfortunately we can't verify that.

Right.
There are some Core2 where what ACPI advertises as C2 the TSC works,
and some where it does something other than "hardware C2",
such as "hardware C3" and the TSC stops, so Linux is conservative here.

If you want a stable TSC on Core2 (and before)
then you need to use either idle=poll or processor.max_cstate=1.

Nehalem and newer (Core i7 etc) have an invarient TSC that works no matter
what C-states are present.

cheers,
Len Brown, Intel Open Source Technology Center