Re: [PATCH] x86/split_lock: Enable the split lock detect feature on Raptor Lake P and Alder Lake N CPUs

[Dave Hansen <dave.hansen@intel.com>]

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I have an alternative patch.

Let's just consider the MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT bit to be
architectural.  Are there *ACTUAL* implementations where this is wrong?
 If not, let's just make it part of the architecture.  Intel can then
keep it true forever.

Some documentation which says:

	All processors that enumerate support for MSR_IA32_CORE_CAPS and
	set MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT support split lock 	
	detection.

would suffice, I think.  Just look at the diffstat.  What's not to love?

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---

 b/arch/x86/kernel/cpu/intel.c |   55 +++++++++++++-----------------------------
 1 file changed, 18 insertions(+), 37 deletions(-)

diff -puN arch/x86/kernel/cpu/intel.c~split-lock-arch arch/x86/kernel/cpu/intel.c
--- a/arch/x86/kernel/cpu/intel.c~split-lock-arch	2022-07-05 12:37:21.294034182 -0700
+++ b/arch/x86/kernel/cpu/intel.c	2022-07-05 12:43:40.483842478 -0700
@@ -1265,31 +1265,14 @@ void handle_bus_lock(struct pt_regs *reg
 }
 
 /*
- * Bits in the IA32_CORE_CAPABILITIES are not architectural, so they should
- * only be trusted if it is confirmed that a CPU model implements a
- * specific feature at a particular bit position.
- *
- * The possible driver data field values:
- *
- * - 0: CPU models that are known to have the per-core split-lock detection
- *	feature even though they do not enumerate IA32_CORE_CAPABILITIES.
- *
- * - 1: CPU models which may enumerate IA32_CORE_CAPABILITIES and if so use
- *      bit 5 to enumerate the per-core split-lock detection feature.
+ * Not all bits in MSR_IA32_CORE_CAPS are architectural, but
+ * MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT is.  All CPUs that set
+ * it have split lock detection.
  */
 static const struct x86_cpu_id split_lock_cpu_ids[] __initconst = {
-	X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X,		0),
-	X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_L,		0),
-	X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D,		0),
-	X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT,	1),
-	X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_D,	1),
-	X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_L,	1),
-	X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE_L,		1),
-	X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE,		1),
-	X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X,	1),
-	X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE,		1),
-	X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L,		1),
-	X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE,		1),
+	X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X,	1),
+	X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_L,	1),
+	X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D,	1),
 	{}
 };
 
@@ -1301,24 +1284,22 @@ static void __init split_lock_setup(stru
 	if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
 		return;
 
+	/* Check for CPUs that have support but do not enumerate it: */
 	m = x86_match_cpu(split_lock_cpu_ids);
-	if (!m)
-		return;
+	if (m)
+		goto supported;
 
-	switch (m->driver_data) {
-	case 0:
-		break;
-	case 1:
-		if (!cpu_has(c, X86_FEATURE_CORE_CAPABILITIES))
-			return;
-		rdmsrl(MSR_IA32_CORE_CAPS, ia32_core_caps);
-		if (!(ia32_core_caps & MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT))
-			return;
-		break;
-	default:
+	if (!cpu_has(c, X86_FEATURE_CORE_CAPABILITIES))
 		return;
-	}
 
+	rdmsrl(MSR_IA32_CORE_CAPS, ia32_core_caps);
+	if (ia32_core_caps & MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT)
+		goto supported;
+
+	/* CPU is not in the model list and does not have the MSR bit: */
+	return;
+
+supported:
 	cpu_model_supports_sld = true;
 	__split_lock_setup();
 }
_