From: Kartik Rajput <kkartik@nvidia.com>
To: Jon Hunter <jonathanh@nvidia.com>,
akhilrajeev@nvidia.com, andi.shyti@kernel.org, robh@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org,
thierry.reding@gmail.com, ldewangan@nvidia.com, digetx@gmail.com,
smangipudi@nvidia.com, linux-i2c@vger.kernel.org,
devicetree@vger.kernel.org, linux-tegra@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH 1/2] i2c: tegra: Add logic to support different register offsets
Date: Tue, 28 Oct 2025 11:17:09 +0530 [thread overview]
Message-ID: <b1ad93cb-fee0-4b29-af10-a6668624dfbe@nvidia.com> (raw)
In-Reply-To: <ab204023-1c45-4c67-9a90-d854da937ee8@nvidia.com>
On 24/10/25 20:43, Jon Hunter wrote:
>
> On 01/10/2025 16:36, Kartik Rajput wrote:
>> Tegra410 use different offsets for existing I2C registers, update
>> the logic to use appropriate offsets per SoC.
>>
>> Signed-off-by: Kartik Rajput <kkartik@nvidia.com>
>> ---
>> drivers/i2c/busses/i2c-tegra.c | 499 ++++++++++++++++++++++-----------
>> 1 file changed, 334 insertions(+), 165 deletions(-)
>>
>> diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c
>> index 038809264526..1e26d67cbd30 100644
>> --- a/drivers/i2c/busses/i2c-tegra.c
>> +++ b/drivers/i2c/busses/i2c-tegra.c
>
> ...
>
>> +static const struct tegra_i2c_regs tegra20_i2c_regs_vi = {
>> + .cnfg = 0x0c00 + (0x000 << 2),
>> + .status = 0x0c00 + (0x01c << 2),
>> + .sl_cnfg = 0x0c00 + (0x020 << 2),
>> + .sl_addr1 = 0x0c00 + (0x02c << 2),
>> + .sl_addr2 = 0x0c00 + (0x030 << 2),
>> + .tlow_sext = 0x0c00 + (0x034 << 2),
>> + .tx_fifo = 0x0c00 + (0x050 << 2),
>> + .rx_fifo = 0x0c00 + (0x054 << 2),
>> + .packet_transfer_status = 0x0c00 + (0x058 << 2),
>> + .fifo_control = 0x0c00 + (0x05c << 2),
>> + .fifo_status = 0x0c00 + (0x060 << 2),
>> + .int_mask = 0x0c00 + (0x064 << 2),
>> + .int_status = 0x0c00 + (0x068 << 2),
>> + .clk_divisor = 0x0c00 + (0x06c << 2),
>> + .bus_clear_cnfg = 0x0c00 + (0x084 << 2),
>> + .bus_clear_status = 0x0c00 + (0x088 << 2),
>> + .config_load = 0x0c00 + (0x08c << 2),
>> + .clken_override = 0x0c00 + (0x090 << 2),
>> + .interface_timing_0 = 0x0c00 + (0x094 << 2),
>> + .interface_timing_1 = 0x0c00 + (0x098 << 2),
>> + .hs_interface_timing_0 = 0x0c00 + (0x09c << 2),
>> + .hs_interface_timing_1 = 0x0c00 + (0x0a0 << 2),
>> + .master_reset_cntrl = 0x0c00 + (0x0a8 << 2),
>> + .mst_fifo_control = 0x0c00 + (0x0b4 << 2),
>> + .mst_fifo_status = 0x0c00 + (0x0b8 << 2),
>> + .sw_mutex = 0x0c00 + (0x0ec << 2),
>
> Why do we define all the above with '<< 2'? Seems odd.
>
> Jon
>
Ack. I will update this with the calculated values.
Thanks,
Kartik
next prev parent reply other threads:[~2025-10-28 5:47 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-01 15:36 [PATCH 0/2] Add I2C support for Tegra410 Kartik Rajput
2025-10-01 15:36 ` [PATCH 1/2] i2c: tegra: Add logic to support different register offsets Kartik Rajput
2025-10-24 15:11 ` Jon Hunter
2025-10-24 15:13 ` Jon Hunter
2025-10-28 5:47 ` Kartik Rajput [this message]
2025-10-24 15:33 ` Jon Hunter
2025-10-28 5:42 ` Kartik Rajput
2025-11-06 7:59 ` Jon Hunter
2025-11-06 8:06 ` Kartik Rajput
2025-10-01 15:36 ` [PATCH 2/2] i2c: tegra: Add support for Tegra410 Kartik Rajput
2025-10-24 15:17 ` Jon Hunter
2025-10-28 5:44 ` Kartik Rajput
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