* [PATCH 0/2] phy: qcom: qmp-pcie: Update PCIe PHY settings for SM8550
@ 2023-12-28 5:42 Qiang Yu
2023-12-28 5:42 ` [PATCH 1/2] phy: qcom: qmp-pcie: Update PCIe1 " Qiang Yu
` (3 more replies)
0 siblings, 4 replies; 9+ messages in thread
From: Qiang Yu @ 2023-12-28 5:42 UTC (permalink / raw)
To: agross, andersson, konrad.dybcio, vkoul, kishon
Cc: linux-arm-msm, linux-phy, linux-kernel, quic_cang, quic_mrana,
quic_qianyu
Align PCIe0/PCIe1 PHY settings with SM8550 latest PCIe PHY Hardware
Programming Guide.
Can Guo (1):
phy: qcom: qmp-pcie: Update PCIe1 PHY settings for SM8550
Qiang Yu (1):
phy: qcom: qmp-pcie: Update PCIe0 PHY settings for SM8550
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 20 ++++++++++++++------
drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6.h | 2 ++
drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_20.h | 2 ++
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_20.h | 1 +
.../phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_20.h | 2 ++
5 files changed, 21 insertions(+), 6 deletions(-)
--
2.7.4
^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH 1/2] phy: qcom: qmp-pcie: Update PCIe1 PHY settings for SM8550 2023-12-28 5:42 [PATCH 0/2] phy: qcom: qmp-pcie: Update PCIe PHY settings for SM8550 Qiang Yu @ 2023-12-28 5:42 ` Qiang Yu 2023-12-28 5:42 ` [PATCH 2/2] phy: qcom: qmp-pcie: Update PCIe0 " Qiang Yu ` (2 subsequent siblings) 3 siblings, 0 replies; 9+ messages in thread From: Qiang Yu @ 2023-12-28 5:42 UTC (permalink / raw) To: agross, andersson, konrad.dybcio, vkoul, kishon Cc: linux-arm-msm, linux-phy, linux-kernel, quic_cang, quic_mrana, quic_qianyu From: Can Guo <quic_cang@quicinc.com> Align PCIe1 PHY settings with SM8550 latest PCIe PHY Hardware Programming Guide. Signed-off-by: Can Guo <quic_cang@quicinc.com> Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com> --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 16 +++++++++++----- drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_20.h | 2 ++ drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_20.h | 1 + drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_20.h | 2 ++ 4 files changed, 16 insertions(+), 5 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index 2af7115..5f87ebc 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -1823,10 +1823,9 @@ static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_serdes_tbl[] = { static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_ln_shrd_tbl[] = { QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RXCLK_DIV2_CTRL, 0x01), - QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_Q_EN_RATES, 0xe), QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_DFE_DAC_ENABLE1, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH1, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH2, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH1, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH2, 0x0d), QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B0, 0x12), QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B1, 0x12), QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B2, 0xdb), @@ -1843,6 +1842,7 @@ static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_ln_shrd_tbl[] = { QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH4_RATE3, 0x1f), QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH5_RATE3, 0x1f), QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH6_RATE3, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_SUMMER_CAL_SPD_MODE, 0x5b), }; static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_tx_tbl[] = { @@ -1855,13 +1855,15 @@ static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_tx_tbl[] = { }; static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_rx_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2, 0x0c), QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_GAIN_RATE_2, 0x04), QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_PI_CONTROLS, 0x16), QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3, 0x00), QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_CAL_CTRL2, 0x80), QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_POSTCAL_OFFSET, 0x7c), QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_3, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_TX_ADPT_CTRL, 0x10), QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_VGA_CAL_MAN_VAL, 0x0a), QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_GM_CAL, 0x0d), QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_EQU_ADAPTOR_CNTRL4, 0x0b), @@ -1883,11 +1885,13 @@ static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_rx_tbl[] = { QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B4, 0x78), QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B5, 0x76), QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B6, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V6_20_VGA_CAL_CNTRL1, 0x00), }; static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_pcs_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_G12S1_TXDEEMPH_M6DB, 0x17), QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_G3S2_PRE_GAIN, 0x2e), - QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_COM_ELECIDLE_DLY_SEL, 0x25), + QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_RX_SIGDET_LVL, 0xcc), QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_EQ_CONFIG4, 0x00), QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_EQ_CONFIG5, 0x22), QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_TX_RX_CONFIG1, 0x04), @@ -1898,6 +1902,8 @@ static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_pcs_misc_tbl[] = { QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_ENDPOINT_REFCLK_DRIVE, 0xc1), QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_OSC_DTCT_ATCIONS, 0x00), QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_EQ_CONFIG1, 0x16), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G3_RXEQEVAL_TIME, 0x27), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_RXEQEVAL_TIME, 0x27), QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_EQ_CONFIG5, 0x02), QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_PRE_GAIN, 0x2e), QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG1, 0x03), diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_20.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_20.h index e3eb087..dfcecf3 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_20.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_20.h @@ -12,6 +12,8 @@ #define QPHY_PCIE_V6_20_PCS_ENDPOINT_REFCLK_DRIVE 0x01c #define QPHY_PCIE_V6_20_PCS_OSC_DTCT_ATCIONS 0x090 #define QPHY_PCIE_V6_20_PCS_EQ_CONFIG1 0x0a0 +#define QPHY_PCIE_V6_20_PCS_G3_RXEQEVAL_TIME 0x0f0 +#define QPHY_PCIE_V6_20_PCS_G4_RXEQEVAL_TIME 0x0f4 #define QPHY_PCIE_V6_20_PCS_EQ_CONFIG5 0x108 #define QPHY_PCIE_V6_20_PCS_G4_PRE_GAIN 0x15c #define QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG1 0x17c diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_20.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_20.h index 9c3f1e4..4d9615c 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_20.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_20.h @@ -7,6 +7,7 @@ #define QCOM_PHY_QMP_PCS_V6_20_H_ /* Only for QMP V6_20 PHY - USB/PCIe PCS registers */ +#define QPHY_V6_20_PCS_G12S1_TXDEEMPH_M6DB 0x170 #define QPHY_V6_20_PCS_G3S2_PRE_GAIN 0x178 #define QPHY_V6_20_PCS_RX_SIGDET_LVL 0x190 #define QPHY_V6_20_PCS_COM_ELECIDLE_DLY_SEL 0x1b8 diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_20.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_20.h index 6ed5339..7bac5d5 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_20.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_20.h @@ -23,6 +23,8 @@ #define QSERDES_V6_20_RX_DFE_1 0xac #define QSERDES_V6_20_RX_DFE_2 0xb0 #define QSERDES_V6_20_RX_DFE_3 0xb4 +#define QSERDES_V6_20_RX_TX_ADPT_CTRL 0xd4 +#define QSERDES_V6_20_VGA_CAL_CNTRL1 0xe0 #define QSERDES_V6_20_RX_VGA_CAL_MAN_VAL 0xe8 #define QSERDES_V6_20_RX_GM_CAL 0x10c #define QSERDES_V6_20_RX_EQU_ADAPTOR_CNTRL4 0x120 -- 2.7.4 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 2/2] phy: qcom: qmp-pcie: Update PCIe0 PHY settings for SM8550 2023-12-28 5:42 [PATCH 0/2] phy: qcom: qmp-pcie: Update PCIe PHY settings for SM8550 Qiang Yu 2023-12-28 5:42 ` [PATCH 1/2] phy: qcom: qmp-pcie: Update PCIe1 " Qiang Yu @ 2023-12-28 5:42 ` Qiang Yu 2024-01-24 8:58 ` [PATCH 0/2] phy: qcom: qmp-pcie: Update PCIe " neil.armstrong 2024-01-30 17:39 ` Vinod Koul 3 siblings, 0 replies; 9+ messages in thread From: Qiang Yu @ 2023-12-28 5:42 UTC (permalink / raw) To: agross, andersson, konrad.dybcio, vkoul, kishon Cc: linux-arm-msm, linux-phy, linux-kernel, quic_cang, quic_mrana, quic_qianyu Align PCIe0 PHY settings with SM8550 latest PCIe PHY Hardware Programming Guide. Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com> --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 4 +++- drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6.h | 2 ++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index 5f87ebc..857581d 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -1747,7 +1747,7 @@ static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_rx_tbl[] = { QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH2, 0x5b), QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH3, 0x1a), QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH4, 0x89), - QMP_PHY_INIT_CFG(QSERDES_V6_RX_TX_ADAPT_POST_THRESH, 0xf0), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_TX_ADAPT_POST_THRESH, 0x00), QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FO_GAIN, 0x09), QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_GAIN, 0x05), QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH1, 0x08), @@ -1767,6 +1767,8 @@ static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_pcs_tbl[] = { }; static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_pcs_misc_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_EQ_CONFIG1, 0x1e), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_RXEQEVAL_TIME, 0x27), QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG2, 0x1d), QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6.h index 91e7000..0ca7933 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6.h @@ -7,6 +7,8 @@ #define QCOM_PHY_QMP_PCS_PCIE_V6_H_ /* Only for QMP V6 PHY - PCIE have different offsets than V5 */ +#define QPHY_PCIE_V6_PCS_PCIE_EQ_CONFIG1 0xa4 +#define QPHY_PCIE_V6_PCS_PCIE_RXEQEVAL_TIME 0xf4 #define QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG2 0x0c #define QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG4 0x14 #define QPHY_PCIE_V6_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x20 -- 2.7.4 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 0/2] phy: qcom: qmp-pcie: Update PCIe PHY settings for SM8550 2023-12-28 5:42 [PATCH 0/2] phy: qcom: qmp-pcie: Update PCIe PHY settings for SM8550 Qiang Yu 2023-12-28 5:42 ` [PATCH 1/2] phy: qcom: qmp-pcie: Update PCIe1 " Qiang Yu 2023-12-28 5:42 ` [PATCH 2/2] phy: qcom: qmp-pcie: Update PCIe0 " Qiang Yu @ 2024-01-24 8:58 ` neil.armstrong 2024-01-25 2:59 ` Qiang Yu 2024-01-30 17:39 ` Vinod Koul 3 siblings, 1 reply; 9+ messages in thread From: neil.armstrong @ 2024-01-24 8:58 UTC (permalink / raw) To: Qiang Yu, agross, andersson, konrad.dybcio, vkoul, kishon Cc: linux-arm-msm, linux-phy, linux-kernel, quic_cang, quic_mrana On 28/12/2023 06:42, Qiang Yu wrote: > Align PCIe0/PCIe1 PHY settings with SM8550 latest PCIe PHY Hardware > Programming Guide. > > Can Guo (1): > phy: qcom: qmp-pcie: Update PCIe1 PHY settings for SM8550 > > Qiang Yu (1): > phy: qcom: qmp-pcie: Update PCIe0 PHY settings for SM8550 > > drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 20 ++++++++++++++------ > drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6.h | 2 ++ > drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_20.h | 2 ++ > drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_20.h | 1 + > .../phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_20.h | 2 ++ > 5 files changed, 21 insertions(+), 6 deletions(-) > - On SM8550-HDK: # lspci 0000:00:00.0 PCI bridge: Qualcomm Device 0113 0000:01:00.0 Network controller: Qualcomm Device 1107 (rev 01) 0001:00:00.0 PCI bridge: Qualcomm Device 0113 0001:01:00.0 Non-Volatile memory controller: Phison Electronics Corporation E12 NVMe Controller (rev 01) # lspci -nvv 0000:00:00.0 0604: 17cb:0113 (prog-if 00 [Normal decode]) LnkCap: Port #0, Speed 8GT/s, Width x2, ASPM L0s L1, Exit Latency L0s <4us, L1 <8us LnkSta: Speed 5GT/s, Width x2 0001:00:00.0 0604: 17cb:0113 (prog-if 00 [Normal decode]) LnkCap: Port #0, Speed 16GT/s, Width x2, ASPM L0s L1, Exit Latency L0s <4us, L1 <8us LnkSta: Speed 8GT/s, Width x2 Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-HDK - On SM8550-QRD: # lspci 00:00.0 PCI bridge: Qualcomm Device 0113 01:00.0 Network controller: Qualcomm Device 1107 (rev 01) # lspci -nvv LnkCap: Port #0, Speed 8GT/s, Width x2, ASPM L0s L1, Exit Latency L0s <4us, L1 <8us LnkSta: Speed 5GT/s, Width x2 Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD Thanks, Neil ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 0/2] phy: qcom: qmp-pcie: Update PCIe PHY settings for SM8550 2024-01-24 8:58 ` [PATCH 0/2] phy: qcom: qmp-pcie: Update PCIe " neil.armstrong @ 2024-01-25 2:59 ` Qiang Yu 2024-01-25 7:53 ` neil.armstrong 0 siblings, 1 reply; 9+ messages in thread From: Qiang Yu @ 2024-01-25 2:59 UTC (permalink / raw) To: neil.armstrong, agross, andersson, konrad.dybcio, vkoul, kishon Cc: linux-arm-msm, linux-phy, linux-kernel, quic_cang, quic_mrana On 1/24/2024 4:58 PM, neil.armstrong@linaro.org wrote: > On 28/12/2023 06:42, Qiang Yu wrote: >> Align PCIe0/PCIe1 PHY settings with SM8550 latest PCIe PHY Hardware >> Programming Guide. >> >> Can Guo (1): >> phy: qcom: qmp-pcie: Update PCIe1 PHY settings for SM8550 >> >> Qiang Yu (1): >> phy: qcom: qmp-pcie: Update PCIe0 PHY settings for SM8550 >> >> drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 20 >> ++++++++++++++------ >> drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6.h | 2 ++ >> drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_20.h | 2 ++ >> drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_20.h | 1 + >> .../phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_20.h | 2 ++ >> 5 files changed, 21 insertions(+), 6 deletions(-) >> > > - On SM8550-HDK: > # lspci > 0000:00:00.0 PCI bridge: Qualcomm Device 0113 > 0000:01:00.0 Network controller: Qualcomm Device 1107 (rev 01) > 0001:00:00.0 PCI bridge: Qualcomm Device 0113 > 0001:01:00.0 Non-Volatile memory controller: Phison Electronics > Corporation E12 NVMe Controller (rev 01) > > > # lspci -nvv > 0000:00:00.0 0604: 17cb:0113 (prog-if 00 [Normal decode]) > LnkCap: Port #0, Speed 8GT/s, Width x2, ASPM L0s L1, Exit > Latency L0s <4us, L1 <8us > LnkSta: Speed 5GT/s, Width x2 > 0001:00:00.0 0604: 17cb:0113 (prog-if 00 [Normal decode]) > LnkCap: Port #0, Speed 16GT/s, Width x2, ASPM L0s L1, Exit > Latency L0s <4us, L1 <8us > LnkSta: Speed 8GT/s, Width x2 > > Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-HDK > > - On SM8550-QRD: > # lspci > 00:00.0 PCI bridge: Qualcomm Device 0113 > 01:00.0 Network controller: Qualcomm Device 1107 (rev 01) > > # lspci -nvv > LnkCap: Port #0, Speed 8GT/s, Width x2, ASPM L0s L1, Exit > Latency L0s <4us, L1 <8us > LnkSta: Speed 5GT/s, Width x2 > > Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD > > Thanks, > Neil Hi Neil, Thanks for testing this patch. I verified on aim300, did not see speed downgrade. Let me have a try on HDK8550. Thanks, Qiang ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 0/2] phy: qcom: qmp-pcie: Update PCIe PHY settings for SM8550 2024-01-25 2:59 ` Qiang Yu @ 2024-01-25 7:53 ` neil.armstrong 2024-01-25 9:51 ` Konrad Dybcio 0 siblings, 1 reply; 9+ messages in thread From: neil.armstrong @ 2024-01-25 7:53 UTC (permalink / raw) To: Qiang Yu, agross, andersson, konrad.dybcio, vkoul, kishon Cc: linux-arm-msm, linux-phy, linux-kernel, quic_cang, quic_mrana On 25/01/2024 03:59, Qiang Yu wrote: > > On 1/24/2024 4:58 PM, neil.armstrong@linaro.org wrote: >> On 28/12/2023 06:42, Qiang Yu wrote: >>> Align PCIe0/PCIe1 PHY settings with SM8550 latest PCIe PHY Hardware >>> Programming Guide. >>> >>> Can Guo (1): >>> phy: qcom: qmp-pcie: Update PCIe1 PHY settings for SM8550 >>> >>> Qiang Yu (1): >>> phy: qcom: qmp-pcie: Update PCIe0 PHY settings for SM8550 >>> >>> drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 20 ++++++++++++++------ >>> drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6.h | 2 ++ >>> drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_20.h | 2 ++ >>> drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_20.h | 1 + >>> .../phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_20.h | 2 ++ >>> 5 files changed, 21 insertions(+), 6 deletions(-) >>> >> >> - On SM8550-HDK: >> # lspci >> 0000:00:00.0 PCI bridge: Qualcomm Device 0113 >> 0000:01:00.0 Network controller: Qualcomm Device 1107 (rev 01) >> 0001:00:00.0 PCI bridge: Qualcomm Device 0113 >> 0001:01:00.0 Non-Volatile memory controller: Phison Electronics Corporation E12 NVMe Controller (rev 01) >> >> >> # lspci -nvv >> 0000:00:00.0 0604: 17cb:0113 (prog-if 00 [Normal decode]) >> LnkCap: Port #0, Speed 8GT/s, Width x2, ASPM L0s L1, Exit Latency L0s <4us, L1 <8us >> LnkSta: Speed 5GT/s, Width x2 >> 0001:00:00.0 0604: 17cb:0113 (prog-if 00 [Normal decode]) >> LnkCap: Port #0, Speed 16GT/s, Width x2, ASPM L0s L1, Exit Latency L0s <4us, L1 <8us >> LnkSta: Speed 8GT/s, Width x2 >> >> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-HDK >> >> - On SM8550-QRD: >> # lspci >> 00:00.0 PCI bridge: Qualcomm Device 0113 >> 01:00.0 Network controller: Qualcomm Device 1107 (rev 01) >> >> # lspci -nvv >> LnkCap: Port #0, Speed 8GT/s, Width x2, ASPM L0s L1, Exit Latency L0s <4us, L1 <8us >> LnkSta: Speed 5GT/s, Width x2 >> >> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD >> >> Thanks, >> Neil > > Hi Neil, > > Thanks for testing this patch. I verified on aim300, did not see speed downgrade. Let me have a try on HDK8550. I haven't seen speed downgrade either on the HDK8550 Neil > > Thanks, > Qiang > ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 0/2] phy: qcom: qmp-pcie: Update PCIe PHY settings for SM8550 2024-01-25 7:53 ` neil.armstrong @ 2024-01-25 9:51 ` Konrad Dybcio 2024-01-25 10:13 ` Qiang Yu 0 siblings, 1 reply; 9+ messages in thread From: Konrad Dybcio @ 2024-01-25 9:51 UTC (permalink / raw) To: neil.armstrong, Qiang Yu, agross, andersson, vkoul, kishon Cc: linux-arm-msm, linux-phy, linux-kernel, quic_cang, quic_mrana On 1/25/24 08:53, neil.armstrong@linaro.org wrote: > On 25/01/2024 03:59, Qiang Yu wrote: >> >> On 1/24/2024 4:58 PM, neil.armstrong@linaro.org wrote: >>> On 28/12/2023 06:42, Qiang Yu wrote: >>>> Align PCIe0/PCIe1 PHY settings with SM8550 latest PCIe PHY Hardware >>>> Programming Guide. >>>> >>>> Can Guo (1): >>>> phy: qcom: qmp-pcie: Update PCIe1 PHY settings for SM8550 >>>> >>>> Qiang Yu (1): >>>> phy: qcom: qmp-pcie: Update PCIe0 PHY settings for SM8550 >>>> >>>> drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 20 ++++++++++++++------ >>>> drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6.h | 2 ++ >>>> drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_20.h | 2 ++ >>>> drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_20.h | 1 + >>>> .../phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_20.h | 2 ++ >>>> 5 files changed, 21 insertions(+), 6 deletions(-) >>>> >>> >>> - On SM8550-HDK: >>> # lspci >>> 0000:00:00.0 PCI bridge: Qualcomm Device 0113 >>> 0000:01:00.0 Network controller: Qualcomm Device 1107 (rev 01) >>> 0001:00:00.0 PCI bridge: Qualcomm Device 0113 >>> 0001:01:00.0 Non-Volatile memory controller: Phison Electronics Corporation E12 NVMe Controller (rev 01) >>> >>> >>> # lspci -nvv >>> 0000:00:00.0 0604: 17cb:0113 (prog-if 00 [Normal decode]) >>> LnkCap: Port #0, Speed 8GT/s, Width x2, ASPM L0s L1, Exit Latency L0s <4us, L1 <8us >>> LnkSta: Speed 5GT/s, Width x2 >>> 0001:00:00.0 0604: 17cb:0113 (prog-if 00 [Normal decode]) >>> LnkCap: Port #0, Speed 16GT/s, Width x2, ASPM L0s L1, Exit Latency L0s <4us, L1 <8us >>> LnkSta: Speed 8GT/s, Width x2 >>> >>> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-HDK >>> >>> - On SM8550-QRD: >>> # lspci >>> 00:00.0 PCI bridge: Qualcomm Device 0113 >>> 01:00.0 Network controller: Qualcomm Device 1107 (rev 01) >>> >>> # lspci -nvv >>> LnkCap: Port #0, Speed 8GT/s, Width x2, ASPM L0s L1, Exit Latency L0s <4us, L1 <8us >>> LnkSta: Speed 5GT/s, Width x2 >>> >>> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD >>> >>> Thanks, >>> Neil >> >> Hi Neil, >> >> Thanks for testing this patch. I verified on aim300, did not see speed downgrade. Let me have a try on HDK8550. > > I haven't seen speed downgrade either on the HDK8550 I'm guessing the 5 GT/s link goes to the Wi-Fi chip, which may be negotiating a lower PCIe gen in order to save power. Konrad ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 0/2] phy: qcom: qmp-pcie: Update PCIe PHY settings for SM8550 2024-01-25 9:51 ` Konrad Dybcio @ 2024-01-25 10:13 ` Qiang Yu 0 siblings, 0 replies; 9+ messages in thread From: Qiang Yu @ 2024-01-25 10:13 UTC (permalink / raw) To: Konrad Dybcio, neil.armstrong, agross, andersson, vkoul, kishon Cc: linux-arm-msm, linux-phy, linux-kernel, quic_cang, quic_mrana On 1/25/2024 5:51 PM, Konrad Dybcio wrote: > > > On 1/25/24 08:53, neil.armstrong@linaro.org wrote: >> On 25/01/2024 03:59, Qiang Yu wrote: >>> >>> On 1/24/2024 4:58 PM, neil.armstrong@linaro.org wrote: >>>> On 28/12/2023 06:42, Qiang Yu wrote: >>>>> Align PCIe0/PCIe1 PHY settings with SM8550 latest PCIe PHY Hardware >>>>> Programming Guide. >>>>> >>>>> Can Guo (1): >>>>> phy: qcom: qmp-pcie: Update PCIe1 PHY settings for SM8550 >>>>> >>>>> Qiang Yu (1): >>>>> phy: qcom: qmp-pcie: Update PCIe0 PHY settings for SM8550 >>>>> >>>>> drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 20 >>>>> ++++++++++++++------ >>>>> drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6.h | 2 ++ >>>>> drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_20.h | 2 ++ >>>>> drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_20.h | 1 + >>>>> .../phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_20.h | 2 ++ >>>>> 5 files changed, 21 insertions(+), 6 deletions(-) >>>>> >>>> >>>> - On SM8550-HDK: >>>> # lspci >>>> 0000:00:00.0 PCI bridge: Qualcomm Device 0113 >>>> 0000:01:00.0 Network controller: Qualcomm Device 1107 (rev 01) >>>> 0001:00:00.0 PCI bridge: Qualcomm Device 0113 >>>> 0001:01:00.0 Non-Volatile memory controller: Phison Electronics >>>> Corporation E12 NVMe Controller (rev 01) >>>> >>>> >>>> # lspci -nvv >>>> 0000:00:00.0 0604: 17cb:0113 (prog-if 00 [Normal decode]) >>>> LnkCap: Port #0, Speed 8GT/s, Width x2, ASPM L0s L1, >>>> Exit Latency L0s <4us, L1 <8us >>>> LnkSta: Speed 5GT/s, Width x2 >>>> 0001:00:00.0 0604: 17cb:0113 (prog-if 00 [Normal decode]) >>>> LnkCap: Port #0, Speed 16GT/s, Width x2, ASPM L0s L1, >>>> Exit Latency L0s <4us, L1 <8us >>>> LnkSta: Speed 8GT/s, Width x2 >>>> >>>> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-HDK >>>> >>>> - On SM8550-QRD: >>>> # lspci >>>> 00:00.0 PCI bridge: Qualcomm Device 0113 >>>> 01:00.0 Network controller: Qualcomm Device 1107 (rev 01) >>>> >>>> # lspci -nvv >>>> LnkCap: Port #0, Speed 8GT/s, Width x2, ASPM L0s L1, >>>> Exit Latency L0s <4us, L1 <8us >>>> LnkSta: Speed 5GT/s, Width x2 >>>> >>>> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD >>>> >>>> Thanks, >>>> Neil >>> >>> Hi Neil, >>> >>> Thanks for testing this patch. I verified on aim300, did not see >>> speed downgrade. Let me have a try on HDK8550. >> >> I haven't seen speed downgrade either on the HDK8550 > > I'm guessing the 5 GT/s link goes to the Wi-Fi chip, which may > be negotiating a lower PCIe gen in order to save power. > > Konrad Hi Konrad,Neil. OK, I see. I misunderstood. Thanks. ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 0/2] phy: qcom: qmp-pcie: Update PCIe PHY settings for SM8550 2023-12-28 5:42 [PATCH 0/2] phy: qcom: qmp-pcie: Update PCIe PHY settings for SM8550 Qiang Yu ` (2 preceding siblings ...) 2024-01-24 8:58 ` [PATCH 0/2] phy: qcom: qmp-pcie: Update PCIe " neil.armstrong @ 2024-01-30 17:39 ` Vinod Koul 3 siblings, 0 replies; 9+ messages in thread From: Vinod Koul @ 2024-01-30 17:39 UTC (permalink / raw) To: agross, andersson, konrad.dybcio, kishon, Qiang Yu Cc: linux-arm-msm, linux-phy, linux-kernel, quic_cang, quic_mrana On Thu, 28 Dec 2023 13:42:35 +0800, Qiang Yu wrote: > Align PCIe0/PCIe1 PHY settings with SM8550 latest PCIe PHY Hardware > Programming Guide. > > Can Guo (1): > phy: qcom: qmp-pcie: Update PCIe1 PHY settings for SM8550 > > Qiang Yu (1): > phy: qcom: qmp-pcie: Update PCIe0 PHY settings for SM8550 > > [...] Applied, thanks! [1/2] phy: qcom: qmp-pcie: Update PCIe1 PHY settings for SM8550 commit: 06e34728827cb47026e80db22304d03ee83c73a8 [2/2] phy: qcom: qmp-pcie: Update PCIe0 PHY settings for SM8550 commit: 80082fc89edde66fe61ab85d23ea27b245fe73cb Best regards, -- ~Vinod ^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2024-01-30 17:39 UTC | newest] Thread overview: 9+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2023-12-28 5:42 [PATCH 0/2] phy: qcom: qmp-pcie: Update PCIe PHY settings for SM8550 Qiang Yu 2023-12-28 5:42 ` [PATCH 1/2] phy: qcom: qmp-pcie: Update PCIe1 " Qiang Yu 2023-12-28 5:42 ` [PATCH 2/2] phy: qcom: qmp-pcie: Update PCIe0 " Qiang Yu 2024-01-24 8:58 ` [PATCH 0/2] phy: qcom: qmp-pcie: Update PCIe " neil.armstrong 2024-01-25 2:59 ` Qiang Yu 2024-01-25 7:53 ` neil.armstrong 2024-01-25 9:51 ` Konrad Dybcio 2024-01-25 10:13 ` Qiang Yu 2024-01-30 17:39 ` Vinod Koul
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