[PATCH 0/4] *** SUBJECT HERE ***

[PATCH 0/4] *** SUBJECT HERE ***

[Xiaoshun Xu]

External email : Please do not click links or open attachments until you have verified the sender or the content.


From: Xiaoshun Xu <xiaoshun.xu@mediatek.com>

v1:
1. Add dt-bindings compatible and vio-idx-num attribute of MT8189
2. Add support DEVAPC of MT8189
3. Refine MT8189 DEVAPC clock control flow
4. Refine MT8189 DEVAPC interrupt handler

*** BLURB HERE ***

xiaoshun.xu (4):
  dt-bindings: soc: devapc: Add for support MT8189
  soc: mediatek: mtk-devapc: Add support for MT8189 DEVAPC
  soc: mediatek: mtk-devapc: refine DEVAPC clock control
  soc: mediatek: mtk-devapc: refine devapc interrupt handler

 .../bindings/soc/mediatek/devapc.yaml         |   6 +
 drivers/soc/mediatek/mtk-devapc.c             | 176 ++++++++++++++----
 2 files changed, 144 insertions(+), 38 deletions(-)

--
2.45.2

[PATCH 1/4] dt-bindings: soc: devapc: Add for support MT8189

[Xiaoshun Xu]

External email : Please do not click links or open attachments until you have verified the sender or the content.


From: "xiaoshun.xu" <xiaoshun.xu@mediatek.com>

Add compatible and vio-idx-num attribute of MT8189

Signed-off-by: xiaoshun.xu <xiaoshun.xu@mediatek.com>
---
 Documentation/devicetree/bindings/soc/mediatek/devapc.yaml | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/soc/mediatek/devapc.yaml b/Documentation/devicetree/bindings/soc/mediatek/devapc.yaml
index 99e2caafeadf..4068786d3bb1 100644
--- a/Documentation/devicetree/bindings/soc/mediatek/devapc.yaml
+++ b/Documentation/devicetree/bindings/soc/mediatek/devapc.yaml
@@ -21,6 +21,7 @@ properties:
     enum:
       - mediatek,mt6779-devapc
       - mediatek,mt8186-devapc
+      - mediatek,mt8189-devapc

   reg:
     description: The base address of devapc register bank
@@ -30,6 +31,10 @@ properties:
     description: A single interrupt specifier
     maxItems: 1

+  vio-idx-num:
+    description: Describe the number of bus slaves controlled by devapc
+    maxItems: 1
+
   clocks:
     description: Contains module clock source and clock names
     maxItems: 1
@@ -55,6 +60,7 @@ examples:
     devapc: devapc@10207000 {
       compatible = "mediatek,mt6779-devapc";
       reg = <0x10207000 0x1000>;
+      vio-idx-num = <132>;
       interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_LOW>;
       clocks = <&infracfg_ao CLK_INFRA_DEVICE_APC>;
       clock-names = "devapc-infra-clock";
--
2.45.2

[PATCH 2/4] soc: mediatek: mtk-devapc: Add support for MT8189 DEVAPC

[Xiaoshun Xu]

External email : Please do not click links or open attachments until you have verified the sender or the content.


From: "xiaoshun.xu" <xiaoshun.xu@mediatek.com>

Add support for MT8189 DEVAPC, DEVAPC debug registers have new version,
so refine the structure of devapc_regs_ofs_xxxx to devapc_regs_ofs_verX,
and rename the infra_base to base in mtk_devapc_context because DEVAPC
not only access the infra_base to dump debug information when violation
happens

Signed-off-by: xiaoshun.xu <xiaoshun.xu@mediatek.com>
---
 drivers/soc/mediatek/mtk-devapc.c | 146 +++++++++++++++++++++++-------
 1 file changed, 114 insertions(+), 32 deletions(-)

diff --git a/drivers/soc/mediatek/mtk-devapc.c b/drivers/soc/mediatek/mtk-devapc.c
index f54c966138b5..6dbec4016a24 100644
--- a/drivers/soc/mediatek/mtk-devapc.c
+++ b/drivers/soc/mediatek/mtk-devapc.c
@@ -26,9 +26,19 @@ struct mtk_devapc_vio_dbgs {
                        u32 addr_h:4;
                        u32 resv:4;
                } dbg0_bits;
+
+               struct {
+                       u32 dmnid:6;
+                       u32 vio_w:1;
+                       u32 vio_r:1;
+                       u32 addr_h:4;
+                       u32 resv:20;
+               } dbg0_bits_ver2;
        };

        u32 vio_dbg1;
+       u32 vio_dbg2;
+       u32 vio_dbg3;
 };

 struct mtk_devapc_regs_ofs {
@@ -37,6 +47,8 @@ struct mtk_devapc_regs_ofs {
        u32 vio_sta_offset;
        u32 vio_dbg0_offset;
        u32 vio_dbg1_offset;
+       u32 vio_dbg2_offset;
+       u32 vio_dbg3_offset;
        u32 apc_con_offset;
        u32 vio_shift_sta_offset;
        u32 vio_shift_sel_offset;
@@ -44,16 +56,20 @@ struct mtk_devapc_regs_ofs {
 };

 struct mtk_devapc_data {
-       /* numbers of violation index */
-       u32 vio_idx_num;
+       u32 version;
+       /* Default numbers of violation index */
+       u32 default_vio_idx_num;
        const struct mtk_devapc_regs_ofs *regs_ofs;
 };

 struct mtk_devapc_context {
        struct device *dev;
-       void __iomem *infra_base;
+       void __iomem *base;
        struct clk *infra_clk;
        const struct mtk_devapc_data *data;
+
+       /* numbers of violation index */
+       u32 vio_idx_num;
 };

 static void clear_vio_status(struct mtk_devapc_context *ctx)
@@ -61,12 +77,12 @@ static void clear_vio_status(struct mtk_devapc_context *ctx)
        void __iomem *reg;
        int i;

-       reg = ctx->infra_base + ctx->data->regs_ofs->vio_sta_offset;
+       reg = ctx->base + ctx->data->regs_ofs->vio_sta_offset;

-       for (i = 0; i < VIO_MOD_TO_REG_IND(ctx->data->vio_idx_num) - 1; i++)
+       for (i = 0; i < VIO_MOD_TO_REG_IND(ctx->vio_idx_num - 1); i++)
                writel(GENMASK(31, 0), reg + 4 * i);

-       writel(GENMASK(VIO_MOD_TO_REG_OFF(ctx->data->vio_idx_num) - 1, 0),
+       writel(GENMASK(VIO_MOD_TO_REG_OFF(ctx->vio_idx_num - 1), 0),
               reg + 4 * i);
 }

@@ -76,22 +92,22 @@ static void mask_module_irq(struct mtk_devapc_context *ctx, bool mask)
        u32 val;
        int i;

-       reg = ctx->infra_base + ctx->data->regs_ofs->vio_mask_offset;
+       reg = ctx->base + ctx->data->regs_ofs->vio_mask_offset;

        if (mask)
                val = GENMASK(31, 0);
        else
                val = 0;

-       for (i = 0; i < VIO_MOD_TO_REG_IND(ctx->data->vio_idx_num) - 1; i++)
+       for (i = 0; i < VIO_MOD_TO_REG_IND(ctx->vio_idx_num - 1); i++)
                writel(val, reg + 4 * i);

        val = readl(reg + 4 * i);
        if (mask)
-               val |= GENMASK(VIO_MOD_TO_REG_OFF(ctx->data->vio_idx_num) - 1,
+               val |= GENMASK(VIO_MOD_TO_REG_OFF(ctx->vio_idx_num - 1),
                               0);
        else
-               val &= ~GENMASK(VIO_MOD_TO_REG_OFF(ctx->data->vio_idx_num) - 1,
+               val &= ~GENMASK(VIO_MOD_TO_REG_OFF(ctx->vio_idx_num - 1),
                                0);

        writel(val, reg + 4 * i);
@@ -118,11 +134,11 @@ static int devapc_sync_vio_dbg(struct mtk_devapc_context *ctx)
        int ret;
        u32 val;

-       pd_vio_shift_sta_reg = ctx->infra_base +
+       pd_vio_shift_sta_reg = ctx->base +
                               ctx->data->regs_ofs->vio_shift_sta_offset;
-       pd_vio_shift_sel_reg = ctx->infra_base +
+       pd_vio_shift_sel_reg = ctx->base +
                               ctx->data->regs_ofs->vio_shift_sel_offset;
-       pd_vio_shift_con_reg = ctx->infra_base +
+       pd_vio_shift_con_reg = ctx->base +
                               ctx->data->regs_ofs->vio_shift_con_offset;

        /* Find the minimum shift group which has violation */
@@ -163,22 +179,52 @@ static void devapc_extract_vio_dbg(struct mtk_devapc_context *ctx)
        struct mtk_devapc_vio_dbgs vio_dbgs;
        void __iomem *vio_dbg0_reg;
        void __iomem *vio_dbg1_reg;
+       void __iomem *vio_dbg2_reg;
+       void __iomem *vio_dbg3_reg;
+       u32 vio_addr_l, vio_addr_h, bus_id, domain_id;
+       u32 vio_w, vio_r;
+       u64 vio_addr;

-       vio_dbg0_reg = ctx->infra_base + ctx->data->regs_ofs->vio_dbg0_offset;
-       vio_dbg1_reg = ctx->infra_base + ctx->data->regs_ofs->vio_dbg1_offset;
+       vio_dbg0_reg = ctx->base + ctx->data->regs_ofs->vio_dbg0_offset;
+       vio_dbg1_reg = ctx->base + ctx->data->regs_ofs->vio_dbg1_offset;
+       vio_dbg2_reg = ctx->base + ctx->data->regs_ofs->vio_dbg2_offset;
+       vio_dbg3_reg = ctx->base + ctx->data->regs_ofs->vio_dbg3_offset;

        vio_dbgs.vio_dbg0 = readl(vio_dbg0_reg);
        vio_dbgs.vio_dbg1 = readl(vio_dbg1_reg);
+       if (ctx->data->version >= 2U)
+               vio_dbgs.vio_dbg2 = readl(vio_dbg2_reg);
+       if (ctx->data->version == 3U)
+               vio_dbgs.vio_dbg3 = readl(vio_dbg3_reg);
+
+       if (ctx->data->version == 1U) {
+               /* arch version 1 */
+               bus_id = vio_dbgs.dbg0_bits.mstid;
+               vio_addr = vio_dbgs.vio_dbg1;
+               domain_id = vio_dbgs.dbg0_bits.dmnid;
+               vio_w = vio_dbgs.dbg0_bits.vio_w;
+               vio_r = vio_dbgs.dbg0_bits.vio_r;
+       } else {
+               /* arch version 2 & 3 */
+               bus_id = vio_dbgs.vio_dbg1;
+
+               vio_addr_l = vio_dbgs.vio_dbg2;
+               vio_addr_h = ctx->data->version == 2U ? vio_dbgs.dbg0_bits_ver2.addr_h :
+                                                       vio_dbgs.vio_dbg3;
+               vio_addr = ((u64)vio_addr_h << 32) + vio_addr_l;
+               domain_id = vio_dbgs.dbg0_bits_ver2.dmnid;
+               vio_w = vio_dbgs.dbg0_bits_ver2.vio_w;
+               vio_r = vio_dbgs.dbg0_bits_ver2.vio_r;
+       }

        /* Print violation information */
-       if (vio_dbgs.dbg0_bits.vio_w)
+       if (vio_w)
                dev_info(ctx->dev, "Write Violation\n");
-       else if (vio_dbgs.dbg0_bits.vio_r)
+       else if (vio_r)
                dev_info(ctx->dev, "Read Violation\n");

-       dev_info(ctx->dev, "Bus ID:0x%x, Dom ID:0x%x, Vio Addr:0x%x\n",
-                vio_dbgs.dbg0_bits.mstid, vio_dbgs.dbg0_bits.dmnid,
-                vio_dbgs.vio_dbg1);
+       dev_info(ctx->dev, "Bus ID:0x%x, Dom ID:0x%x, Vio Addr:0x%llx\n",
+                bus_id, domain_id, vio_addr);
 }

 /*
@@ -203,7 +249,8 @@ static irqreturn_t devapc_violation_irq(int irq_number, void *data)
  */
 static void start_devapc(struct mtk_devapc_context *ctx)
 {
-       writel(BIT(31), ctx->infra_base + ctx->data->regs_ofs->apc_con_offset);
+
+       writel(BIT(31), ctx->base + ctx->data->regs_ofs->apc_con_offset);

        mask_module_irq(ctx, false);
 }
@@ -215,10 +262,10 @@ static void stop_devapc(struct mtk_devapc_context *ctx)
 {
        mask_module_irq(ctx, true);

-       writel(BIT(2), ctx->infra_base + ctx->data->regs_ofs->apc_con_offset);
+       writel(BIT(2), ctx->base + ctx->data->regs_ofs->apc_con_offset);
 }

-static const struct mtk_devapc_regs_ofs devapc_regs_ofs_mt6779 = {
+static const struct mtk_devapc_regs_ofs devapc_regs_ofs_ver1 = {
        .vio_mask_offset = 0x0,
        .vio_sta_offset = 0x400,
        .vio_dbg0_offset = 0x900,
@@ -229,14 +276,34 @@ static const struct mtk_devapc_regs_ofs devapc_regs_ofs_mt6779 = {
        .vio_shift_con_offset = 0xF20,
 };

+static const struct mtk_devapc_regs_ofs devapc_regs_ofs_ver2 = {
+       .vio_mask_offset = 0x0,
+       .vio_sta_offset = 0x400,
+       .vio_dbg0_offset = 0x900,
+       .vio_dbg1_offset = 0x904,
+       .vio_dbg2_offset = 0x908,
+       .vio_dbg3_offset = 0x90c,
+       .apc_con_offset = 0xF00,
+       .vio_shift_sta_offset = 0xF20,
+       .vio_shift_sel_offset = 0xF30,
+       .vio_shift_con_offset = 0xF10,
+};
+
 static const struct mtk_devapc_data devapc_mt6779 = {
-       .vio_idx_num = 511,
-       .regs_ofs = &devapc_regs_ofs_mt6779,
+       .version = 1,
+       .default_vio_idx_num = 511,
+       .regs_ofs = &devapc_regs_ofs_ver1,
 };

 static const struct mtk_devapc_data devapc_mt8186 = {
-       .vio_idx_num = 519,
-       .regs_ofs = &devapc_regs_ofs_mt6779,
+       .version = 1,
+       .default_vio_idx_num = 519,
+       .regs_ofs = &devapc_regs_ofs_ver1,
+};
+
+static const struct mtk_devapc_data devapc_mt8189 = {
+       .version = 3,
+       .regs_ofs = &devapc_regs_ofs_ver2,
 };

 static const struct of_device_id mtk_devapc_dt_match[] = {
@@ -246,6 +313,9 @@ static const struct of_device_id mtk_devapc_dt_match[] = {
        }, {
                .compatible = "mediatek,mt8186-devapc",
                .data = &devapc_mt8186,
+       }, {
+               .compatible = "mediatek,mt8189-devapc",
+               .data = &devapc_mt8189,
        }, {
        },
 };
@@ -268,10 +338,21 @@ static int mtk_devapc_probe(struct platform_device *pdev)
        ctx->data = of_device_get_match_data(&pdev->dev);
        ctx->dev = &pdev->dev;

-       ctx->infra_base = of_iomap(node, 0);
-       if (!ctx->infra_base)
+       ctx->base = of_iomap(node, 0);
+       if (!ctx->base)
                return -EINVAL;

+       /*
+        * Set effective vio_idx_num from default value.
+        * If vio_idx_num is 0, get the info from DT.
+        */
+       ctx->vio_idx_num = ctx->data->default_vio_idx_num;
+       if (ctx->vio_idx_num == 0)
+               if (of_property_read_u32(node,
+                                        "vio-idx-num",
+                                        &ctx->vio_idx_num))
+                       return -EINVAL;
+
        devapc_irq = irq_of_parse_and_map(node, 0);
        if (!devapc_irq) {
                ret = -EINVAL;
@@ -296,7 +377,7 @@ static int mtk_devapc_probe(struct platform_device *pdev)
        return 0;

 err:
-       iounmap(ctx->infra_base);
+       iounmap(ctx->base);
        return ret;
 }

@@ -305,12 +386,13 @@ static void mtk_devapc_remove(struct platform_device *pdev)
        struct mtk_devapc_context *ctx = platform_get_drvdata(pdev);

        stop_devapc(ctx);
-       iounmap(ctx->infra_base);
+
+       iounmap(ctx->base);
 }

 static struct platform_driver mtk_devapc_driver = {
        .probe = mtk_devapc_probe,
-       .remove = mtk_devapc_remove,
+       .remove_new = mtk_devapc_remove,
        .driver = {
                .name = "mtk-devapc",
                .of_match_table = mtk_devapc_dt_match,
--
2.45.2

[PATCH 3/4] soc: mediatek: mtk-devapc: refine DEVAPC clock control

[Xiaoshun Xu]

External email : Please do not click links or open attachments until you have verified the sender or the content.


From: "xiaoshun.xu" <xiaoshun.xu@mediatek.com>

Because the new DEVAPC design, DEVAPC clock is controlled by
HW power domains, the control flow of DEVAPC clock is not
necessary, but to maintain compatibility with legacy ICs,
keep this part of code.

Signed-off-by: xiaoshun.xu <xiaoshun.xu@mediatek.com>
---
 drivers/soc/mediatek/mtk-devapc.c | 21 ++++++++++++++++-----
 1 file changed, 16 insertions(+), 5 deletions(-)

diff --git a/drivers/soc/mediatek/mtk-devapc.c b/drivers/soc/mediatek/mtk-devapc.c
index 6dbec4016a24..18964d82ff08 100644
--- a/drivers/soc/mediatek/mtk-devapc.c
+++ b/drivers/soc/mediatek/mtk-devapc.c
@@ -359,16 +359,25 @@ static int mtk_devapc_probe(struct platform_device *pdev)
                goto err;
        }

-       ctx->infra_clk = devm_clk_get_enabled(&pdev->dev, "devapc-infra-clock");
+       /*
+        * The new design of DAPC clock is controlled by HW power domains,
+        * making it unnecessary to provide the clock control driver.
+        */
+       ctx->infra_clk = devm_clk_get_optional(&pdev->dev, "devapc-infra-clock");
        if (IS_ERR(ctx->infra_clk)) {
-               ret = -EINVAL;
-               goto err;
+               dev_dbg(ctx->dev, "Cannot get devapc clock from CCF\n");
+               ctx->infra_clk = NULL;
+       } else {
+               if (clk_prepare_enable(ctx->infra_clk))
+                       return -EINVAL;
        }

        ret = devm_request_irq(&pdev->dev, devapc_irq, devapc_violation_irq,
-                              IRQF_TRIGGER_NONE, "devapc", ctx);
-       if (ret)
+                              IRQF_TRIGGER_NONE | IRQF_SHARED, "devapc", ctx);
+       if (ret) {
+               clk_disable_unprepare(ctx->infra_clk);
                goto err;
+       }

        platform_set_drvdata(pdev, ctx);

@@ -387,6 +396,8 @@ static void mtk_devapc_remove(struct platform_device *pdev)

        stop_devapc(ctx);

+       clk_disable_unprepare(ctx->infra_clk);
+
        iounmap(ctx->base);
 }

--
2.45.2

[PATCH 4/4] soc: mediatek: mtk-devapc: refine DEVAPC irq handler

[Xiaoshun Xu]

External email : Please do not click links or open attachments until you have verified the sender or the content.


From: "xiaoshun.xu" <xiaoshun.xu@mediatek.com>

Because the violation IRQ uses a while loop, it might cause the
system to remain in the interrupt handler indefinitely. We are
currently optimizing this part of the process to handle only 20
violations for debug violation issues, and then exit the loop

Signed-off-by: xiaoshun.xu <xiaoshun.xu@mediatek.com>
---
 drivers/soc/mediatek/mtk-devapc.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/soc/mediatek/mtk-devapc.c b/drivers/soc/mediatek/mtk-devapc.c
index 18964d82ff08..30b7ee8b880a 100644
--- a/drivers/soc/mediatek/mtk-devapc.c
+++ b/drivers/soc/mediatek/mtk-devapc.c
@@ -15,6 +15,8 @@
 #define VIO_MOD_TO_REG_IND(m)  ((m) / 32)
 #define VIO_MOD_TO_REG_OFF(m)  ((m) % 32)

+#define MAX_VIO_NUM 20
+
 struct mtk_devapc_vio_dbgs {
        union {
                u32 vio_dbg0;
@@ -234,13 +236,18 @@ static void devapc_extract_vio_dbg(struct mtk_devapc_context *ctx)
  */
 static irqreturn_t devapc_violation_irq(int irq_number, void *data)
 {
+       unsigned int vio_num = 0;
        struct mtk_devapc_context *ctx = data;

-       while (devapc_sync_vio_dbg(ctx))
+       mask_module_irq(ctx, true);
+
+       for (vio_num = 0; (vio_num < MAX_VIO_NUM) && (devapc_sync_vio_dbg(ctx)); ++vio_num)
                devapc_extract_vio_dbg(ctx);

        clear_vio_status(ctx);

+       mask_module_irq(ctx, false);
+
        return IRQ_HANDLED;
 }

--
2.45.2

Re: [PATCH 1/4] dt-bindings: soc: devapc: Add for support MT8189

[Rob Herring (Arm)]

On Fri, 12 Dec 2025 11:13:42 +0800, Xiaoshun Xu wrote:
> 
> External email : Please do not click links or open attachments until you have verified the sender or the content.
> 
> 
> From: "xiaoshun.xu" <xiaoshun.xu@mediatek.com>
> 
> Add compatible and vio-idx-num attribute of MT8189
> 
> Signed-off-by: xiaoshun.xu <xiaoshun.xu@mediatek.com>
> ---
>  Documentation/devicetree/bindings/soc/mediatek/devapc.yaml | 6 ++++++
>  1 file changed, 6 insertions(+)
> 

My bot found errors running 'make dt_binding_check' on your patch:

yamllint warnings/errors:

dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/soc/mediatek/devapc.yaml: vio-idx-num: missing type definition

doc reference errors (make refcheckdocs):

See https://patchwork.kernel.org/project/devicetree/patch/20251212031450.489128-2-xiaoshun.xu@mediatek.corp-partner.google.com

The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.

Re: [PATCH 1/4] dt-bindings: soc: devapc: Add for support MT8189

[Krzysztof Kozlowski]

On 12/12/2025 05:29, Rob Herring (Arm) wrote:
> 
> On Fri, 12 Dec 2025 11:13:42 +0800, Xiaoshun Xu wrote:
>>
>> External email : Please do not click links or open attachments until you have verified the sender or the content.
>>
>>
>> From: "xiaoshun.xu" <xiaoshun.xu@mediatek.com>
>>
>> Add compatible and vio-idx-num attribute of MT8189
>>
>> Signed-off-by: xiaoshun.xu <xiaoshun.xu@mediatek.com>
>> ---
>>  Documentation/devicetree/bindings/soc/mediatek/devapc.yaml | 6 ++++++
>>  1 file changed, 6 insertions(+)
>>
> 
> My bot found errors running 'make dt_binding_check' on your patch:
> 
> yamllint warnings/errors:
> 
> dtschema/dtc warnings/errors:
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/soc/mediatek/devapc.yaml: vio-idx-num: missing type definition
> 
> doc reference errors (make refcheckdocs):
> 


None of these patches here managed to pass spam checks on my inbox, so I
got only this report. Considering patch containing "External email"
clause in the commit msg, I would say posting was somehow non-standard
or just broken.

That's obviously a no-go and finally mediatek corp-partners need to act
on these poor postings (not an exception here).

Best regards,
Krzysztof

Re: [PATCH 0/4] *** SUBJECT HERE ***

[Xiaoshun Xu (徐晓顺)]

On Fri, 2025-12-12 at 11:13 +0800, Xiaoshun Xu wrote:
Sorry, there are some mistakes in my patch sets. I will provide a new
version later. Thank you!
> 
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
> 
> 
> From: Xiaoshun Xu <xiaoshun.xu@mediatek.com>
> 
> v1:
> 1. Add dt-bindings compatible and vio-idx-num attribute of MT8189
> 2. Add support DEVAPC of MT8189
> 3. Refine MT8189 DEVAPC clock control flow
> 4. Refine MT8189 DEVAPC interrupt handler
> 
> *** BLURB HERE ***
> 
> xiaoshun.xu (4):
>   dt-bindings: soc: devapc: Add for support MT8189
>   soc: mediatek: mtk-devapc: Add support for MT8189 DEVAPC
>   soc: mediatek: mtk-devapc: refine DEVAPC clock control
>   soc: mediatek: mtk-devapc: refine devapc interrupt handler
> 
>  .../bindings/soc/mediatek/devapc.yaml         |   6 +
>  drivers/soc/mediatek/mtk-devapc.c             | 176 ++++++++++++++--
> --
>  2 files changed, 144 insertions(+), 38 deletions(-)
> 
> --
> 2.45.2
>