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From: Vadim Fedorenko <vadim.fedorenko@linux.dev>
To: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>,
	Manivannan Sadhasivam <mani@kernel.org>,
	Richard Cochran <richardcochran@gmail.com>
Cc: mhi@lists.linux.dev, linux-arm-msm@vger.kernel.org,
	linux-kernel@vger.kernel.org, netdev@vger.kernel.org,
	Vivek Pernamitta <quic_vpernami@quicinc.com>
Subject: Re: [PATCH v2 2/6] bus: mhi: host: Add support for non-posted TSC timesync feature
Date: Tue, 14 Apr 2026 18:46:14 +0100	[thread overview]
Message-ID: <cbe3bd2a-4cbe-43db-bb19-37b2d8890eb4@linux.dev> (raw)
In-Reply-To: <20260411-tsc_timesync-v2-2-6f25f72987b3@oss.qualcomm.com>

On 11/04/2026 09:12, Krishna Chaitanya Chundru wrote:
> From: Vivek Pernamitta <quic_vpernami@quicinc.com>
> 
> Implement non-posted time synchronization as described in section 5.1.1
> of the MHI v1.2 specification. The host disables low-power link states
> to minimize latency, reads the local time, issues a MMIO read to the
> device's TIME register.
> 
> Add support for initializing this feature and export a function to be
> used by the drivers which does the time synchronization.
> 
> MHI reads the device time registers in the MMIO address space pointed to
> by the capability register after disabling all low power modes and keeping
> MHI in M0. Before and after MHI reads, the local time is captured
> and shared for processing.

[...]

> +	/*
> +	 * time critical code to fetch device time, delay between these two steps
> +	 * should be deterministic as possible.
> +	 */
> +	preempt_disable();
> +	local_irq_disable();
> +
> +	time->t_host_pre = ktime_get_real();
> +
> +	/*
> +	 * To ensure the PCIe link is in L0 when ASPM is enabled, perform series
> +	 * of back-to-back reads. This is necessary because the link may be in a
> +	 * low-power state (e.g., L1 or L1ss), and need to be forced it to
> +	 * transition to L0.
> +	 */
> +	for (i = 0; i < MHI_NUM_BACK_TO_BACK_READS; i++) {
> +		ret = mhi_read_reg(mhi_cntrl, mhi_tsync->time_reg,
> +				   TSC_TIMESYNC_TIME_LOW_OFFSET, &time->t_dev_lo);
> +
> +		ret = mhi_read_reg(mhi_cntrl, mhi_tsync->time_reg,
> +				   TSC_TIMESYNC_TIME_HIGH_OFFSET, &time->t_dev_hi);
> +	}
> +
> +	time->t_host_post = ktime_get_real();
> +
> +	local_irq_enable();
> +	preempt_enable();

PTP_SYS_OFFSET_EXTENDED receives the amount of samples to read from user
space, you can use it instead of MHI_NUM_BACK_TO_BACK_READS, and in this
case it's better to grab host-pre and host-post time for a single
register read.

Also, PTP_SYS_OFFSET_EXTENDED was improved and currently supports
multiple clockids as system time, it's good to account for it.

  parent reply	other threads:[~2026-04-14 17:46 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-04-11  8:12 [PATCH v2 0/6] bus: mhi: host: mhi_phc: Add support for PHC over MHI Krishna Chaitanya Chundru
2026-04-11  8:12 ` [PATCH v2 1/6] bus: mhi: host: Add support to read MHI capabilities Krishna Chaitanya Chundru
2026-04-11  8:12 ` [PATCH v2 2/6] bus: mhi: host: Add support for non-posted TSC timesync feature Krishna Chaitanya Chundru
2026-04-11 13:43   ` Jie Gan
2026-04-13  6:42   ` Manivannan Sadhasivam
2026-04-13  7:27   ` Manivannan Sadhasivam
2026-04-14 17:46   ` Vadim Fedorenko [this message]
2026-04-11  8:12 ` [PATCH v2 3/6] bus: mhi: host: Add support for 64bit register reads and writes Krishna Chaitanya Chundru
2026-04-11  8:12 ` [PATCH v2 4/6] bus: mhi: pci_generic: Add support for 64 bit register read & write Krishna Chaitanya Chundru
2026-04-11  8:12 ` [PATCH v2 5/6] bus: mhi: host: Update the Time sync logic to read 64 bit register value Krishna Chaitanya Chundru
2026-04-11  8:12 ` [PATCH v2 6/6] bus: mhi: host: mhi_phc: Add support for PHC over MHI Krishna Chaitanya Chundru
2026-04-11 13:50   ` Jie Gan
2026-04-13  8:06   ` Manivannan Sadhasivam
2026-04-12 15:09 ` [PATCH v2 0/6] " Jakub Kicinski
2026-04-13  5:44   ` Manivannan Sadhasivam

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