* [PATCH v3 0/2] Add basic support for MYIR Remi Pi
@ 2025-01-31 9:57 Julien Massot
2025-01-31 9:57 ` [PATCH v3 1/2] dt-bindings: soc: renesas: Document MYIR Remi Pi board Julien Massot
2025-01-31 9:58 ` [PATCH v3 2/2] arm64: renesas: add initial support for MYIR Remi Pi Julien Massot
0 siblings, 2 replies; 8+ messages in thread
From: Julien Massot @ 2025-01-31 9:57 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, kernel
Cc: linux-renesas-soc, devicetree, linux-kernel, Julien Massot,
Krzysztof Kozlowski
The Remi Pi is a compact board based on the Renesas RZ/G2L SoC.
This initial patchset add support for basic functions:
- UART
- I2C
- HDMI
- Ethernet
More work is needed to support the remaining functions such as
USB Type C, SD card, Audio, Wi-Fi and Bluetooth.
Some schematics are available at https://down.myir-tech.com/RemiPi/
Signed-off-by: Julien Massot <julien.massot@collabora.com>
---
Changes in v3:
- Use 'MYIR' spelling consistently
- Removed: scif1, and scif2 nodes, and enable scif4
- Changed regulator-1p8v vin-supply to reg_5p0v
- Added 'reset-gpios' for boh ethernet phys
- Dropped unused 'spi0' pinctrl
- Removed 'sdhi0_pins_uhs' duplicated pinctrl
- Removed 'usb1_pins' they are not mentionned in the schematics
- Sort all the references to nodes alphabetically
- Link to v2: https://lore.kernel.org/r/20250127-myir-remi-pi-v2-0-7bd3a1c62752@collabora.com
Changes in v2:
- Reorder Makefile entry to be sorted
- Remove underscore from DT nodes names
- Fix compatible for ethernet nodes and remove uneeded properties
- Remove uneeded x1-clock
- Link to v1: https://lore.kernel.org/r/20250122-myir-remi-pi-v1-0-0e44e1cb8a90@collabora.com
---
Julien Massot (2):
dt-bindings: soc: renesas: Document MYIR Remi Pi board
arm64: renesas: add initial support for MYIR Remi Pi
.../devicetree/bindings/soc/renesas/renesas.yaml | 7 +
arch/arm64/boot/dts/renesas/Makefile | 1 +
.../arm64/boot/dts/renesas/r9a07g044l2-remi-pi.dts | 351 +++++++++++++++++++++
3 files changed, 359 insertions(+)
---
base-commit: c4b9570cfb63501638db720f3bee9f6dfd044b82
change-id: 20250122-myir-remi-pi-94d6055f5879
Best regards,
--
Julien Massot <julien.massot@collabora.com>
^ permalink raw reply [flat|nested] 8+ messages in thread* [PATCH v3 1/2] dt-bindings: soc: renesas: Document MYIR Remi Pi board 2025-01-31 9:57 [PATCH v3 0/2] Add basic support for MYIR Remi Pi Julien Massot @ 2025-01-31 9:57 ` Julien Massot 2025-02-07 8:45 ` Geert Uytterhoeven 2025-01-31 9:58 ` [PATCH v3 2/2] arm64: renesas: add initial support for MYIR Remi Pi Julien Massot 1 sibling, 1 reply; 8+ messages in thread From: Julien Massot @ 2025-01-31 9:57 UTC (permalink / raw) To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski, Conor Dooley, kernel Cc: linux-renesas-soc, devicetree, linux-kernel, Julien Massot, Krzysztof Kozlowski Document the MYIR Remi Pi" which is based on the Renesas RZ/G2L ("R9A07G044L2") SoC. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Julien Massot <julien.massot@collabora.com> --- Documentation/devicetree/bindings/soc/renesas/renesas.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml index b7acb65bdecd2a3828f5757735eb473c39f27b57..3e02bc2e17483cf53679a130eaaa5943d2f9a2a7 100644 --- a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml +++ b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml @@ -491,6 +491,13 @@ properties: - renesas,r9a07g044l2 # Dual Cortex-A55 RZ/G2L - const: renesas,r9a07g044 + - items: + - enum: + # MYIR Remi Pi SBC (MYB-YG2LX-REMI) + - myir,remi-pi + - const: renesas,r9a07g044l2 + - const: renesas,r9a07g044 + - description: RZ/V2L (R9A07G054) items: - enum: -- 2.48.1 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH v3 1/2] dt-bindings: soc: renesas: Document MYIR Remi Pi board 2025-01-31 9:57 ` [PATCH v3 1/2] dt-bindings: soc: renesas: Document MYIR Remi Pi board Julien Massot @ 2025-02-07 8:45 ` Geert Uytterhoeven 0 siblings, 0 replies; 8+ messages in thread From: Geert Uytterhoeven @ 2025-02-07 8:45 UTC (permalink / raw) To: Julien Massot Cc: Magnus Damm, Rob Herring, Krzysztof Kozlowski, Conor Dooley, kernel, linux-renesas-soc, devicetree, linux-kernel, Krzysztof Kozlowski On Fri, 31 Jan 2025 at 10:58, Julien Massot <julien.massot@collabora.com> wrote: > Document the MYIR Remi Pi" which is based on the Renesas > RZ/G2L ("R9A07G044L2") SoC. > > Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > Signed-off-by: Julien Massot <julien.massot@collabora.com> Thanks, will queue in renesas-devel for v6.15. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v3 2/2] arm64: renesas: add initial support for MYIR Remi Pi 2025-01-31 9:57 [PATCH v3 0/2] Add basic support for MYIR Remi Pi Julien Massot 2025-01-31 9:57 ` [PATCH v3 1/2] dt-bindings: soc: renesas: Document MYIR Remi Pi board Julien Massot @ 2025-01-31 9:58 ` Julien Massot 2025-01-31 10:22 ` Krzysztof Kozlowski 2025-02-06 11:16 ` Geert Uytterhoeven 1 sibling, 2 replies; 8+ messages in thread From: Julien Massot @ 2025-01-31 9:58 UTC (permalink / raw) To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski, Conor Dooley, kernel Cc: linux-renesas-soc, devicetree, linux-kernel, Julien Massot Add basic support for the MYIR Remi Pi (based on r9a07g044l2): - UART - i2c - emmc - USB host - HDMI output - Ethernet Signed-off-by: Julien Massot <julien.massot@collabora.com> --- arch/arm64/boot/dts/renesas/Makefile | 1 + .../arm64/boot/dts/renesas/r9a07g044l2-remi-pi.dts | 351 +++++++++++++++++++++ 2 files changed, 352 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index 97228a3cb99c163d299b508ee7653aafea3d1a3a..6824c63a1b154acf13de7e3d44bb10d5754738c4 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -126,6 +126,7 @@ dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-smarc-cru-csi-ov5645.dtbo r9a07g044c2-smarc-cru-csi-ov5645-dtbs := r9a07g044c2-smarc.dtb r9a07g044c2-smarc-cru-csi-ov5645.dtbo dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-smarc-cru-csi-ov5645.dtb +dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-remi-pi.dtb dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc.dtb dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc-cru-csi-ov5645.dtbo r9a07g044l2-smarc-cru-csi-ov5645-dtbs := r9a07g044l2-smarc.dtb r9a07g044l2-smarc-cru-csi-ov5645.dtbo diff --git a/arch/arm64/boot/dts/renesas/r9a07g044l2-remi-pi.dts b/arch/arm64/boot/dts/renesas/r9a07g044l2-remi-pi.dts new file mode 100644 index 0000000000000000000000000000000000000000..526221cd6af14ecafa199d07f6f20f848c911fa2 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a07g044l2-remi-pi.dts @@ -0,0 +1,351 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the MYIR Remi Pi + * + * Copyright (C) 2022 MYIR Electronics Corp. + * Copyright (C) 2025 Collabora Ltd. + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/rzg2l-pinctrl.h> + +#include "r9a07g044l2.dtsi" + +/ { + model = "MYIR Tech Limited Remi Pi MYB-YG2LX-REMI"; + compatible = "myir,remi-pi", "renesas,r9a07g044l2", "renesas,r9a07g044"; + + aliases { + ethernet0 = ð0; + ethernet1 = ð1; + + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + + mmc0 = &sdhi0; + + serial0 = &scif0; + serial3 = &scif3; + serial4 = &scif4; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x0 0x38000000>; + }; + + reg_5p0v: regulator-5p0v { + compatible = "regulator-fixed"; + regulator-name = "fixed-5.0V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + vin-supply = <®_5p0v>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + vin-supply = <®_5p0v>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_1p1v: regulator-vdd-core { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.1V"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + hdmi-out { + compatible = "hdmi-connector"; + type = "a"; + ddc-i2c-bus = <&i2c1>; + + port { + hdmi_con: endpoint { + remote-endpoint = <<8912_out>; + }; + }; + }; +}; + +&dsi { + status = "okay"; + + ports { + port@1 { + dsi_out: endpoint { + remote-endpoint = <<8912_in>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&du { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +ð0 { + pinctrl-0 = <ð0_pins>; + pinctrl-names = "default"; + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + status = "okay"; + + phy0: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <4>; + interrupts-extended = <&pinctrl RZG2L_GPIO(44, 2) IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&pinctrl RZG2L_GPIO(44, 3) GPIO_ACTIVE_LOW>; + }; +}; + +ð1 { + pinctrl-0 = <ð1_pins>; + pinctrl-names = "default"; + phy-handle = <&phy1>; + phy-mode = "rgmii-id"; + status = "okay"; + + phy1: ethernet-phy@6 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <6>; + interrupts-extended = <&pinctrl RZG2L_GPIO(43, 2) IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&pinctrl RZG2L_GPIO(43, 3) GPIO_ACTIVE_LOW>; + }; +}; + +&extal_clk { + clock-frequency = <24000000>; +}; + +&gpu { + mali-supply = <®_1p1v>; +}; + +&i2c0 { + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + + clock-frequency = <400000>; + status = "okay"; + + hdmi-bridge@48 { + compatible = "lontium,lt8912b"; + reg = <0x48> ; + reset-gpios = <&pinctrl RZG2L_GPIO(42, 2) GPIO_ACTIVE_LOW>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + lt8912_in: endpoint { + data-lanes = <1 2 3 4>; + remote-endpoint = <&dsi_out>; + }; + }; + + port@1 { + reg = <1>; + + lt8912_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + clock-frequency = <100000>; + status = "okay"; +}; + +&i2c2 { + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "default"; + clock-frequency = <100000>; + status = "okay"; +}; + +&i2c3 { + pinctrl-0 = <&i2c3_pins>; + pinctrl-names = "default"; + clock-frequency = <100000>; + status = "okay"; +}; + +&mtu3 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&ostm1 { + status = "okay"; +}; + +&ostm2 { + status = "okay"; +}; + +&phyrst { + status = "okay"; +}; + +&pinctrl { + eth0_pins: eth0 { + pinmux = <RZG2L_PORT_PINMUX(27, 1, 1)>, /* ET0_MDC */ + <RZG2L_PORT_PINMUX(28, 0, 1)>, /* ET0_MDIO */ + <RZG2L_PORT_PINMUX(20, 0, 1)>, /* ET0_TXC */ + <RZG2L_PORT_PINMUX(20, 1, 1)>, /* ET0_TX_CTL */ + <RZG2L_PORT_PINMUX(20, 2, 1)>, /* ET0_TXD0 */ + <RZG2L_PORT_PINMUX(21, 0, 1)>, /* ET0_TXD1 */ + <RZG2L_PORT_PINMUX(21, 1, 1)>, /* ET0_TXD2 */ + <RZG2L_PORT_PINMUX(22, 0, 1)>, /* ET0_TXD3 */ + <RZG2L_PORT_PINMUX(24, 0, 1)>, /* ET0_RXC */ + <RZG2L_PORT_PINMUX(24, 1, 1)>, /* ET0_RX_CTL */ + <RZG2L_PORT_PINMUX(25, 0, 1)>, /* ET0_RXD0 */ + <RZG2L_PORT_PINMUX(25, 1, 1)>, /* ET0_RXD1 */ + <RZG2L_PORT_PINMUX(26, 0, 1)>, /* ET0_RXD2 */ + <RZG2L_PORT_PINMUX(26, 1, 1)>; /* ET0_RXD3 */ + }; + + eth1_pins: eth1 { + pinmux = <RZG2L_PORT_PINMUX(37, 0, 1)>, /* ET1_MDC */ + <RZG2L_PORT_PINMUX(37, 1, 1)>, /* ET1_MDIO */ + <RZG2L_PORT_PINMUX(29, 0, 1)>, /* ET1_TXC */ + <RZG2L_PORT_PINMUX(29, 1, 1)>, /* ET1_TX_CTL */ + <RZG2L_PORT_PINMUX(30, 0, 1)>, /* ET1_TXD0 */ + <RZG2L_PORT_PINMUX(30, 1, 1)>, /* ET1_TXD1 */ + <RZG2L_PORT_PINMUX(31, 0, 1)>, /* ET1_TXD2 */ + <RZG2L_PORT_PINMUX(31, 1, 1)>, /* ET1_TXD3 */ + <RZG2L_PORT_PINMUX(33, 1, 1)>, /* ET1_RXC */ + <RZG2L_PORT_PINMUX(34, 0, 1)>, /* ET1_RX_CTL */ + <RZG2L_PORT_PINMUX(34, 1, 1)>, /* ET1_RXD0 */ + <RZG2L_PORT_PINMUX(35, 0, 1)>, /* ET1_RXD1 */ + <RZG2L_PORT_PINMUX(35, 1, 1)>, /* ET1_RXD2 */ + <RZG2L_PORT_PINMUX(36, 0, 1)>; /* ET1_RXD3 */ + }; + + i2c0_pins: i2c0 { + pins = "RIIC0_SDA", "RIIC0_SCL"; + input-enable; + }; + + i2c1_pins: i2c1 { + pins = "RIIC1_SDA", "RIIC1_SCL"; + input-enable; + }; + + i2c2_pins: i2c2 { + pinmux = <RZG2L_PORT_PINMUX(3, 0, 2)>, /* SDA */ + <RZG2L_PORT_PINMUX(3, 1, 2)>; /* SCL */ + }; + + i2c3_pins: i2c3 { + pinmux = <RZG2L_PORT_PINMUX(18, 0, 3)>, /* SDA */ + <RZG2L_PORT_PINMUX(18, 1, 3)>; /* SCL */ + }; + + scif0_pins: scif0 { + pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>, /* TxD */ + <RZG2L_PORT_PINMUX(38, 1, 1)>; /* RxD */ + }; + + scif3_pins: scif3 { + pinmux = <RZG2L_PORT_PINMUX(0, 0, 5)>, /* TxD */ + <RZG2L_PORT_PINMUX(0, 1, 5)>; /* RxD */ + }; + + scif4_pins: scif4 { + pinmux = <RZG2L_PORT_PINMUX(2, 0, 5)>, /* TxD */ + <RZG2L_PORT_PINMUX(2, 1, 5)>; /* RxD */ + }; + + sdhi0_pins: sd0 { + sd0_data { + pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3", + "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7"; + power-source = <1800>; + }; + + sd0_ctrl { + pins = "SD0_CLK", "SD0_CMD"; + power-source = <1800>; + }; + + sd0_rst { + pins = "SD0_RST#"; + power-source = <1800>; + }; + }; +}; + +&scif0 { + pinctrl-0 = <&scif0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&scif3 { + pinctrl-0 = <&scif3_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&scif4 { + pinctrl-0 = <&scif4_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&sdhi0 { + pinctrl-0 = <&sdhi0_pins>; + pinctrl-1 = <&sdhi0_pins>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + bus-width = <8>; + mmc-hs200-1_8v; + non-removable; + fixed-emmc-driver-type = <1>; + status = "okay"; +}; + +&usb2_phy1 { + status = "okay"; +}; -- 2.48.1 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH v3 2/2] arm64: renesas: add initial support for MYIR Remi Pi 2025-01-31 9:58 ` [PATCH v3 2/2] arm64: renesas: add initial support for MYIR Remi Pi Julien Massot @ 2025-01-31 10:22 ` Krzysztof Kozlowski 2025-02-06 11:16 ` Geert Uytterhoeven 1 sibling, 0 replies; 8+ messages in thread From: Krzysztof Kozlowski @ 2025-01-31 10:22 UTC (permalink / raw) To: Julien Massot, Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski, Conor Dooley, kernel Cc: linux-renesas-soc, devicetree, linux-kernel On 31/01/2025 10:58, Julien Massot wrote: > + > + sdhi0_pins: sd0 { > + sd0_data { Same comments as before. See DTS coding style. Best regards, Krzysztof ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v3 2/2] arm64: renesas: add initial support for MYIR Remi Pi 2025-01-31 9:58 ` [PATCH v3 2/2] arm64: renesas: add initial support for MYIR Remi Pi Julien Massot 2025-01-31 10:22 ` Krzysztof Kozlowski @ 2025-02-06 11:16 ` Geert Uytterhoeven 2025-02-07 7:16 ` Julien Massot 1 sibling, 1 reply; 8+ messages in thread From: Geert Uytterhoeven @ 2025-02-06 11:16 UTC (permalink / raw) To: Julien Massot Cc: Magnus Damm, Rob Herring, Krzysztof Kozlowski, Conor Dooley, kernel, linux-renesas-soc, devicetree, linux-kernel Hi Julien, On Fri, 31 Jan 2025 at 10:58, Julien Massot <julien.massot@collabora.com> wrote: > Add basic support for the MYIR Remi Pi (based on r9a07g044l2): > - UART > - i2c > - emmc > - USB host > - HDMI output > - Ethernet > > Signed-off-by: Julien Massot <julien.massot@collabora.com> Thanks for the update! > --- /dev/null > +++ b/arch/arm64/boot/dts/renesas/r9a07g044l2-remi-pi.dts > @@ -0,0 +1,351 @@ > +/ { > + model = "MYIR Tech Limited Remi Pi MYB-YG2LX-REMI"; > + compatible = "myir,remi-pi", "renesas,r9a07g044l2", "renesas,r9a07g044"; > + > + aliases { > + ethernet0 = ð0; > + ethernet1 = ð1; > + > + i2c0 = &i2c0; > + i2c1 = &i2c1; > + i2c2 = &i2c2; > + i2c3 = &i2c3; > + > + mmc0 = &sdhi0; > + > + serial0 = &scif0; > + serial3 = &scif3; Wasn't the plan to drop scif3, so it can be used by an RTOS running on the Cortex-A33 core? > + serial4 = &scif4; > + }; > + > + chosen { > + stdout-path = "serial0:115200n8"; > + }; > + > + memory@48000000 { > + device_type = "memory"; > + /* first 128MB is reserved for secure area. */ > + reg = <0x0 0x48000000 0x0 0x38000000>; > + }; > + > + reg_5p0v: regulator-5p0v { > + reg_3p3v: regulator-3p3v { > + reg_1p8v: regulator-1p8v { > + reg_1p1v: regulator-vdd-core { > + hdmi-out { More sorting work to do... > +}; > + sdhi0_pins: sd0 { > + sd0_data { > + pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3", > + "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7"; > + power-source = <1800>; > + }; > + > + sd0_ctrl { Here, too. Plus the underscores reported by Krzysztof. > + pins = "SD0_CLK", "SD0_CMD"; > + power-source = <1800>; > + }; > + > + sd0_rst { > + pins = "SD0_RST#"; > + power-source = <1800>; > + }; > + }; I fixed the style issues locally, so if you can confirm or deny the removal of scif3, I can fix that while applying. Thanks! Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v3 2/2] arm64: renesas: add initial support for MYIR Remi Pi 2025-02-06 11:16 ` Geert Uytterhoeven @ 2025-02-07 7:16 ` Julien Massot 2025-02-07 8:45 ` Geert Uytterhoeven 0 siblings, 1 reply; 8+ messages in thread From: Julien Massot @ 2025-02-07 7:16 UTC (permalink / raw) To: Geert Uytterhoeven Cc: Magnus Damm, Rob Herring, Krzysztof Kozlowski, Conor Dooley, kernel, linux-renesas-soc, devicetree, linux-kernel Hi Geert, Krzysztof, > On Fri, 31 Jan 2025 at 10:58, Julien Massot <julien.massot@collabora.com> wrote: > > Add basic support for the MYIR Remi Pi (based on r9a07g044l2): > > - UART > > - i2c > > - emmc > > - USB host > > - HDMI output > > - Ethernet > > > > Signed-off-by: Julien Massot <julien.massot@collabora.com> > > Thanks for the update! > > > --- /dev/null > > +++ b/arch/arm64/boot/dts/renesas/r9a07g044l2-remi-pi.dts > > @@ -0,0 +1,351 @@ > > > +/ { > > + model = "MYIR Tech Limited Remi Pi MYB-YG2LX-REMI"; > > + compatible = "myir,remi-pi", "renesas,r9a07g044l2", "renesas,r9a07g044"; > > + > > + aliases { > > + ethernet0 = ð0; > > + ethernet1 = ð1; > > + > > + i2c0 = &i2c0; > > + i2c1 = &i2c1; > > + i2c2 = &i2c2; > > + i2c3 = &i2c3; > > + > > + mmc0 = &sdhi0; > > + > > + serial0 = &scif0; > > + serial3 = &scif3; > > Wasn't the plan to drop scif3, so it can be used by an RTOS running > on the Cortex-A33 core? Sorry, indeed I forgot scif3 removal. I don't see a reason to borrow the Cortex-A33 scif. > > > + serial4 = &scif4; > > + }; > > + > > + chosen { > > + stdout-path = "serial0:115200n8"; > > + }; > > + > > + memory@48000000 { > > + device_type = "memory"; > > + /* first 128MB is reserved for secure area. */ > > + reg = <0x0 0x48000000 0x0 0x38000000>; > > + }; > > + > > + reg_5p0v: regulator-5p0v { > > > + reg_3p3v: regulator-3p3v { > > > + reg_1p8v: regulator-1p8v { > > > + reg_1p1v: regulator-vdd-core { > > > + hdmi-out { > > More sorting work to do... > > Ok, I will keep in mind for the next time. > > > > +}; > > > + sdhi0_pins: sd0 { > > + sd0_data { > > + pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3", > > + "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7"; > > + power-source = <1800>; > > + }; > > + > > + sd0_ctrl { > > Here, too. Plus the underscores reported by Krzysztof. Ok, no underscore in node names, even for the pins definition. > > > + pins = "SD0_CLK", "SD0_CMD"; > > + power-source = <1800>; > > + }; > > + > > + sd0_rst { > > + pins = "SD0_RST#"; > > + power-source = <1800>; > > + }; > > + }; > > I fixed the style issues locally, so if you can confirm or deny the removal > of scif3, I can fix that while applying. Confirmed, we should not enable scif3. Thanks -- Julien ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v3 2/2] arm64: renesas: add initial support for MYIR Remi Pi 2025-02-07 7:16 ` Julien Massot @ 2025-02-07 8:45 ` Geert Uytterhoeven 0 siblings, 0 replies; 8+ messages in thread From: Geert Uytterhoeven @ 2025-02-07 8:45 UTC (permalink / raw) To: Julien Massot Cc: Magnus Damm, Rob Herring, Krzysztof Kozlowski, Conor Dooley, kernel, linux-renesas-soc, devicetree, linux-kernel Hi Julien, On Fri, 7 Feb 2025 at 08:16, Julien Massot <julien.massot@collabora.com> wrote: > > On Fri, 31 Jan 2025 at 10:58, Julien Massot <julien.massot@collabora.com> wrote: > > > Add basic support for the MYIR Remi Pi (based on r9a07g044l2): > > > - UART > > > - i2c > > > - emmc > > > - USB host > > > - HDMI output > > > - Ethernet > > > > > > Signed-off-by: Julien Massot <julien.massot@collabora.com> > > > > Thanks for the update! > > I fixed the style issues locally, so if you can confirm or deny the removal > > of scif3, I can fix that while applying. > > Confirmed, we should not enable scif3. Thanks, Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue in renesas-devel for v6.15 with the above fixed. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2025-02-07 8:45 UTC | newest] Thread overview: 8+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2025-01-31 9:57 [PATCH v3 0/2] Add basic support for MYIR Remi Pi Julien Massot 2025-01-31 9:57 ` [PATCH v3 1/2] dt-bindings: soc: renesas: Document MYIR Remi Pi board Julien Massot 2025-02-07 8:45 ` Geert Uytterhoeven 2025-01-31 9:58 ` [PATCH v3 2/2] arm64: renesas: add initial support for MYIR Remi Pi Julien Massot 2025-01-31 10:22 ` Krzysztof Kozlowski 2025-02-06 11:16 ` Geert Uytterhoeven 2025-02-07 7:16 ` Julien Massot 2025-02-07 8:45 ` Geert Uytterhoeven
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