* [PATCH v4 0/3] Add AM64x ICSSG Ethernet support
@ 2024-02-05 9:05 MD Danish Anwar
2024-02-05 9:05 ` [PATCH v4 1/3] arm64: dts: ti: k3-am64-main: Add ICSSG IEP nodes MD Danish Anwar
` (2 more replies)
0 siblings, 3 replies; 7+ messages in thread
From: MD Danish Anwar @ 2024-02-05 9:05 UTC (permalink / raw)
To: Vignesh Raghavendra, Nishanth Menon
Cc: Andrew Lunn, Conor Dooley, Krzysztof Kozlowski, Rob Herring,
linux-kernel, devicetree, linux-arm-kernel, Tero Kristo, srk,
r-gunasekaran, Roger Quadros, MD Danish Anwar
Hi All,
This series adds support for ICSSG ethernet on AM64x.
This series is based on the latest next-20240205 linux-next.
AM64x EVM has three ethernet ports. One is dedicated to CPSW and one is
dedicated to ICSSG1. The remaining port is muxed between CPSW and ICSSG1
ICSSG1 ports. The ICSSG1 node is added in the k3-am642-evm.dts. By default
the muxed port is used by CPSW so 2nd ICSSG1 port is disabled in the
k3-am642-evm.dts. But overlay k3-am642-evm-icssg1-dualemac.dtso can be
applied to use muxed port as ICSSG1.
This is the v4 of the series [v1].
Changes from v3 to v4:
*) Dropped ethernet3 alias from k3-am642-evm.dts as suggested by Roger.
*) Dropped extra blank lines from k3-am642-evm.dts.
*) Updated commit message of patch 3/3
*) Updated licensing header in k3-am642-evm-icssg1-dualemac.dtso.
*) Fixed up alias for ethernet1 to icssg1_emac1 in
k3-am642-evm-icssg1-dualemac.dtso as suggested by Roger.
*) Renamed 'mdio-mux-1' and 'mdio-mux-2' to 'mdio-mux@1' and 'mdio-mux@0'
respectively as suggested by Roger.
Changes from v2 to v3:
*) No functional changes.
*) Rebased on latest linux-next (next-20240122) after 6.8-rc1.
Changes from v1 to v2:
*) Fixed aliases section in k3-am642-evm.dts
*) Fixed firmware-names in k3-am642-evm.dts
*) Changed icssg1_phy1 to ethernet-phy@f from ethernet-phy@0 as suggested
by Andrew L.
*) Changed makefile to handle overlays using CONFIG_OF_ALL_DTBS as
suggested by Nishant and Andrew Davis.
*) Fixed aliases section in k3-am642-evm-icssg1-dualemac.dtso
*) Fixed pinctrl in k3-am642-evm-icssg1-dualemac.dtso
*) Updated commit message of patch 3/3 of the series to warn about adding
label name to 'mdio-mux-1' node.
[v1] https://lore.kernel.org/all/20231207081917.340167-1-danishanwar@ti.com/
[v2] https://lore.kernel.org/all/20231212165832.3933335-1-danishanwar@ti.com/
[v3] https://lore.kernel.org/all/20240122113045.1711818-1-danishanwar@ti.com/
Thanks and Regards,
MD Danish Anwar
MD Danish Anwar (2):
arm64: dts: ti: k3-am642-evm: add ICSSG1 Ethernet support
arm64: dts: ti: k3-am642-evm: add overlay for icssg1 2nd port
Suman Anna (1):
arm64: dts: ti: k3-am64-main: Add ICSSG IEP nodes
arch/arm64/boot/dts/ti/Makefile | 5 +
arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 24 +++++
.../dts/ti/k3-am642-evm-icssg1-dualemac.dtso | 79 +++++++++++++++
arch/arm64/boot/dts/ti/k3-am642-evm.dts | 99 ++++++++++++++++++-
4 files changed, 206 insertions(+), 1 deletion(-)
create mode 100644 arch/arm64/boot/dts/ti/k3-am642-evm-icssg1-dualemac.dtso
base-commit: 23e11d0318521e8693459b0e4d23aec614b3b68b
--
2.34.1
^ permalink raw reply [flat|nested] 7+ messages in thread* [PATCH v4 1/3] arm64: dts: ti: k3-am64-main: Add ICSSG IEP nodes 2024-02-05 9:05 [PATCH v4 0/3] Add AM64x ICSSG Ethernet support MD Danish Anwar @ 2024-02-05 9:05 ` MD Danish Anwar 2024-02-08 12:04 ` Roger Quadros 2024-02-05 9:05 ` [PATCH v4 2/3] arm64: dts: ti: k3-am642-evm: add ICSSG1 Ethernet support MD Danish Anwar 2024-02-05 9:05 ` [PATCH v4 3/3] arm64: dts: ti: k3-am642-evm: add overlay for icssg1 2nd port MD Danish Anwar 2 siblings, 1 reply; 7+ messages in thread From: MD Danish Anwar @ 2024-02-05 9:05 UTC (permalink / raw) To: Vignesh Raghavendra, Nishanth Menon Cc: Andrew Lunn, Conor Dooley, Krzysztof Kozlowski, Rob Herring, linux-kernel, devicetree, linux-arm-kernel, Tero Kristo, srk, r-gunasekaran, Roger Quadros, Suman Anna, Grygorii Strashko, MD Danish Anwar From: Suman Anna <s-anna@ti.com> The ICSSG IP on AM64x SoCs have two Industrial Ethernet Peripherals (IEPs) to manage/generate Industrial Ethernet functions such as time stamping. Each IEP sub-module is sourced from an internal clock mux that can be derived from either of the IP instance's ICSSG_IEP_GCLK or from another internal ICSSG CORE_CLK mux. Add both the IEP nodes for both the ICSSG instances. The IEP clock is currently configured to be derived indirectly from the ICSSG_ICLK running at 250 MHz. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: MD Danish Anwar <danishanwar@ti.com> Reviewed-by: Ravi Gunasekaran <r-gunasekaran@ti.com> --- arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi index e348114f42e0..9d2dad8ae8df 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -1244,6 +1244,18 @@ icssg0_iepclk_mux: iepclk-mux@30 { }; }; + icssg0_iep0: iep@2e000 { + compatible = "ti,am654-icss-iep"; + reg = <0x2e000 0x1000>; + clocks = <&icssg0_iepclk_mux>; + }; + + icssg0_iep1: iep@2f000 { + compatible = "ti,am654-icss-iep"; + reg = <0x2f000 0x1000>; + clocks = <&icssg0_iepclk_mux>; + }; + icssg0_mii_rt: mii-rt@32000 { compatible = "ti,pruss-mii", "syscon"; reg = <0x32000 0x100>; @@ -1385,6 +1397,18 @@ icssg1_iepclk_mux: iepclk-mux@30 { }; }; + icssg1_iep0: iep@2e000 { + compatible = "ti,am654-icss-iep"; + reg = <0x2e000 0x1000>; + clocks = <&icssg1_iepclk_mux>; + }; + + icssg1_iep1: iep@2f000 { + compatible = "ti,am654-icss-iep"; + reg = <0x2f000 0x1000>; + clocks = <&icssg1_iepclk_mux>; + }; + icssg1_mii_rt: mii-rt@32000 { compatible = "ti,pruss-mii", "syscon"; reg = <0x32000 0x100>; -- 2.34.1 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH v4 1/3] arm64: dts: ti: k3-am64-main: Add ICSSG IEP nodes 2024-02-05 9:05 ` [PATCH v4 1/3] arm64: dts: ti: k3-am64-main: Add ICSSG IEP nodes MD Danish Anwar @ 2024-02-08 12:04 ` Roger Quadros 0 siblings, 0 replies; 7+ messages in thread From: Roger Quadros @ 2024-02-08 12:04 UTC (permalink / raw) To: MD Danish Anwar, Vignesh Raghavendra, Nishanth Menon Cc: Andrew Lunn, Conor Dooley, Krzysztof Kozlowski, Rob Herring, linux-kernel, devicetree, linux-arm-kernel, Tero Kristo, srk, r-gunasekaran, Suman Anna, Grygorii Strashko On 05/02/2024 11:05, MD Danish Anwar wrote: > From: Suman Anna <s-anna@ti.com> > > The ICSSG IP on AM64x SoCs have two Industrial Ethernet Peripherals (IEPs) > to manage/generate Industrial Ethernet functions such as time stamping. > Each IEP sub-module is sourced from an internal clock mux that can be > derived from either of the IP instance's ICSSG_IEP_GCLK or from another > internal ICSSG CORE_CLK mux. Add both the IEP nodes for both the ICSSG > instances. The IEP clock is currently configured to be derived > indirectly from the ICSSG_ICLK running at 250 MHz. > > Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> > Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> > Signed-off-by: Suman Anna <s-anna@ti.com> > Signed-off-by: MD Danish Anwar <danishanwar@ti.com> > Reviewed-by: Ravi Gunasekaran <r-gunasekaran@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> ^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v4 2/3] arm64: dts: ti: k3-am642-evm: add ICSSG1 Ethernet support 2024-02-05 9:05 [PATCH v4 0/3] Add AM64x ICSSG Ethernet support MD Danish Anwar 2024-02-05 9:05 ` [PATCH v4 1/3] arm64: dts: ti: k3-am64-main: Add ICSSG IEP nodes MD Danish Anwar @ 2024-02-05 9:05 ` MD Danish Anwar 2024-02-08 12:14 ` Roger Quadros 2024-02-05 9:05 ` [PATCH v4 3/3] arm64: dts: ti: k3-am642-evm: add overlay for icssg1 2nd port MD Danish Anwar 2 siblings, 1 reply; 7+ messages in thread From: MD Danish Anwar @ 2024-02-05 9:05 UTC (permalink / raw) To: Vignesh Raghavendra, Nishanth Menon Cc: Andrew Lunn, Conor Dooley, Krzysztof Kozlowski, Rob Herring, linux-kernel, devicetree, linux-arm-kernel, Tero Kristo, srk, r-gunasekaran, Roger Quadros, MD Danish Anwar ICSSG1 provides dual Gigabit Ethernet support with proper FW loaded. The ICSSG1 MII0 (RGMII1) has DP83869 PHY attached to it. The ICSSG1 shares MII1 (RGMII2) PHY DP83869 with CPSW3g and it's assigned by default to CPSW3g. The MDIO access to MII1 (RGMII2) PHY DP83869 is controlled by MDIO bus switch and also assigned to CPSW3g. Therefore the ICSSG1 MII1 (RGMII2) port is kept disable and ICSSG1 is enabled in single MAC mode by default. Signed-off-by: MD Danish Anwar <danishanwar@ti.com> Reviewed-by: Ravi Gunasekaran <r-gunasekaran@ti.com> --- arch/arm64/boot/dts/ti/k3-am642-evm.dts | 97 +++++++++++++++++++++++++ 1 file changed, 97 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts index 8c5651d2cf5d..6b97e447c486 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -32,6 +32,7 @@ aliases { mmc1 = &sdhci1; ethernet0 = &cpsw_port1; ethernet1 = &cpsw_port2; + ethernet2 = &icssg1_emac0; }; memory@80000000 { @@ -229,6 +230,66 @@ transceiver2: can-phy1 { max-bitrate = <5000000>; standby-gpios = <&exp1 9 GPIO_ACTIVE_HIGH>; }; + + icssg1_eth: icssg1-eth { + compatible = "ti,am642-icssg-prueth"; + pinctrl-names = "default"; + pinctrl-0 = <&icssg1_rgmii1_pins_default>; + sram = <&oc_sram>; + ti,prus = <&pru1_0>, <&rtu1_0>, <&tx_pru1_0>, <&pru1_1>, <&rtu1_1>, <&tx_pru1_1>; + firmware-name = "ti-pruss/am64x-sr2-pru0-prueth-fw.elf", + "ti-pruss/am64x-sr2-rtu0-prueth-fw.elf", + "ti-pruss/am64x-sr2-txpru0-prueth-fw.elf", + "ti-pruss/am64x-sr2-pru1-prueth-fw.elf", + "ti-pruss/am64x-sr2-rtu1-prueth-fw.elf", + "ti-pruss/am64x-sr2-txpru1-prueth-fw.elf"; + + ti,pruss-gp-mux-sel = <2>, /* MII mode */ + <2>, + <2>, + <2>, /* MII mode */ + <2>, + <2>; + ti,mii-g-rt = <&icssg1_mii_g_rt>; + ti,mii-rt = <&icssg1_mii_rt>; + ti,iep = <&icssg1_iep0>, <&icssg1_iep1>; + interrupt-parent = <&icssg1_intc>; + interrupts = <24 0 2>, <25 1 3>; + interrupt-names = "tx_ts0", "tx_ts1"; + dmas = <&main_pktdma 0xc200 15>, /* egress slice 0 */ + <&main_pktdma 0xc201 15>, /* egress slice 0 */ + <&main_pktdma 0xc202 15>, /* egress slice 0 */ + <&main_pktdma 0xc203 15>, /* egress slice 0 */ + <&main_pktdma 0xc204 15>, /* egress slice 1 */ + <&main_pktdma 0xc205 15>, /* egress slice 1 */ + <&main_pktdma 0xc206 15>, /* egress slice 1 */ + <&main_pktdma 0xc207 15>, /* egress slice 1 */ + <&main_pktdma 0x4200 15>, /* ingress slice 0 */ + <&main_pktdma 0x4201 15>; /* ingress slice 1 */ + dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3", + "tx1-0", "tx1-1", "tx1-2", "tx1-3", + "rx0", "rx1"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + icssg1_emac0: port@0 { + reg = <0>; + phy-handle = <&icssg1_phy1>; + phy-mode = "rgmii-id"; + ti,syscon-rgmii-delay = <&main_conf 0x4110>; + /* Filled in by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + }; + icssg1_emac1: port@1 { + reg = <1>; + ti,syscon-rgmii-delay = <&main_conf 0x4114>; + /* Filled in by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + status = "disabled"; + }; + }; + }; }; &main_pmx0 { @@ -383,6 +444,30 @@ ddr_vtt_pins_default: ddr-vtt-default-pins { AM64X_IOPAD(0x0030, PIN_OUTPUT_PULLUP, 7) /* (L18) OSPI0_CSN1.GPIO0_12 */ >; }; + + icssg1_mdio1_pins_default: icssg1-mdio1-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x015c, PIN_OUTPUT, 0) /* (Y6) PRG1_MDIO0_MDC */ + AM64X_IOPAD(0x0158, PIN_INPUT, 0) /* (AA6) PRG1_MDIO0_MDIO */ + >; + }; + + icssg1_rgmii1_pins_default: icssg1-rgmii1-default-pins{ + pinctrl-single,pins = < + AM64X_IOPAD(0x00b8, PIN_INPUT, 2) /* (Y7) PRG1_PRU0_GPO0.PRG1_RGMII1_RD0 */ + AM64X_IOPAD(0x00bc, PIN_INPUT, 2) /* (U8) PRG1_PRU0_GPO1.PRG1_RGMII1_RD1 */ + AM64X_IOPAD(0x00c0, PIN_INPUT, 2) /* (W8) PRG1_PRU0_GPO2.PRG1_RGMII1_RD2 */ + AM64X_IOPAD(0x00c4, PIN_INPUT, 2) /* (V8) PRG1_PRU0_GPO3.PRG1_RGMII1_RD3 */ + AM64X_IOPAD(0x00d0, PIN_INPUT, 2) /* (AA7) PRG1_PRU0_GPO6.PRG1_RGMII1_RXC */ + AM64X_IOPAD(0x00c8, PIN_INPUT, 2) /* (Y8) PRG1_PRU0_GPO4.PRG1_RGMII1_RX_CTL */ + AM64X_IOPAD(0x00e4, PIN_INPUT, 2) /* (AA8) PRG1_PRU0_GPO11.PRG1_RGMII1_TD0 */ + AM64X_IOPAD(0x00e8, PIN_INPUT, 2) /* (U9) PRG1_PRU0_GPO12.PRG1_RGMII1_TD1 */ + AM64X_IOPAD(0x00ec, PIN_INPUT, 2) /* (W9) PRG1_PRU0_GPO13.PRG1_RGMII1_TD2 */ + AM64X_IOPAD(0x00f0, PIN_INPUT, 2) /* (AA9) PRG1_PRU0_GPO14.PRG1_RGMII1_TD3 */ + AM64X_IOPAD(0x00f8, PIN_INPUT, 2) /* (V9) PRG1_PRU0_GPO16.PRG1_RGMII1_TXC */ + AM64X_IOPAD(0x00f4, PIN_INPUT, 2) /* (Y9) PRG1_PRU0_GPO15.PRG1_RGMII1_TX_CTL */ + >; + }; }; &main_uart0 { @@ -731,3 +816,15 @@ &main_mcan1 { pinctrl-0 = <&main_mcan1_pins_default>; phys = <&transceiver2>; }; + +&icssg1_mdio { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&icssg1_mdio1_pins_default>; + + icssg1_phy1: ethernet-phy@f { + reg = <0xf>; + tx-internal-delay-ps = <250>; + rx-internal-delay-ps = <2000>; + }; +}; -- 2.34.1 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH v4 2/3] arm64: dts: ti: k3-am642-evm: add ICSSG1 Ethernet support 2024-02-05 9:05 ` [PATCH v4 2/3] arm64: dts: ti: k3-am642-evm: add ICSSG1 Ethernet support MD Danish Anwar @ 2024-02-08 12:14 ` Roger Quadros 0 siblings, 0 replies; 7+ messages in thread From: Roger Quadros @ 2024-02-08 12:14 UTC (permalink / raw) To: MD Danish Anwar, Vignesh Raghavendra, Nishanth Menon Cc: Andrew Lunn, Conor Dooley, Krzysztof Kozlowski, Rob Herring, linux-kernel, devicetree, linux-arm-kernel, Tero Kristo, srk, r-gunasekaran On 05/02/2024 11:05, MD Danish Anwar wrote: > ICSSG1 provides dual Gigabit Ethernet support with proper FW loaded. > > The ICSSG1 MII0 (RGMII1) has DP83869 PHY attached to it. The ICSSG1 shares > MII1 (RGMII2) PHY DP83869 with CPSW3g and it's assigned by default to > CPSW3g. The MDIO access to MII1 (RGMII2) PHY DP83869 is controlled by MDIO > bus switch and also assigned to CPSW3g. Therefore the ICSSG1 MII1 (RGMII2) > port is kept disable and ICSSG1 is enabled in single MAC mode by > default. > > Signed-off-by: MD Danish Anwar <danishanwar@ti.com> > Reviewed-by: Ravi Gunasekaran <r-gunasekaran@ti.com> > --- > arch/arm64/boot/dts/ti/k3-am642-evm.dts | 97 +++++++++++++++++++++++++ > 1 file changed, 97 insertions(+) > > diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts > index 8c5651d2cf5d..6b97e447c486 100644 > --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts > +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts > @@ -32,6 +32,7 @@ aliases { > mmc1 = &sdhci1; > ethernet0 = &cpsw_port1; > ethernet1 = &cpsw_port2; > + ethernet2 = &icssg1_emac0; > }; > > memory@80000000 { > @@ -229,6 +230,66 @@ transceiver2: can-phy1 { > max-bitrate = <5000000>; > standby-gpios = <&exp1 9 GPIO_ACTIVE_HIGH>; > }; > + > + icssg1_eth: icssg1-eth { > + compatible = "ti,am642-icssg-prueth"; > + pinctrl-names = "default"; > + pinctrl-0 = <&icssg1_rgmii1_pins_default>; > + sram = <&oc_sram>; > + ti,prus = <&pru1_0>, <&rtu1_0>, <&tx_pru1_0>, <&pru1_1>, <&rtu1_1>, <&tx_pru1_1>; > + firmware-name = "ti-pruss/am64x-sr2-pru0-prueth-fw.elf", > + "ti-pruss/am64x-sr2-rtu0-prueth-fw.elf", > + "ti-pruss/am64x-sr2-txpru0-prueth-fw.elf", > + "ti-pruss/am64x-sr2-pru1-prueth-fw.elf", > + "ti-pruss/am64x-sr2-rtu1-prueth-fw.elf", > + "ti-pruss/am64x-sr2-txpru1-prueth-fw.elf"; > + > + ti,pruss-gp-mux-sel = <2>, /* MII mode */ > + <2>, > + <2>, > + <2>, /* MII mode */ > + <2>, > + <2>; > + ti,mii-g-rt = <&icssg1_mii_g_rt>; > + ti,mii-rt = <&icssg1_mii_rt>; > + ti,iep = <&icssg1_iep0>, <&icssg1_iep1>; > + interrupt-parent = <&icssg1_intc>; > + interrupts = <24 0 2>, <25 1 3>; > + interrupt-names = "tx_ts0", "tx_ts1"; > + dmas = <&main_pktdma 0xc200 15>, /* egress slice 0 */ > + <&main_pktdma 0xc201 15>, /* egress slice 0 */ > + <&main_pktdma 0xc202 15>, /* egress slice 0 */ > + <&main_pktdma 0xc203 15>, /* egress slice 0 */ > + <&main_pktdma 0xc204 15>, /* egress slice 1 */ > + <&main_pktdma 0xc205 15>, /* egress slice 1 */ > + <&main_pktdma 0xc206 15>, /* egress slice 1 */ > + <&main_pktdma 0xc207 15>, /* egress slice 1 */ > + <&main_pktdma 0x4200 15>, /* ingress slice 0 */ > + <&main_pktdma 0x4201 15>; /* ingress slice 1 */ > + dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3", > + "tx1-0", "tx1-1", "tx1-2", "tx1-3", > + "rx0", "rx1"; > + > + ethernet-ports { > + #address-cells = <1>; > + #size-cells = <0>; > + icssg1_emac0: port@0 { > + reg = <0>; > + phy-handle = <&icssg1_phy1>; > + phy-mode = "rgmii-id"; > + ti,syscon-rgmii-delay = <&main_conf 0x4110>; "syscon" compatible will be eventually dropped from the main_conf node. It is not there on other platforms e.g. am62p One solution is to add a device tree node in main_conf and reference to that. e.g. https://lore.kernel.org/all/20240205135908.54656-3-rogerq@kernel.org/ > + /* Filled in by bootloader */ > + local-mac-address = [00 00 00 00 00 00]; > + }; > + icssg1_emac1: port@1 { > + reg = <1>; > + ti,syscon-rgmii-delay = <&main_conf 0x4114>; here too > + /* Filled in by bootloader */ > + local-mac-address = [00 00 00 00 00 00]; > + status = "disabled"; > + }; > + }; > + }; > }; > > &main_pmx0 { > @@ -383,6 +444,30 @@ ddr_vtt_pins_default: ddr-vtt-default-pins { > AM64X_IOPAD(0x0030, PIN_OUTPUT_PULLUP, 7) /* (L18) OSPI0_CSN1.GPIO0_12 */ > >; > }; > + > + icssg1_mdio1_pins_default: icssg1-mdio1-default-pins { > + pinctrl-single,pins = < > + AM64X_IOPAD(0x015c, PIN_OUTPUT, 0) /* (Y6) PRG1_MDIO0_MDC */ > + AM64X_IOPAD(0x0158, PIN_INPUT, 0) /* (AA6) PRG1_MDIO0_MDIO */ > + >; > + }; > + > + icssg1_rgmii1_pins_default: icssg1-rgmii1-default-pins{ > + pinctrl-single,pins = < > + AM64X_IOPAD(0x00b8, PIN_INPUT, 2) /* (Y7) PRG1_PRU0_GPO0.PRG1_RGMII1_RD0 */ > + AM64X_IOPAD(0x00bc, PIN_INPUT, 2) /* (U8) PRG1_PRU0_GPO1.PRG1_RGMII1_RD1 */ > + AM64X_IOPAD(0x00c0, PIN_INPUT, 2) /* (W8) PRG1_PRU0_GPO2.PRG1_RGMII1_RD2 */ > + AM64X_IOPAD(0x00c4, PIN_INPUT, 2) /* (V8) PRG1_PRU0_GPO3.PRG1_RGMII1_RD3 */ > + AM64X_IOPAD(0x00d0, PIN_INPUT, 2) /* (AA7) PRG1_PRU0_GPO6.PRG1_RGMII1_RXC */ > + AM64X_IOPAD(0x00c8, PIN_INPUT, 2) /* (Y8) PRG1_PRU0_GPO4.PRG1_RGMII1_RX_CTL */ > + AM64X_IOPAD(0x00e4, PIN_INPUT, 2) /* (AA8) PRG1_PRU0_GPO11.PRG1_RGMII1_TD0 */ > + AM64X_IOPAD(0x00e8, PIN_INPUT, 2) /* (U9) PRG1_PRU0_GPO12.PRG1_RGMII1_TD1 */ > + AM64X_IOPAD(0x00ec, PIN_INPUT, 2) /* (W9) PRG1_PRU0_GPO13.PRG1_RGMII1_TD2 */ > + AM64X_IOPAD(0x00f0, PIN_INPUT, 2) /* (AA9) PRG1_PRU0_GPO14.PRG1_RGMII1_TD3 */ > + AM64X_IOPAD(0x00f8, PIN_INPUT, 2) /* (V9) PRG1_PRU0_GPO16.PRG1_RGMII1_TXC */ > + AM64X_IOPAD(0x00f4, PIN_INPUT, 2) /* (Y9) PRG1_PRU0_GPO15.PRG1_RGMII1_TX_CTL */ > + >; > + }; > }; > > &main_uart0 { > @@ -731,3 +816,15 @@ &main_mcan1 { > pinctrl-0 = <&main_mcan1_pins_default>; > phys = <&transceiver2>; > }; > + > +&icssg1_mdio { > + status = "okay"; > + pinctrl-names = "default"; > + pinctrl-0 = <&icssg1_mdio1_pins_default>; > + > + icssg1_phy1: ethernet-phy@f { > + reg = <0xf>; > + tx-internal-delay-ps = <250>; > + rx-internal-delay-ps = <2000>; > + }; > +}; -- cheers, -roger ^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v4 3/3] arm64: dts: ti: k3-am642-evm: add overlay for icssg1 2nd port 2024-02-05 9:05 [PATCH v4 0/3] Add AM64x ICSSG Ethernet support MD Danish Anwar 2024-02-05 9:05 ` [PATCH v4 1/3] arm64: dts: ti: k3-am64-main: Add ICSSG IEP nodes MD Danish Anwar 2024-02-05 9:05 ` [PATCH v4 2/3] arm64: dts: ti: k3-am642-evm: add ICSSG1 Ethernet support MD Danish Anwar @ 2024-02-05 9:05 ` MD Danish Anwar 2024-02-08 12:17 ` Roger Quadros 2 siblings, 1 reply; 7+ messages in thread From: MD Danish Anwar @ 2024-02-05 9:05 UTC (permalink / raw) To: Vignesh Raghavendra, Nishanth Menon Cc: Andrew Lunn, Conor Dooley, Krzysztof Kozlowski, Rob Herring, linux-kernel, devicetree, linux-arm-kernel, Tero Kristo, srk, r-gunasekaran, Roger Quadros, MD Danish Anwar The am642-evm doesn't allow to enable 2 x CPSW3g ports and 2 x ICSSG1 ports all together, so base k3-am642-evm.dts enables by default 2 x CPSW3g ports and 1 x ICSSG1 ports, but it is also possible to support 1 x CPSW3g ports and 2 x ICSSG1 ports configuration. This patch adds overlay to support 1 x CPSW3g ports and 2 x ICSSG1 ports configuration: - Renames 'mdio-mux-1' node to 'mdio-mux@1' - Add label name 'mdio_mux_1' for 'mdio-mux@1' node so that the node 'mdio-mux@1' can be disabled in the overlay using the label name. - disable 2nd CPSW3g port - update CPSW3g pinmuxes to not use RGMII2 - disable mdio-mux-1 and define mdio-mux-2 to route ICSSG1 MDIO to the shared DP83869 PHY - add and enable ICSSG1 RGMII2 pinmuxes - enable ICSSG1 MII1 port Signed-off-by: MD Danish Anwar <danishanwar@ti.com> Reviewed-by: Ravi Gunasekaran <r-gunasekaran@ti.com> --- arch/arm64/boot/dts/ti/Makefile | 5 ++ .../dts/ti/k3-am642-evm-icssg1-dualemac.dtso | 79 +++++++++++++++++++ arch/arm64/boot/dts/ti/k3-am642-evm.dts | 2 +- 3 files changed, 85 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/ti/k3-am642-evm-icssg1-dualemac.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index 52c1dc910308..320b2fae5730 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -43,6 +43,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-am642-sk.dtb dtb-$(CONFIG_ARCH_K3) += k3-am642-tqma64xxl-mbax4xxl.dtb dtb-$(CONFIG_ARCH_K3) += k3-am64-tqma64xxl-mbax4xxl-sdcard.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am64-tqma64xxl-mbax4xxl-wlan.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am642-evm-icssg1-dualemac.dtbo # Boards with AM65x SoC k3-am654-gp-evm-dtbs := k3-am654-base-board.dtb k3-am654-base-board-rocktech-rk101-panel.dtbo @@ -105,6 +106,8 @@ k3-am642-tqma64xxl-mbax4xxl-sdcard-dtbs := \ k3-am642-tqma64xxl-mbax4xxl.dtb k3-am64-tqma64xxl-mbax4xxl-sdcard.dtbo k3-am642-tqma64xxl-mbax4xxl-wlan-dtbs := \ k3-am642-tqma64xxl-mbax4xxl.dtb k3-am64-tqma64xxl-mbax4xxl-wlan.dtbo +k3-am642-evm-icssg1-dualemac-dtbs := \ + k3-am642-evm.dtb k3-am642-evm-icssg1-dualemac.dtbo k3-j721e-evm-pcie0-ep-dtbs := k3-j721e-common-proc-board.dtb \ k3-j721e-evm-pcie0-ep.dtbo k3-j721s2-evm-pcie1-ep-dtbs := k3-j721s2-common-proc-board.dtb \ @@ -120,6 +123,7 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \ k3-am62a7-sk-csi2-ov5640.dtb \ k3-am642-tqma64xxl-mbax4xxl-sdcard.dtb \ k3-am642-tqma64xxl-mbax4xxl-wlan.dtb \ + k3-am642-evm-icssg1-dualemac.dtb \ k3-j721e-evm-pcie0-ep.dtb \ k3-j721s2-evm-pcie1-ep.dtb @@ -129,6 +133,7 @@ DTC_FLAGS_k3-am625-sk += -@ DTC_FLAGS_k3-am62-lp-sk += -@ DTC_FLAGS_k3-am62a7-sk += -@ DTC_FLAGS_k3-am642-tqma64xxl-mbax4xxl += -@ +DTC_FLAGS_k3-am642-evm += -@ DTC_FLAGS_k3-am6548-iot2050-advanced-m2 += -@ DTC_FLAGS_k3-j721e-common-proc-board += -@ DTC_FLAGS_k3-j721s2-common-proc-board += -@ diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm-icssg1-dualemac.dtso b/arch/arm64/boot/dts/ti/k3-am642-evm-icssg1-dualemac.dtso new file mode 100644 index 000000000000..f653a8eb820e --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am642-evm-icssg1-dualemac.dtso @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * DT overlay for enabling 2nd ICSSG1 port on AM642 EVM + * + * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include <dt-bindings/gpio/gpio.h> +#include "k3-pinctrl.h" + +&{/} { + aliases { + ethernet1 = "/icssg1-eth/ethernet-ports/port@1"; + }; + + mdio-mux@0 { + compatible = "mdio-mux-multiplexer"; + mux-controls = <&mdio_mux>; + mdio-parent-bus = <&icssg1_mdio>; + #address-cells = <1>; + #size-cells = <0>; + + mdio@0 { + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + + icssg1_phy2: ethernet-phy@3 { + reg = <3>; + tx-internal-delay-ps = <250>; + rx-internal-delay-ps = <2000>; + }; + }; + }; +}; + +&main_pmx0 { + icssg1_rgmii2_pins_default: icssg1-rgmii2-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x0108, PIN_INPUT, 2) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */ + AM64X_IOPAD(0x010c, PIN_INPUT, 2) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */ + AM64X_IOPAD(0x0110, PIN_INPUT, 2) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */ + AM64X_IOPAD(0x0114, PIN_INPUT, 2) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */ + AM64X_IOPAD(0x0120, PIN_INPUT, 2) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */ + AM64X_IOPAD(0x0118, PIN_INPUT, 2) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */ + AM64X_IOPAD(0x0134, PIN_OUTPUT, 2) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */ + AM64X_IOPAD(0x0138, PIN_OUTPUT, 2) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */ + AM64X_IOPAD(0x013c, PIN_OUTPUT, 2) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */ + AM64X_IOPAD(0x0140, PIN_OUTPUT, 2) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */ + AM64X_IOPAD(0x0148, PIN_OUTPUT, 2) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */ + AM64X_IOPAD(0x0144, PIN_OUTPUT, 2) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */ + >; + }; +}; + +&cpsw3g { + pinctrl-0 = <&rgmii1_pins_default>; +}; + +&cpsw_port2 { + status = "disabled"; +}; + +&mdio_mux_1 { + status = "disabled"; +}; + +&icssg1_eth { + pinctrl-0 = <&icssg1_rgmii1_pins_default>, <&icssg1_rgmii2_pins_default>; +}; + +&icssg1_emac1 { + status = "okay"; + phy-handle = <&icssg1_phy2>; + phy-mode = "rgmii-id"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts index 6b97e447c486..35ed5b5aab63 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -199,7 +199,7 @@ mdio_mux: mux-controller { mux-gpios = <&exp1 12 GPIO_ACTIVE_HIGH>; }; - mdio-mux-1 { + mdio_mux_1: mdio-mux@1 { compatible = "mdio-mux-multiplexer"; mux-controls = <&mdio_mux>; mdio-parent-bus = <&cpsw3g_mdio>; -- 2.34.1 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH v4 3/3] arm64: dts: ti: k3-am642-evm: add overlay for icssg1 2nd port 2024-02-05 9:05 ` [PATCH v4 3/3] arm64: dts: ti: k3-am642-evm: add overlay for icssg1 2nd port MD Danish Anwar @ 2024-02-08 12:17 ` Roger Quadros 0 siblings, 0 replies; 7+ messages in thread From: Roger Quadros @ 2024-02-08 12:17 UTC (permalink / raw) To: MD Danish Anwar, Vignesh Raghavendra, Nishanth Menon Cc: Andrew Lunn, Conor Dooley, Krzysztof Kozlowski, Rob Herring, linux-kernel, devicetree, linux-arm-kernel, Tero Kristo, srk, r-gunasekaran On 05/02/2024 11:05, MD Danish Anwar wrote: > The am642-evm doesn't allow to enable 2 x CPSW3g ports and 2 x ICSSG1 ports > all together, so base k3-am642-evm.dts enables by default 2 x CPSW3g ports > and 1 x ICSSG1 ports, but it is also possible to support 1 x CPSW3g ports > and 2 x ICSSG1 ports configuration. > > This patch adds overlay to support 1 x CPSW3g ports and 2 x ICSSG1 ports > configuration: > - Renames 'mdio-mux-1' node to 'mdio-mux@1' > - Add label name 'mdio_mux_1' for 'mdio-mux@1' node so that the node > 'mdio-mux@1' can be disabled in the overlay using the label name. > - disable 2nd CPSW3g port > - update CPSW3g pinmuxes to not use RGMII2 > - disable mdio-mux-1 and define mdio-mux-2 to route ICSSG1 MDIO to the > shared DP83869 PHY > - add and enable ICSSG1 RGMII2 pinmuxes > - enable ICSSG1 MII1 port /icssg1/ICSSG1 in subject > > Signed-off-by: MD Danish Anwar <danishanwar@ti.com> > Reviewed-by: Ravi Gunasekaran <r-gunasekaran@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> ^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2024-02-08 12:18 UTC | newest] Thread overview: 7+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2024-02-05 9:05 [PATCH v4 0/3] Add AM64x ICSSG Ethernet support MD Danish Anwar 2024-02-05 9:05 ` [PATCH v4 1/3] arm64: dts: ti: k3-am64-main: Add ICSSG IEP nodes MD Danish Anwar 2024-02-08 12:04 ` Roger Quadros 2024-02-05 9:05 ` [PATCH v4 2/3] arm64: dts: ti: k3-am642-evm: add ICSSG1 Ethernet support MD Danish Anwar 2024-02-08 12:14 ` Roger Quadros 2024-02-05 9:05 ` [PATCH v4 3/3] arm64: dts: ti: k3-am642-evm: add overlay for icssg1 2nd port MD Danish Anwar 2024-02-08 12:17 ` Roger Quadros
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