* [PATCH v3 1/4] clk: at91: sckc: Fix parent_data struct for slow osc
2025-05-06 20:04 [PATCH v3 0/4] AT91 SAMA7 SoC Clock Adjustments Ryan.Wanner
@ 2025-05-06 20:04 ` Ryan.Wanner
2025-05-06 20:04 ` [PATCH v3 2/4] clk: at91: sama7d65: Add missing clk_hw to parent_data Ryan.Wanner
` (2 subsequent siblings)
3 siblings, 0 replies; 7+ messages in thread
From: Ryan.Wanner @ 2025-05-06 20:04 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, nicolas.ferre, alexandre.belloni,
claudiu.beznea, mturquette, sboyd
Cc: devicetree, linux-arm-kernel, linux-kernel, linux-clk,
Ryan Wanner
From: Ryan Wanner <Ryan.Wanner@microchip.com>
The slow xtal is not described correctly as a parent, the driver looks for a
"slow_xtal" string which is incorrect and will not work with the new
formating of xtals.
To avoid this and keep this driver backwards compatible the
parent_data.fw_name is replaced with parent_data.name and the original
parent_data.name is replaced with parent_data.index. Using the index is
safe due to the driver requiring only 1 xtal.
Fixes: 8aa1db9ccee0e ("clk: at91: sckc: switch to parent_data/parent_hw")
Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
---
drivers/clk/at91/sckc.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/at91/sckc.c b/drivers/clk/at91/sckc.c
index 021d1b412af4..952a805b6f7e 100644
--- a/drivers/clk/at91/sckc.c
+++ b/drivers/clk/at91/sckc.c
@@ -374,7 +374,7 @@ static void __init at91sam9x5_sckc_register(struct device_node *np,
const char *xtal_name;
struct clk_hw *slow_rc, *slow_osc, *slowck;
static struct clk_parent_data parent_data = {
- .name = "slow_xtal",
+ .index = 0,
};
const struct clk_hw *parent_hws[2];
bool bypass;
@@ -407,7 +407,7 @@ static void __init at91sam9x5_sckc_register(struct device_node *np,
if (!xtal_name)
goto unregister_slow_rc;
- parent_data.fw_name = xtal_name;
+ parent_data.name = xtal_name;
slow_osc = at91_clk_register_slow_osc(regbase, "slow_osc",
&parent_data, 1200000, bypass, bits);
@@ -476,7 +476,7 @@ static void __init of_sam9x60_sckc_setup(struct device_node *np)
const char *xtal_name;
const struct clk_hw *parent_hws[2];
static struct clk_parent_data parent_data = {
- .name = "slow_xtal",
+ .index = 0,
};
bool bypass;
int ret;
@@ -494,7 +494,7 @@ static void __init of_sam9x60_sckc_setup(struct device_node *np)
if (!xtal_name)
goto unregister_slow_rc;
- parent_data.fw_name = xtal_name;
+ parent_data.name = xtal_name;
bypass = of_property_read_bool(np, "atmel,osc-bypass");
slow_osc = at91_clk_register_slow_osc(regbase, "slow_osc",
&parent_data, 5000000, bypass,
@@ -592,7 +592,7 @@ static void __init of_sama5d4_sckc_setup(struct device_node *np)
const char *xtal_name;
const struct clk_hw *parent_hws[2];
static struct clk_parent_data parent_data = {
- .name = "slow_xtal",
+ .index = 0,
};
int ret;
@@ -609,7 +609,7 @@ static void __init of_sama5d4_sckc_setup(struct device_node *np)
xtal_name = of_clk_get_parent_name(np, 0);
if (!xtal_name)
goto unregister_slow_rc;
- parent_data.fw_name = xtal_name;
+ parent_data.name = xtal_name;
osc = kzalloc(sizeof(*osc), GFP_KERNEL);
if (!osc)
--
2.43.0
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH v3 2/4] clk: at91: sama7d65: Add missing clk_hw to parent_data
2025-05-06 20:04 [PATCH v3 0/4] AT91 SAMA7 SoC Clock Adjustments Ryan.Wanner
2025-05-06 20:04 ` [PATCH v3 1/4] clk: at91: sckc: Fix parent_data struct for slow osc Ryan.Wanner
@ 2025-05-06 20:04 ` Ryan.Wanner
2025-05-12 14:47 ` Claudiu Beznea
2025-05-06 20:04 ` [PATCH v3 3/4] clk: at91: sama7g5: " Ryan.Wanner
2025-05-06 20:04 ` [PATCH v3 4/4] ARM: dts: microchip: sama7g5: Adjust clock xtal phandle Ryan.Wanner
3 siblings, 1 reply; 7+ messages in thread
From: Ryan.Wanner @ 2025-05-06 20:04 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, nicolas.ferre, alexandre.belloni,
claudiu.beznea, mturquette, sboyd
Cc: devicetree, linux-arm-kernel, linux-kernel, linux-clk,
Ryan Wanner
From: Ryan Wanner <Ryan.Wanner@microchip.com>
The main_xtal clk_hw struct is not passed into parent_data.hw causing
the main_osc to not have a parent causing a corrupted clock tree.
Passing the main_xtal struct into the parent_data struct will
ensure the correct parent structure for main_osc and a correct clock
tree.
Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
---
drivers/clk/at91/sama7d65.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/at91/sama7d65.c b/drivers/clk/at91/sama7d65.c
index a5d40df8b2f2..1e9d3c393883 100644
--- a/drivers/clk/at91/sama7d65.c
+++ b/drivers/clk/at91/sama7d65.c
@@ -1100,7 +1100,7 @@ static void __init sama7d65_pmc_setup(struct device_node *np)
struct regmap *regmap;
struct clk_hw *hw, *main_rc_hw, *main_osc_hw, *main_xtal_hw;
struct clk_hw *td_slck_hw, *md_slck_hw;
- static struct clk_parent_data parent_data;
+ static struct clk_parent_data parent_data = {0};
struct clk_hw *parent_hws[10];
bool bypass;
int i, j;
@@ -1138,6 +1138,7 @@ static void __init sama7d65_pmc_setup(struct device_node *np)
parent_data.name = main_xtal_name;
parent_data.fw_name = main_xtal_name;
+ parent_data.hw = main_xtal_hw;
main_osc_hw = at91_clk_register_main_osc(regmap, "main_osc", NULL,
&parent_data, bypass);
if (IS_ERR(main_osc_hw))
--
2.43.0
^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [PATCH v3 2/4] clk: at91: sama7d65: Add missing clk_hw to parent_data
2025-05-06 20:04 ` [PATCH v3 2/4] clk: at91: sama7d65: Add missing clk_hw to parent_data Ryan.Wanner
@ 2025-05-12 14:47 ` Claudiu Beznea
2025-05-12 19:38 ` Ryan.Wanner
0 siblings, 1 reply; 7+ messages in thread
From: Claudiu Beznea @ 2025-05-12 14:47 UTC (permalink / raw)
To: Ryan.Wanner, robh, krzk+dt, conor+dt, nicolas.ferre,
alexandre.belloni, mturquette, sboyd
Cc: devicetree, linux-arm-kernel, linux-kernel, linux-clk
Hi, Ryan,
On 06.05.2025 23:04, Ryan.Wanner@microchip.com wrote:
> From: Ryan Wanner <Ryan.Wanner@microchip.com>
>
> The main_xtal clk_hw struct is not passed into parent_data.hw causing
> the main_osc to not have a parent causing a corrupted clock tree.
> Passing the main_xtal struct into the parent_data struct will
> ensure the correct parent structure for main_osc and a correct clock
> tree.
>
> Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
> ---
> drivers/clk/at91/sama7d65.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/at91/sama7d65.c b/drivers/clk/at91/sama7d65.c
> index a5d40df8b2f2..1e9d3c393883 100644
> --- a/drivers/clk/at91/sama7d65.c
> +++ b/drivers/clk/at91/sama7d65.c
> @@ -1100,7 +1100,7 @@ static void __init sama7d65_pmc_setup(struct device_node *np)
> struct regmap *regmap;
> struct clk_hw *hw, *main_rc_hw, *main_osc_hw, *main_xtal_hw;
> struct clk_hw *td_slck_hw, *md_slck_hw;
> - static struct clk_parent_data parent_data;
> + static struct clk_parent_data parent_data = {0};
> struct clk_hw *parent_hws[10];
> bool bypass;
> int i, j;
> @@ -1138,6 +1138,7 @@ static void __init sama7d65_pmc_setup(struct device_node *np)
>
> parent_data.name = main_xtal_name;
> parent_data.fw_name = main_xtal_name;
> + parent_data.hw = main_xtal_hw;
Is this line still needed with the initialization of parent data above:
static struct clk_parent_data parent_data = {0};
> main_osc_hw = at91_clk_register_main_osc(regmap, "main_osc", NULL,
> &parent_data, bypass);
> if (IS_ERR(main_osc_hw))
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [PATCH v3 2/4] clk: at91: sama7d65: Add missing clk_hw to parent_data
2025-05-12 14:47 ` Claudiu Beznea
@ 2025-05-12 19:38 ` Ryan.Wanner
0 siblings, 0 replies; 7+ messages in thread
From: Ryan.Wanner @ 2025-05-12 19:38 UTC (permalink / raw)
To: claudiu.beznea, robh, krzk+dt, conor+dt, Nicolas.Ferre,
alexandre.belloni, mturquette, sboyd
Cc: devicetree, linux-arm-kernel, linux-kernel, linux-clk
Hi Claudiu,
On 5/12/25 07:47, Claudiu Beznea wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> Hi, Ryan,
>
> On 06.05.2025 23:04, Ryan.Wanner@microchip.com wrote:
>> From: Ryan Wanner <Ryan.Wanner@microchip.com>
>>
>> The main_xtal clk_hw struct is not passed into parent_data.hw causing
>> the main_osc to not have a parent causing a corrupted clock tree.
>> Passing the main_xtal struct into the parent_data struct will
>> ensure the correct parent structure for main_osc and a correct clock
>> tree.
>>
>> Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
>> ---
>> drivers/clk/at91/sama7d65.c | 3 ++-
>> 1 file changed, 2 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/clk/at91/sama7d65.c b/drivers/clk/at91/sama7d65.c
>> index a5d40df8b2f2..1e9d3c393883 100644
>> --- a/drivers/clk/at91/sama7d65.c
>> +++ b/drivers/clk/at91/sama7d65.c
>> @@ -1100,7 +1100,7 @@ static void __init sama7d65_pmc_setup(struct device_node *np)
>> struct regmap *regmap;
>> struct clk_hw *hw, *main_rc_hw, *main_osc_hw, *main_xtal_hw;
>> struct clk_hw *td_slck_hw, *md_slck_hw;
>> - static struct clk_parent_data parent_data;
>> + static struct clk_parent_data parent_data = {0};
>> struct clk_hw *parent_hws[10];
>> bool bypass;
>> int i, j;
>> @@ -1138,6 +1138,7 @@ static void __init sama7d65_pmc_setup(struct device_node *np)
>>
>> parent_data.name = main_xtal_name;
>> parent_data.fw_name = main_xtal_name;
>> + parent_data.hw = main_xtal_hw;
>
> Is this line still needed with the initialization of parent data above:
Yes it is still needed because the clk_hw struct still needs to be
passed into the parent_data struct. If not the wrong parent will be set.
>
> static struct clk_parent_data parent_data = {0};
>
>> main_osc_hw = at91_clk_register_main_osc(regmap, "main_osc", NULL,
>> &parent_data, bypass);
>> if (IS_ERR(main_osc_hw))
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v3 3/4] clk: at91: sama7g5: Add missing clk_hw to parent_data
2025-05-06 20:04 [PATCH v3 0/4] AT91 SAMA7 SoC Clock Adjustments Ryan.Wanner
2025-05-06 20:04 ` [PATCH v3 1/4] clk: at91: sckc: Fix parent_data struct for slow osc Ryan.Wanner
2025-05-06 20:04 ` [PATCH v3 2/4] clk: at91: sama7d65: Add missing clk_hw to parent_data Ryan.Wanner
@ 2025-05-06 20:04 ` Ryan.Wanner
2025-05-06 20:04 ` [PATCH v3 4/4] ARM: dts: microchip: sama7g5: Adjust clock xtal phandle Ryan.Wanner
3 siblings, 0 replies; 7+ messages in thread
From: Ryan.Wanner @ 2025-05-06 20:04 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, nicolas.ferre, alexandre.belloni,
claudiu.beznea, mturquette, sboyd
Cc: devicetree, linux-arm-kernel, linux-kernel, linux-clk,
Ryan Wanner
From: Ryan Wanner <Ryan.Wanner@microchip.com>
The main_xtal clk_hw struct is not passed into parent_data.hw causing
the main_osc to not have a parent and corrupting the clock tree.
Passing the main_xtal struct into the parent_data struct will ensure
the correct parent structure.
Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
---
drivers/clk/at91/sama7g5.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c
index 8385badc1c70..b4eefca0b6d5 100644
--- a/drivers/clk/at91/sama7g5.c
+++ b/drivers/clk/at91/sama7g5.c
@@ -979,7 +979,7 @@ static void __init sama7g5_pmc_setup(struct device_node *np)
struct regmap *regmap;
struct clk_hw *hw, *main_rc_hw, *main_osc_hw, *main_xtal_hw;
struct clk_hw *td_slck_hw, *md_slck_hw;
- static struct clk_parent_data parent_data;
+ static struct clk_parent_data parent_data = {0};
struct clk_hw *parent_hws[10];
bool bypass;
int i, j;
@@ -1017,6 +1017,7 @@ static void __init sama7g5_pmc_setup(struct device_node *np)
parent_data.name = main_xtal_name;
parent_data.fw_name = main_xtal_name;
+ parent_data.hw = main_xtal_hw;
main_osc_hw = at91_clk_register_main_osc(regmap, "main_osc", NULL,
&parent_data, bypass);
if (IS_ERR(main_osc_hw))
--
2.43.0
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH v3 4/4] ARM: dts: microchip: sama7g5: Adjust clock xtal phandle
2025-05-06 20:04 [PATCH v3 0/4] AT91 SAMA7 SoC Clock Adjustments Ryan.Wanner
` (2 preceding siblings ...)
2025-05-06 20:04 ` [PATCH v3 3/4] clk: at91: sama7g5: " Ryan.Wanner
@ 2025-05-06 20:04 ` Ryan.Wanner
3 siblings, 0 replies; 7+ messages in thread
From: Ryan.Wanner @ 2025-05-06 20:04 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, nicolas.ferre, alexandre.belloni,
claudiu.beznea, mturquette, sboyd
Cc: devicetree, linux-arm-kernel, linux-kernel, linux-clk,
Ryan Wanner
From: Ryan Wanner <Ryan.Wanner@microchip.com>
Adjust clock xtal phandles to match the new xtal phandle formatting.
Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
---
arch/arm/boot/dts/microchip/at91-sama7g5ek.dts | 18 ++++++++----------
arch/arm/boot/dts/microchip/sama7g5.dtsi | 4 ++--
2 files changed, 10 insertions(+), 12 deletions(-)
diff --git a/arch/arm/boot/dts/microchip/at91-sama7g5ek.dts b/arch/arm/boot/dts/microchip/at91-sama7g5ek.dts
index 2543599013b1..79bf58f8c02e 100644
--- a/arch/arm/boot/dts/microchip/at91-sama7g5ek.dts
+++ b/arch/arm/boot/dts/microchip/at91-sama7g5ek.dts
@@ -35,16 +35,6 @@ aliases {
i2c2 = &i2c9;
};
- clocks {
- slow_xtal {
- clock-frequency = <32768>;
- };
-
- main_xtal {
- clock-frequency = <24000000>;
- };
- };
-
gpio-keys {
compatible = "gpio-keys";
@@ -512,6 +502,10 @@ spi11: spi@400 {
};
};
+&main_xtal {
+ clock-frequency = <24000000>;
+};
+
&gmac0 {
#address-cells = <1>;
#size-cells = <0>;
@@ -917,3 +911,7 @@ &vddout25 {
vin-supply = <&vdd_3v3>;
status = "okay";
};
+
+&slow_xtal {
+ clock-frequency = <32768>;
+};
diff --git a/arch/arm/boot/dts/microchip/sama7g5.dtsi b/arch/arm/boot/dts/microchip/sama7g5.dtsi
index 17bcdcf0cf4a..250c9e98a8bb 100644
--- a/arch/arm/boot/dts/microchip/sama7g5.dtsi
+++ b/arch/arm/boot/dts/microchip/sama7g5.dtsi
@@ -117,12 +117,12 @@ map1 {
};
clocks {
- slow_xtal: slow_xtal {
+ slow_xtal: clock-slowxtal {
compatible = "fixed-clock";
#clock-cells = <0>;
};
- main_xtal: main_xtal {
+ main_xtal: clock-mainxtal {
compatible = "fixed-clock";
#clock-cells = <0>;
};
--
2.43.0
^ permalink raw reply related [flat|nested] 7+ messages in thread