From: Chen Yu <yu.c.chen@intel.com>
To: tony.luck@intel.com, reinette.chatre@intel.com
Cc: x86@kernel.org, linux-kernel@vger.kernel.org, bp@alien8.de,
tglx@kernel.org, mingo@redhat.com, dave.hansen@linux.intel.com,
hpa@zytor.com, dave.martin@arm.com, james.morse@arm.com,
fenghuay@nvidia.com, babu.moger@amd.com,
anil.keshavamurthy@broadcom.com
Subject: [PATCH v2 0/6] Introduce MMIO-based CMT access for Enhanced RDT
Date: Fri, 5 Jun 2026 00:07:53 +0800 [thread overview]
Message-ID: <cover.1780587063.git.yu.c.chen@intel.com> (raw)
Intel Enhanced Resource Director Technology (ERDT) extends the existing
RDT framework with two major capabilities:
1. MMIO-based access to monitoring and allocation registers, replacing
the legacy MSR-based interface.
2. Region-aware RDT for fine-grained control over different tiers of
memory (e.g., CXL.mem, DDR).
This is described in the Intel RDT Architecture Specification:
https://cdrdv2-public.intel.com/789566/356688-intel-rdt-arch-spec.pdf
This patch set focuses on the first part: enabling MMIO-based access for
Cache Monitoring Technology (CMT), while CAT/MBM/MBA are still using MSR.
The platform advertises the MMIO register layout through the ACPI ERDT
(Enhanced Resource Director Technology) table, which contains sub-tables
describing per-domain register regions for monitoring and allocation.
With ERDT, L3 cache occupancy counters are read via MMIO rather than
MSR, allowing the reads to be performed from any CPU without requiring
cross-CPU IPIs. This series parses the relevant ACPI sub-tables (RMDD,
CMRC), prepares the resctrl monitor infrastructure for MMIO-based reads,
and adds initial support for reading L3 occupancy via the CMRC interface.
kselftest of CMT and L3_CAT has passed with minor adjustment at
https://lore.kernel.org/lkml/20260523101715.3964456-1-yu.c.chen@intel.com/.
Changes since V1:
- Add #include <linux/cleanup.h> to follow the "include-what-you-use" best
practice (Tony Luck)
- Fix 3 issues reported by:
https://sashiko.dev/#/patchset/cover.1779872016.git.yu.c.chen%40intel.com
Remove the variable of cacd in struct erdt_domain_info as it will
never be used after initialization.
Invoke erdt_exit() to avoid resource leak if rdt_alloc_capable and
rdt_mon_capable are both false.
Adjust the comments suggested by sashiko.
Anil S Keshavamurthy (1):
x86/resctrl: Parse ACPI ERDT table and map RMDD domains by L3 cache ID
Chen Yu (4):
x86/resctrl: Parse ACPI CMRC table
x86/resctrl: Rename prev_msr to prev_mon_val
x86/resctrl: Refactor the monitor read function
x86/resctrl: Add support for L3 occupancy monitoring via RMID MMIO
read
Tony Luck (1):
fs/resctrl: Do not invoke smp_processor_id() in preemptible context
arch/x86/Kconfig | 4 +-
arch/x86/include/asm/resctrl.h | 4 +
arch/x86/kernel/cpu/resctrl/Makefile | 1 +
arch/x86/kernel/cpu/resctrl/core.c | 23 +-
arch/x86/kernel/cpu/resctrl/erdt.c | 451 +++++++++++++++++++++++++
arch/x86/kernel/cpu/resctrl/internal.h | 11 +-
arch/x86/kernel/cpu/resctrl/monitor.c | 64 ++--
fs/resctrl/monitor.c | 38 ++-
8 files changed, 551 insertions(+), 45 deletions(-)
create mode 100644 arch/x86/kernel/cpu/resctrl/erdt.c
--
2.25.1
next reply other threads:[~2026-06-04 16:17 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-04 16:07 Chen Yu [this message]
2026-06-04 16:08 ` [PATCH v2 1/6] x86/resctrl: Parse ACPI ERDT table and map RMDD domains by L3 cache ID Chen Yu
2026-06-04 16:56 ` Thomas Gleixner
2026-06-04 16:11 ` [PATCH v2 2/6] x86/resctrl: Parse ACPI CMRC table Chen Yu
2026-06-04 16:57 ` Thomas Gleixner
2026-06-04 16:11 ` [PATCH v2 3/6] x86/resctrl: Rename prev_msr to prev_mon_val Chen Yu
2026-06-04 16:11 ` [PATCH v2 4/6] x86/resctrl: Refactor the monitor read function Chen Yu
2026-06-04 16:11 ` [PATCH v2 5/6] fs/resctrl: Do not invoke smp_processor_id() in preemptible context Chen Yu
2026-06-04 16:11 ` [PATCH v2 6/6] x86/resctrl: Add support for L3 occupancy monitoring via RMID MMIO read Chen Yu
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