From: "Naveen N Rao (AMD)" <naveen@kernel.org>
To: Borislav Petkov <bp@alien8.de>,
Dave Hansen <dave.hansen@linux.intel.com>
Cc: <linux-kernel@vger.kernel.org>, <x86@kernel.org>,
Nikunj A Dadhania <nikunj@amd.com>,
Manali Shukla <manali.shukla@amd.com>,
Bharata B Rao <bharata@amd.com>, "H. Peter Anvin" <hpa@zytor.com>,
Thomas Gleixner <tglx@linutronix.de>
Subject: [PATCH v3 0/3] Support additional AMD EILVT registers
Date: Tue, 21 Jul 2026 13:33:34 +0530 [thread overview]
Message-ID: <cover.1784619898.git.naveen@kernel.org> (raw)
Add support for additional APIC EILVT registers being introduced in
future AMD processors:
https://docs.amd.com/v/u/en-US/69205_1.00_AMD64_IBS_PUB)
This is mostly a re-send of v2, except for a small change in patch 2/3
where I have dropped the KVM export for apic_eilvt_count - it can be
introduced in the series adding the KVM user for the same.
v2:
http://lore.kernel.org/r/cover.1778594390.git.naveen@kernel.org
- Naveen
Naveen N Rao (AMD) (3):
perf/amd/ibs: Limit the max EILVT register count for AMD family 0x10
x86/apic: Introduce a variable to track the number of EILVT registers
x86/apic: Drop APIC_EILVT_NR_MAX and switch to using apic_eilvt_count
arch/x86/include/asm/apic.h | 2 ++
arch/x86/include/asm/apicdef.h | 2 +-
arch/x86/events/amd/ibs.c | 4 ++--
arch/x86/kernel/apic/apic.c | 18 ++++++++++++++++--
4 files changed, 21 insertions(+), 5 deletions(-)
base-commit: e9dac177a4ea335a3f035f81405088e17947f258
--
2.54.0
next reply other threads:[~2026-07-21 8:08 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-21 8:03 Naveen N Rao (AMD) [this message]
2026-07-21 8:03 ` [PATCH v3 1/3] perf/amd/ibs: Limit the max EILVT register count for AMD family 0x10 Naveen N Rao (AMD)
2026-07-21 8:03 ` [PATCH v3 2/3] x86/apic: Introduce a variable to track the number of EILVT registers Naveen N Rao (AMD)
2026-07-21 12:42 ` Thomas Gleixner
2026-07-21 8:03 ` [PATCH v3 3/3] x86/apic: Drop APIC_EILVT_NR_MAX and switch to using apic_eilvt_count Naveen N Rao (AMD)
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