[PATCH v3 0/3] Support additional AMD EILVT registers

[PATCH v3 0/3] Support additional AMD EILVT registers

[Naveen N Rao (AMD)]

Add support for additional APIC EILVT registers being introduced in 
future AMD processors:
https://docs.amd.com/v/u/en-US/69205_1.00_AMD64_IBS_PUB)

This is mostly a re-send of v2, except for a small change in patch 2/3 
where I have dropped the KVM export for apic_eilvt_count - it can be 
introduced in the series adding the KVM user for the same.

v2:
http://lore.kernel.org/r/cover.1778594390.git.naveen@kernel.org



- Naveen


Naveen N Rao (AMD) (3):
  perf/amd/ibs: Limit the max EILVT register count for AMD family 0x10
  x86/apic: Introduce a variable to track the number of EILVT registers
  x86/apic: Drop APIC_EILVT_NR_MAX and switch to using apic_eilvt_count

 arch/x86/include/asm/apic.h    |  2 ++
 arch/x86/include/asm/apicdef.h |  2 +-
 arch/x86/events/amd/ibs.c      |  4 ++--
 arch/x86/kernel/apic/apic.c    | 18 ++++++++++++++++--
 4 files changed, 21 insertions(+), 5 deletions(-)


base-commit: e9dac177a4ea335a3f035f81405088e17947f258
-- 
2.54.0

[PATCH v3 1/3] perf/amd/ibs: Limit the max EILVT register count for AMD family 0x10

[Naveen N Rao (AMD)]

For AMD family 0x10, EILVT offsets are not assigned by BIOS and is
instead assigned by picking the next available EILVT offset.  Use the
maximum EILVT count for family 0x10 (APIC_EILVT_NR_AMD_10H) rather than
an arbitrary maximum EILVT count when looking for the next available
EILVT offset.

Signed-off-by: Naveen N Rao (AMD) <naveen@kernel.org>
Tested-by: Manali Shukla <manali.shukla@amd.com>
---
 arch/x86/events/amd/ibs.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c
index 3531f9c23b8c..555912ac520f 100644
--- a/arch/x86/events/amd/ibs.c
+++ b/arch/x86/events/amd/ibs.c
@@ -1839,13 +1839,13 @@ static void force_ibs_eilvt_setup(void)
 
 	preempt_disable();
 	/* find the next free available EILVT entry, skip offset 0 */
-	for (offset = 1; offset < APIC_EILVT_NR_MAX; offset++) {
+	for (offset = 1; offset < APIC_EILVT_NR_AMD_10H; offset++) {
 		if (get_eilvt(offset))
 			break;
 	}
 	preempt_enable();
 
-	if (offset == APIC_EILVT_NR_MAX) {
+	if (offset == APIC_EILVT_NR_AMD_10H) {
 		pr_debug("No EILVT entry available\n");
 		return;
 	}
-- 
2.54.0

[PATCH v3 2/3] x86/apic: Introduce a variable to track the number of EILVT registers

[Naveen N Rao (AMD)]

Future AMD processors will be increasing the number of EILVT registers.
Rather than hardcoding the maximum EILVT register count and using that
everywhere, introduce a variable to track the EILVT register count.

The number of EILVT registers (the actual count) is exposed through the
extended APIC Feature Register (APIC_EFEAT) bits 23:16. Use this to
initialize the count and fall back to the current default
(APIC_EILVT_NR_AMD_10H) if the count is not available.

Signed-off-by: Naveen N Rao (AMD) <naveen@kernel.org>
Tested-by: Manali Shukla <manali.shukla@amd.com>
---
 arch/x86/include/asm/apic.h    |  2 ++
 arch/x86/include/asm/apicdef.h |  1 +
 arch/x86/kernel/apic/apic.c    | 11 +++++++++++
 3 files changed, 14 insertions(+)

diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h
index 9cd493d467d4..8b03c7a14706 100644
--- a/arch/x86/include/asm/apic.h
+++ b/arch/x86/include/asm/apic.h
@@ -74,6 +74,8 @@ enum apic_intr_mode_id {
 	APIC_SYMMETRIC_IO_NO_ROUTING
 };
 
+extern unsigned int apic_eilvt_count;
+
 /*
  * With 82489DX we can't rely on apic feature bit
  * retrieved via cpuid but still have to deal with
diff --git a/arch/x86/include/asm/apicdef.h b/arch/x86/include/asm/apicdef.h
index bc125c4429dc..ba7657e75ad1 100644
--- a/arch/x86/include/asm/apicdef.h
+++ b/arch/x86/include/asm/apicdef.h
@@ -134,6 +134,7 @@
 #define		APIC_TDR_DIV_64		0x9
 #define		APIC_TDR_DIV_128	0xA
 #define	APIC_EFEAT	0x400
+#define		APIC_EFEAT_XLC(x)	(((x) >> 16) & 0xff)
 #define	APIC_ECTRL	0x410
 #define APIC_SEOI	0x420
 #define APIC_IER	0x480
diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
index 90025451ace2..83895ce954ef 100644
--- a/arch/x86/kernel/apic/apic.c
+++ b/arch/x86/kernel/apic/apic.c
@@ -342,6 +342,7 @@ static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
  */
 
 static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX];
+unsigned int apic_eilvt_count __ro_after_init;
 
 static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new)
 {
@@ -410,6 +411,15 @@ int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask)
 }
 EXPORT_SYMBOL_GPL(setup_APIC_eilvt);
 
+static __init void init_eilvt(void)
+{
+	if (cpu_feature_enabled(X86_FEATURE_EXTAPIC))
+		apic_eilvt_count = APIC_EFEAT_XLC(apic_read(APIC_EFEAT));
+
+	if (!apic_eilvt_count && boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
+		apic_eilvt_count = APIC_EILVT_NR_AMD_10H;
+}
+
 /*
  * Program the next event, relative to now
  */
@@ -2345,6 +2355,7 @@ static void __init apic_bsp_setup(bool upmode)
 	if (upmode)
 		apic_bsp_up_setup();
 	setup_local_APIC();
+	init_eilvt();
 
 	enable_IO_APIC();
 	end_local_APIC_setup();
-- 
2.54.0

Re: [PATCH v3 2/3] x86/apic: Introduce a variable to track the number of EILVT registers

[Thomas Gleixner]

On Tue, Jul 21 2026 at 13:33, Naveen N. Rao wrote:
>  
> +extern unsigned int apic_eilvt_count;

Please do not create yet another global variable. It's an APIC property,
so struct apic is the obvious place for it, no?

Thanks,

        tglx

[PATCH v3 3/3] x86/apic: Drop APIC_EILVT_NR_MAX and switch to using apic_eilvt_count

[Naveen N Rao (AMD)]

Switch to using apic_eilvt_count as the maximum EILVT register count.
Since this value is no longer a compile-time constant, update
eilvt_offsets to be dynamically allocated.

Signed-off-by: Naveen N Rao (AMD) <naveen@kernel.org>
Tested-by: Manali Shukla <manali.shukla@amd.com>
---
 arch/x86/include/asm/apicdef.h | 1 -
 arch/x86/kernel/apic/apic.c    | 7 +++++--
 2 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/arch/x86/include/asm/apicdef.h b/arch/x86/include/asm/apicdef.h
index ba7657e75ad1..32a242ae0455 100644
--- a/arch/x86/include/asm/apicdef.h
+++ b/arch/x86/include/asm/apicdef.h
@@ -140,7 +140,6 @@
 #define APIC_IER	0x480
 #define APIC_EILVTn(n)	(0x500 + 0x10 * n)
 #define		APIC_EILVT_NR_AMD_10H	4
-#define		APIC_EILVT_NR_MAX	APIC_EILVT_NR_AMD_10H
 
 #define APIC_BASE (fix_to_virt(FIX_APIC_BASE))
 #define APIC_BASE_MSR		0x800
diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
index 83895ce954ef..2e98ab259ae0 100644
--- a/arch/x86/kernel/apic/apic.c
+++ b/arch/x86/kernel/apic/apic.c
@@ -341,7 +341,7 @@ static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
  * necessarily a BIOS bug.
  */
 
-static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX];
+static atomic_t *eilvt_offsets;
 unsigned int apic_eilvt_count __ro_after_init;
 
 static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new)
@@ -355,7 +355,7 @@ static unsigned int reserve_eilvt_offset(int offset, unsigned int new)
 {
 	unsigned int rsvd, vector;
 
-	if (offset >= APIC_EILVT_NR_MAX)
+	if (!eilvt_offsets || offset >= apic_eilvt_count)
 		return ~0;
 
 	rsvd = atomic_read(&eilvt_offsets[offset]);
@@ -418,6 +418,9 @@ static __init void init_eilvt(void)
 
 	if (!apic_eilvt_count && boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
 		apic_eilvt_count = APIC_EILVT_NR_AMD_10H;
+
+	if (apic_eilvt_count)
+		eilvt_offsets = kzalloc_objs(atomic_t, apic_eilvt_count);
 }
 
 /*
-- 
2.54.0