[PATCH 0/5] arm64: dts: imx8mq-phanbell: Google Coral Dev Board enablement

[PATCH 0/5] arm64: dts: imx8mq-phanbell: Google Coral Dev Board enablement

[Rudi Heitbaum]

imx8mq-phanbell.dts describes very little of the Google Coral Dev Board
beyond the essentials. This series fixes two defects that affect the board
as it stands today, then adds the i2c buses, the 32 kHz reference clock pad
and the analog audio.

Patches 1 and 2 are bug fixes and stand on their own:

  - BUCK3 feeds the GPU rail and is the only regulator on the board that is
    neither always-on nor claimed by a consumer, so the regulator core
    switches it off when it finishes initialising and the board dies about
    thirty seconds into the boot.

  - The cpu_alert1 cooling map hardcodes an upper state of 2, which does
    not exist on a part whose speed grade provides only two operating
    points. The bind is rejected with -EINVAL and the trip ends up with no
    cooling device at all.

Patches 3 to 5 are enablement. Patch 5 depends on SND_SOC_RT5645 becoming
user selectable, which is "ASoC: rt5645: Make the Kconfig symbol user
selectable", queued in broonie/sound (for-7.2) and not yet in mainline. The
devicetree applies and builds without it; the codec simply cannot be
enabled until that lands.

Producing sound from the analog card also needs "ASoC: rt5645: Perform the
initial jack detect at probe", posted separately to ASoC. Nothing performs
the initial jack detect for a card described with simple-audio-card, so a
headphone already in the socket at boot is never noticed and the output is
silent. That is a codec driver fix rather than a devicetree one, hence the
separate posting.

Deliberately not included: pcie0 and pcie1 need the i.MX8MQ PCIe REF_CLK
source selection to be made conditional, which is a separate series still
in review, and the Bluetooth half of the QCA6174 depends on that in turn.

Tested on a Coral Dev Board on 7.2-rc6: buck3 stays up and the board boots
reliably, both thermal trips bind and throttling engages, the codec probes
on i2c3, and the headphone jack plays 44.1 kHz and 48 kHz.

Rudi Heitbaum (5):
  arm64: dts: imx8mq-phanbell: Keep the GPU rail on
  arm64: dts: imx8mq-phanbell: Do not hardcode a cooling state that may
    not exist
  arm64: dts: imx8mq-phanbell: Enable i2c2 and i2c3
  arm64: dts: imx8mq-phanbell: Mux the 32 kHz reference clock pad
  arm64: dts: imx8mq-phanbell: Enable the rt5645 analog audio

 .../boot/dts/freescale/imx8mq-phanbell.dts    | 124 +++++++++++++++++-
 1 file changed, 123 insertions(+), 1 deletion(-)


base-commit: 075b74841bd0065a3bda3440873c747938e69b68
-- 
2.53.0

[PATCH 1/5] arm64: dts: imx8mq-phanbell: Keep the GPU rail on

[Rudi Heitbaum]

BUCK3 feeds the GPU rail, and unlike every other regulator on this board
it is marked neither regulator-always-on nor referenced by any consumer.
Once a driver for the BD71837 is present the regulator core finds it
unused and switches it off when it completes initialisation:

  buck3: disabling

which takes the board out about thirty seconds into the boot.

Mark it always-on, matching the other seven bucks and all seven LDOs.

Handing it to the GPU power domain instead, the way imx8mq-librem5.dtsi
does, describes the hardware better but does not work here. With that
link removed the same image boots reliably. 

Signed-off-by: Rudi Heitbaum <rudi@heitbaum.com>
---
 arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts
index e34045d10a12..c06a787a4013 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts
@@ -156,6 +156,7 @@ buck3: BUCK3 {
 				regulator-min-microvolt = <700000>;
 				regulator-max-microvolt = <1300000>;
 				regulator-boot-on;
+				regulator-always-on;
 				rohm,dvs-run-voltage = <900000>;
 			};
 
-- 
2.53.0

[PATCH 2/5] arm64: dts: imx8mq-phanbell: Do not hardcode a cooling state that may not exist

[Rudi Heitbaum]

The cpu_alert1 map asks for cooling states 0 to 2, to exclude the two
highest operating points. How many operating points exist depends on the
speed grade: a53_opp_table gates each entry on opp-supported-hw, and a
grade 3 / segment 0 part gets only two of the four, 1.0GHz and 1.5GHz.
cpufreq-cpu0 then has max_state 1 and the bind is rejected:

  thermal thermal_zone0: binding cdev cpufreq-cpu0 to trip 3 failed: -22

thermal_bind_cdev_to_trip() returns -EINVAL when upper exceeds
max_state. The trip is left with no cooling device at all.

Use THERMAL_NO_LIMIT so the map means "all available states" and adapts
to whatever the part provides. On a device with the full table this is
still the hotter of the two trips and still allows more throttling than
cpu_alert0; on a two operating point part the two trips coincide, which
is the best that can be done there.

cpu_alert0 is unaffected: its upper bound of 1 is valid either way, which
is why frequency throttling works at 75C despite this failure.

Signed-off-by: Rudi Heitbaum <rudi@heitbaum.com>
---
 arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts
index c06a787a4013..4ad206f5a9d1 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts
@@ -101,7 +101,7 @@ map0 {
 		map1 {
 			trip = <&cpu_alert1>;
 			cooling-device =
-			<&A53_0 0 2>; /* Exclude two highest OPPs */
+			<&A53_0 0 THERMAL_NO_LIMIT>;
 		};
 
 		map4 {
-- 
2.53.0

[PATCH 3/5] arm64: dts: imx8mq-phanbell: Enable i2c2 and i2c3

[Rudi Heitbaum]

i2c2 is brought out on the 40-pin expansion header. i2c3 carries the
board's audio codec and also reaches the header.

Both run at 100 kHz, which is what the vendor devicetree uses. i2c1 is
internal to the board and carries only the PMIC, which is why it is the one
already at 400 kHz.

Signed-off-by: Rudi Heitbaum <rudi@heitbaum.com>
---
 .../boot/dts/freescale/imx8mq-phanbell.dts    | 28 +++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts
index 4ad206f5a9d1..58f7276eb557 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts
@@ -260,6 +260,20 @@ ldo7: LDO7 {
 	};
 };
 
+&i2c2 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c2>;
+	status = "okay";
+};
+
+&i2c3 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c3>;
+	status = "okay";
+};
+
 &fec1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_fec1>;
@@ -367,6 +381,20 @@ MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA			0x4000007f
 		>;
 	};
 
+	pinctrl_i2c2: i2c2grp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL			0x4000007f
+			MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA			0x4000007f
+		>;
+	};
+
+	pinctrl_i2c3: i2c3grp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL			0x4000007f
+			MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA			0x4000007f
+		>;
+	};
+
 	pinctrl_pmic: pmicirqgrp {
 		fsl,pins = <
 			MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3	0x41
-- 
2.53.0

[PATCH 4/5] arm64: dts: imx8mq-phanbell: Mux the 32 kHz reference clock pad

[Rudi Heitbaum]

Mux GPIO1_IO00 as the ANAMIX 32.768 kHz reference input rather than leave
it in its GPIO reset function. Nothing claims the pad as a consumer, so it
goes in a hog group.

The vendor devicetree hogs ten further pins alongside it, none of which has
a consumer anywhere in the tree. Those only set pad configuration on pins
the kernel does not otherwise touch, so they are left out.

Signed-off-by: Rudi Heitbaum <rudi@heitbaum.com>
---
 arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts
index 58f7276eb557..2d134eefb765 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts
@@ -348,6 +348,9 @@ &wdog1 {
 };
 
 &iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog>;
+
 	pinctrl_fec1: fec1grp {
 		fsl,pins = <
 			MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC			0x3
@@ -374,6 +377,12 @@ MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5			0x16
 		>;
 	};
 
+	pinctrl_hog: hoggrp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K	0x05
+		>;
+	};
+
 	pinctrl_i2c1: i2c1grp {
 		fsl,pins = <
 			MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL			0x4000007f
-- 
2.53.0

[PATCH 5/5] arm64: dts: imx8mq-phanbell: Enable the rt5645 analog audio

[Rudi Heitbaum]

The board has an rt5645 on i2c3 driving the 3.5 mm headphone jack, its
microphone and two on-board DMICs, fed by sai2.

The vendor kernel drives this codec from a machine driver of its own,
"google,edgetpu-audio-card", so its devicetree carries no widgets or
routing and the graph here is rebuilt for simple-audio-card. micbias1 is a
supply widget, and a supply is the source of a route rather than its sink -
as rt5645's own { "IN1P", NULL, "LDO2" } has it - so the sink/source pair
is "Headphone Mic", "micbias1".

GPIO5_IO4 carries headphone detect. The pad has to be muxed away from its
reset function, or both hp-detect-gpios and the codec interrupt point at a
pad that is still SPDIF_RX. Leaving realtek,jd-mode unset selects the mode
in which the driver takes jack state from hp-detect-gpios.

The slot width is pinned at 32 bits. With none set fsl_sai_hw_params()
takes it from the sample width, so a 24 bit open asks for a bit clock of
48000 * 2 * 24 = 2.304 MHz; fsl_sai_set_bclk() only accepts even dividers
and 24.576 MHz / 2.304 MHz is 10.67, so hw_params returns -EINVAL. 32 bit
slots ask for 3.072 MHz, a ratio of 8, and still carry 16 bit at the same
clock: rt5645_hw_params() takes the data length from params_width() and
only writes a BCLK-to-frame ratio for AIF2, so on AIF1 the codec ignores
the padding bits.

Declare both audio PLL families. fsl_sai only moves its mclk between the
8 kHz and 11.025 kHz families if the node names them as pll8k and pll11k,
which fsl_asoc_reparent_pll_clocks() then selects between by requested
rate. Without them the mclk is stuck at whatever assigned-clock-rates set
while 44100 is still on the advertised rate list, so ALSA is offered a rate
the clock cannot produce, does not resample, and hw_params fails:
44100 * 2 * 32 = 2.8224 MHz, and 24.576 MHz divided by that is 8.707.

The cpu dai also needs system-clock-direction-out. Without it
simple_util_parse_clk() leaves clk_direction at 0, which is
SND_SOC_CLOCK_IN, and fsl_sai_set_dai_sysclk() opens with
"if (dir == SND_SOC_CLOCK_IN) return 0". So set_sysclk returns without
setting the mclk rate and without ever reaching the reparent, silently and
at every rate.

Signed-off-by: Rudi Heitbaum <rudi@heitbaum.com>
---
 .../boot/dts/freescale/imx8mq-phanbell.dts    | 84 +++++++++++++++++++
 1 file changed, 84 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts
index 2d134eefb765..b819e644fa54 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts
@@ -46,6 +46,41 @@ fan: gpio-fan {
 		pinctrl-0 = <&pinctrl_gpio_fan>;
 		status = "okay";
 	};
+
+	sound-analog {
+		compatible = "simple-audio-card";
+		simple-audio-card,name = "Coral Analog";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,bitclock-master = <&sound_analog_cpu>;
+		simple-audio-card,frame-master = <&sound_analog_cpu>;
+		simple-audio-card,mclk-fs = <256>;
+
+		simple-audio-card,widgets = "Headphone", "Headphone Jack",
+					    "Microphone", "Headphone Mic",
+					    "Microphone", "Internal Mic";
+
+		simple-audio-card,routing = "Headphone Jack", "HPOL",
+					    "Headphone Jack", "HPOR",
+					    "Headphone Mic", "micbias1",
+					    "DMIC L1", "Internal Mic",
+					    "DMIC R1", "Internal Mic";
+
+		/*
+		 * 32 bit slots regardless of the sample width. sai2 divides its
+		 * 24.576 MHz root by an even integer only, so a 24 bit frame at
+		 * 48 kHz would ask for 2.304 MHz, a ratio of 10.67.
+		 */
+		sound_analog_cpu: simple-audio-card,cpu {
+			sound-dai = <&sai2>;
+			system-clock-direction-out;
+			dai-tdm-slot-num = <2>;
+			dai-tdm-slot-width = <32>;
+		};
+
+		simple-audio-card,codec {
+			sound-dai = <&rt5645>;
+		};
+	};
 };
 
 &A53_0 {
@@ -272,6 +307,18 @@ &i2c3 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_i2c3>;
 	status = "okay";
+
+	rt5645: audio-codec@1a {
+		compatible = "realtek,rt5645";
+		reg = <0x1a>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_hp_det>;
+		#sound-dai-cells = <0>;
+		interrupt-parent = <&gpio5>;
+		interrupts = <4 IRQ_TYPE_EDGE_BOTH>;
+		hp-detect-gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
+		realtek,dmic1-data-pin = <2>;
+	};
 };
 
 &fec1 {
@@ -295,6 +342,27 @@ ethphy0: ethernet-phy@0 {
 	};
 };
 
+&sai2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_sai2>;
+	/*
+	 * pll8k and pll11k let fsl_sai move the mclk between the two
+	 * audio PLL families, so 44.1 kHz rates work as well as 48 kHz.
+	 */
+	clocks = <&clk IMX8MQ_CLK_SAI2_IPG>,
+		 <&clk IMX8MQ_CLK_SAI2_ROOT>,
+		 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>,
+		 <&clk IMX8MQ_AUDIO_PLL1_OUT>,
+		 <&clk IMX8MQ_AUDIO_PLL2_OUT>;
+	clock-names = "bus", "mclk1", "mclk2", "mclk3",
+		      "pll8k", "pll11k";
+	assigned-clocks = <&clk IMX8MQ_CLK_SAI2>;
+	assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
+	assigned-clock-rates = <24576000>;
+	fsl,sai-mclk-direction-output;
+	status = "okay";
+};
+
 &uart1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_uart1>;
@@ -383,6 +451,12 @@ MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K	0x05
 		>;
 	};
 
+	pinctrl_hp_det: hpdetgrp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_SPDIF_RX_GPIO5_IO4			0xd6
+		>;
+	};
+
 	pinctrl_i2c1: i2c1grp {
 		fsl,pins = <
 			MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL			0x4000007f
@@ -410,6 +484,16 @@ MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3	0x41
 		>;
 	};
 
+	pinctrl_sai2: sai2grp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK		0xd6
+			MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC		0xd6
+			MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK		0xd6
+			MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0		0xd6
+			MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0		0xd6
+		>;
+	};
+
 	pinctrl_uart1: uart1grp {
 		fsl,pins = <
 			MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX		0x49
-- 
2.53.0