[PATCH v2 0/9] MIPS: Ingenic: Add XBurst / XBurst II infrastructure and improve overall Ingenic SoC support

[PATCH v2 0/9] MIPS: Ingenic: Add XBurst / XBurst II infrastructure and improve overall Ingenic SoC support

[H. Nikolaus Schaller]

PATCH V2 2026-11-12 09:10:31:
The series updates the Ingenic platform support to allow clean transitions
between bootloader-provided Device Trees and built-in fallbacks. It provides
the foundational Kconfig, PRID, and CPU-probe blocks required for newer 
Ingenic/Lumissil hardware generations (X1600, X2000, X2600) and adds JZ4730
for completeness.

Changes to V1
- allow user selection of BUILTIN_DTB (suggested by Paul Cercueil <paul@crapouillou.net>)
- added the CPU_XBURTS2 type here to solve an issue reported by kernel test robot
- removed PRID_IMP_XBURST2_R2 and merged into single commit
- reviewed all PRID_IMP with data sheets and programming manuals
- added full x2600 and jz4730 definition for completeness
- added platform makefile and load address for X1600, X2000, X2600

PATCH V1 2026-10-25 20:20:55:
The series updates the Ingenic platform support to allow clean transitions
between bootloader-provided Device Trees and built-in fallbacks. It provides
the foundational Kconfig, PRID, and CPU-probe blocks required for newer 
Ingenic/Lumissil hardware generations (X1600, X2000, X2600).

The first patch corrects an inverted Kconfig condition regarding appended 
and built-in DTBs. This fix is necessary to allow configurations where 
the kernel relies entirely on a Device Tree provided dynamically by the 
bootloader instead of forcing a built-in fallback.

The remaining patches implement CPU-probe initialization, correct PRID 
mappings (including vendor-kernel values for the Ingenic A1 SoC), 
platform load addresses, Kconfig updates, and generic board match updates.

Structure of the series:
1. MIPS: Ingenic: Fix inverted MIPS_NO_APPENDED_DTB logic in Kconfig
2. MIPS: Ingenic: Add and update PRIDs for XBurst II R0 and R2
3. MIPS: Ingenic: Expand Kconfig for X1600, X2000, and X2600 SoCs
4. MIPS: Ingenic: Add cpu-probe setup for XBurst and XBurst II R2
5. MIPS: generic: Add MACH_INGENIC type and compatible for X1600
6. MIPS: Ingenic: Add Platform makefile for X1600 and X2000

Testing:
The series has been compile-tested for generic Ingenic targets. PRID 
values for jz4780, x1600, X2000, X2600 were verified on real hardware 
(CI20, LX16, LX20 and LX26 boards respectively).

Please review and consider for inclusion.


H. Nikolaus Schaller (8):
  MIPS: Kconfig: Allow user selection of BUILTIN_DTB with description
  MIPS: Ingenic: Configure CONFIG_BUILTIN_DTB=y for Ingenic based
    devices
  MIPS: Ingenic: Do not force BUILTIN_DTB in Kconfig
  MIPS: Ingenic: Update Ingenic XBurst implementation IDs
  MIPS: generic: Add MACH_INGENIC type and compatible for X1600 and
    X2600
  MIPS: Ingenic: Expand Kconfig for X1600, X2000, and X2600 SoCs
  MIPS: Ingenic: Expand Kconfig by MACH_JZ4730
  MIPS: Ingenic: Add Platform makefile and load addresses for X1600,
    X2000, X2600

周琰杰 (Zhou Yanjie) (1):
  MIPS: Ingenic: Add a new CPU_XBURST2 type

 arch/mips/Kconfig                      | 25 +++++++++++++--
 arch/mips/configs/ci20_defconfig       |  1 +
 arch/mips/configs/cu1000-neo_defconfig |  1 +
 arch/mips/configs/cu1830-neo_defconfig |  1 +
 arch/mips/configs/gcw0_defconfig       |  1 +
 arch/mips/configs/qi_lb60_defconfig    |  1 +
 arch/mips/configs/rs90_defconfig       |  1 +
 arch/mips/generic/board-ingenic.c      |  8 ++++-
 arch/mips/include/asm/bootinfo.h       |  2 ++
 arch/mips/include/asm/cpu-type.h       |  1 +
 arch/mips/include/asm/cpu.h            | 13 ++++----
 arch/mips/ingenic/Kconfig              | 43 ++++++++++++++++++++++++++
 arch/mips/ingenic/Platform             |  3 ++
 arch/mips/kernel/cpu-probe.c           |  7 +++++
 14 files changed, 99 insertions(+), 9 deletions(-)
 create mode 100644 arch/mips/ingenic/Platform

-- 
2.56.0

[PATCH v2 1/9] MIPS: Kconfig: Allow user selection of BUILTIN_DTB with description

[H. Nikolaus Schaller]

Make CONFIG_BUILTIN_DTB visible in Kconfig by adding a prompt and a
detailed help text.

Previously, BUILTIN_DTB was a silent option forcefully selected by
certain machine types (such as MACH_INGENIC) whenever appended DTB
support was disabled. This prevented modern setups from turning off the
built-in DTB fallback when the bootloader is fully capable of passing a
dynamic DTB.

By adding a prompt, users can now explicitly toggle this behavior. The
added help text clarifies the distinction between MIPS_NO_APPENDED_DTB
(which controls image appending) and BUILTIN_DTB (which controls the
compiled-in fallback data and code path via get_fdt()), as well as its
relationship to BUILTIN_DTB_NAME.

Suggested-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com>
---

Notes:
    Help text and commit message generated by public Google AI.

 arch/mips/Kconfig | 24 +++++++++++++++++++++++-
 1 file changed, 23 insertions(+), 1 deletion(-)

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index dac3ec5120a34..92bca520cd5ae 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -2924,7 +2924,29 @@ config UHI_BOOT
 	bool
 
 config BUILTIN_DTB
-	bool
+	bool "Enable builtin DTB fallback support"
+	depends on USE_OF
+	help
+	  Compiles a Device Tree Blob (DTB) directly into the kernel image
+	  and enables the kernel to use it as a fallback during boot.
+
+	  This option:
+	  a) Links the DTB specified by BUILTIN_DTB_NAME into the
+	     kernel binary.
+	  b) Instructs the boot code (get_fdt()) to return this internal
+	     DTB if no dynamic DTB from the bootloader or appended DTB
+	     image data is detected.
+
+	  Note on MIPS boot strategy:
+	  MIPS kernels check for a DTB in the following order inside get_fdt():
+	  1. An appended DTB image (if CONFIG_MIPS_*_APPENDED_DTB is set).
+	  2. The built-in DTB fallback controlled by this option.
+
+	  If your bootloader provides a valid DTB dynamically and you do not
+	  rely on appended or built-in DTBs, you should enable
+	  MIPS_NO_APPENDED_DTB and disable BUILTIN_DTB.
+
+	  If unsure, say Y.
 
 choice
 	prompt "Kernel appended dtb support"
-- 
2.56.0

[PATCH v2 2/9] MIPS: Ingenic: Configure CONFIG_BUILTIN_DTB=y for Ingenic based devices

[H. Nikolaus Schaller]

This enables the new CONFIG_BUILTIN_DTB user variable so that we do
not need to rely on a select CONFIG_BUILTIN_DTB if ..." any more

Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com>
---
 arch/mips/configs/ci20_defconfig       | 1 +
 arch/mips/configs/cu1000-neo_defconfig | 1 +
 arch/mips/configs/cu1830-neo_defconfig | 1 +
 arch/mips/configs/gcw0_defconfig       | 1 +
 arch/mips/configs/qi_lb60_defconfig    | 1 +
 arch/mips/configs/rs90_defconfig       | 1 +
 6 files changed, 6 insertions(+)

diff --git a/arch/mips/configs/ci20_defconfig b/arch/mips/configs/ci20_defconfig
index 90536cab417ee..b45a6c7b54ea8 100644
--- a/arch/mips/configs/ci20_defconfig
+++ b/arch/mips/configs/ci20_defconfig
@@ -23,6 +23,7 @@ CONFIG_MACH_INGENIC_SOC=y
 CONFIG_JZ4780_CI20=y
 CONFIG_HIGHMEM=y
 CONFIG_HZ_100=y
+CONFIG_BUILTIN_DTB=y
 # CONFIG_SUSPEND is not set
 # CONFIG_SECCOMP is not set
 CONFIG_MODULES=y
diff --git a/arch/mips/configs/cu1000-neo_defconfig b/arch/mips/configs/cu1000-neo_defconfig
index ed2a620e4f86a..a505de6e9e367 100644
--- a/arch/mips/configs/cu1000-neo_defconfig
+++ b/arch/mips/configs/cu1000-neo_defconfig
@@ -22,6 +22,7 @@ CONFIG_MACH_INGENIC_SOC=y
 CONFIG_X1000_CU1000_NEO=y
 CONFIG_HIGHMEM=y
 CONFIG_HZ_100=y
+CONFIG_BUILTIN_DTB=y
 # CONFIG_SECCOMP is not set
 # CONFIG_SUSPEND is not set
 CONFIG_MODULES=y
diff --git a/arch/mips/configs/cu1830-neo_defconfig b/arch/mips/configs/cu1830-neo_defconfig
index 9b4aeeef58ceb..1fa7a49543063 100644
--- a/arch/mips/configs/cu1830-neo_defconfig
+++ b/arch/mips/configs/cu1830-neo_defconfig
@@ -22,6 +22,7 @@ CONFIG_MACH_INGENIC_SOC=y
 CONFIG_X1830_CU1830_NEO=y
 CONFIG_HIGHMEM=y
 CONFIG_HZ_100=y
+CONFIG_BUILTIN_DTB=y
 # CONFIG_SECCOMP is not set
 # CONFIG_SUSPEND is not set
 CONFIG_MODULES=y
diff --git a/arch/mips/configs/gcw0_defconfig b/arch/mips/configs/gcw0_defconfig
index 6d737810b470f..36ef053376185 100644
--- a/arch/mips/configs/gcw0_defconfig
+++ b/arch/mips/configs/gcw0_defconfig
@@ -7,6 +7,7 @@ CONFIG_PROFILING=y
 CONFIG_MACH_INGENIC_SOC=y
 CONFIG_JZ4770_GCW0=y
 CONFIG_HIGHMEM=y
+CONFIG_BUILTIN_DTB=y
 # CONFIG_SECCOMP is not set
 CONFIG_MIPS_RAW_APPENDED_DTB=y
 CONFIG_MIPS_CMDLINE_DTB_EXTEND=y
diff --git a/arch/mips/configs/qi_lb60_defconfig b/arch/mips/configs/qi_lb60_defconfig
index a1bb0792f6eb1..18fe70487817c 100644
--- a/arch/mips/configs/qi_lb60_defconfig
+++ b/arch/mips/configs/qi_lb60_defconfig
@@ -9,6 +9,7 @@ CONFIG_EXPERT=y
 CONFIG_MACH_INGENIC_SOC=y
 CONFIG_JZ4740_QI_LB60=y
 CONFIG_HZ_100=y
+CONFIG_BUILTIN_DTB=y
 # CONFIG_SECCOMP is not set
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
diff --git a/arch/mips/configs/rs90_defconfig b/arch/mips/configs/rs90_defconfig
index 8382d535e6dc1..0c57d829d1720 100644
--- a/arch/mips/configs/rs90_defconfig
+++ b/arch/mips/configs/rs90_defconfig
@@ -22,6 +22,7 @@ CONFIG_MACH_INGENIC_SOC=y
 CONFIG_JZ4740_RS90=y
 CONFIG_PAGE_SIZE_16KB=y
 CONFIG_HZ_100=y
+CONFIG_BUILTIN_DTB=y
 # CONFIG_SECCOMP is not set
 CONFIG_MIPS_CMDLINE_DTB_EXTEND=y
 # CONFIG_SUSPEND is not set
-- 
2.56.0

[PATCH v2 3/9] MIPS: Ingenic: Do not force BUILTIN_DTB in Kconfig

[H. Nikolaus Schaller]

Remove the unconditional selection of BUILTIN_DTB for MACH_INGENIC
when MIPS_NO_APPENDED_DTB is enabled.

The current Kconfig logic selects BUILTIN_DTB when
MIPS_NO_APPENDED_DTB is set, although this configuration is intended
to prevent the kernel from appending a DTB to the kernel image.

While the kernel gives precedence to a DTB supplied by the boot loader,
selecting BUILTIN_DTB still triggers additional build steps and may
add unnecessary code to the resulting uImage.

Note that BUILTIN_DTB controls the build process, not necessarily
whether a DTB is actually embedded in the kernel image. For example,
CONFIG_BUILTIN_DTB=y with CONFIG_BUILTIN_DTB_NAME="" still triggers
the generation of .builtin-dtbs.S, but does not embed a DTB.

The goal is to allow a configuration in which no .builtin-dtbs.S
is generated and no DTB is appended to or built into the zImage/uImage.

Fixes: f0f4a753079c ("MIPS: generic: Add support for Ingenic SoCs")
Fixes: 15205fc05482 ("MIPS: ingenic: Add support for appended devicetree")
Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com>
---
 arch/mips/Kconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 92bca520cd5ae..2135a69f9962c 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -127,7 +127,6 @@ config MACH_INGENIC
 	select GPIOLIB
 	select COMMON_CLK
 	select GENERIC_IRQ_CHIP
-	select BUILTIN_DTB if MIPS_NO_APPENDED_DTB
 	select USE_OF
 	select CPU_SUPPORTS_CPUFREQ
 	select MIPS_EXTERNAL_TIMER
-- 
2.56.0

Re: [PATCH v2 3/9] MIPS: Ingenic: Do not force BUILTIN_DTB in Kconfig

[Paul Cercueil]

Hi Nikolaus,

Le jeudi 12 novembre 2026 à 09:10 +0100, H. Nikolaus Schaller a écrit :
> Remove the unconditional selection of BUILTIN_DTB for MACH_INGENIC
> when MIPS_NO_APPENDED_DTB is enabled.
> 
> The current Kconfig logic selects BUILTIN_DTB when
> MIPS_NO_APPENDED_DTB is set, although this configuration is intended
> to prevent the kernel from appending a DTB to the kernel image.
> 
> While the kernel gives precedence to a DTB supplied by the boot loader,
> selecting BUILTIN_DTB still triggers additional build steps and may
> add unnecessary code to the resulting uImage.
> 
> Note that BUILTIN_DTB controls the build process, not necessarily
> whether a DTB is actually embedded in the kernel image. For example,
> CONFIG_BUILTIN_DTB=y with CONFIG_BUILTIN_DTB_NAME="" still triggers
> the generation of .builtin-dtbs.S, but does not embed a DTB.
> 
> The goal is to allow a configuration in which no .builtin-dtbs.S
> is generated and no DTB is appended to or built into the zImage/uImage.
> 
> Fixes: f0f4a753079c ("MIPS: generic: Add support for Ingenic SoCs")
> Fixes: 15205fc05482 ("MIPS: ingenic: Add support for appended devicetree")

I don't think you can have two Fixes: tags...

Cheers,
-Paul

> Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com>
> ---
>  arch/mips/Kconfig | 1 -
>  1 file changed, 1 deletion(-)
> 
> diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
> index 92bca520cd5ae..2135a69f9962c 100644
> --- a/arch/mips/Kconfig
> +++ b/arch/mips/Kconfig
> @@ -127,7 +127,6 @@ config MACH_INGENIC
>  	select GPIOLIB
>  	select COMMON_CLK
>  	select GENERIC_IRQ_CHIP
> -	select BUILTIN_DTB if MIPS_NO_APPENDED_DTB
>  	select USE_OF
>  	select CPU_SUPPORTS_CPUFREQ
>  	select MIPS_EXTERNAL_TIMER

Re: [PATCH v2 3/9] MIPS: Ingenic: Do not force BUILTIN_DTB in Kconfig

[H. Nikolaus Schaller]

> Am 12.11.2026 um 14:57 schrieb Paul Cercueil <paul@crapouillou.net>:
> 
> Hi Nikolaus,
> 
> Le jeudi 12 novembre 2026 à 09:10 +0100, H. Nikolaus Schaller a écrit :
>> Remove the unconditional selection of BUILTIN_DTB for MACH_INGENIC
>> when MIPS_NO_APPENDED_DTB is enabled.
>> 
>> The current Kconfig logic selects BUILTIN_DTB when
>> MIPS_NO_APPENDED_DTB is set, although this configuration is intended
>> to prevent the kernel from appending a DTB to the kernel image.
>> 
>> While the kernel gives precedence to a DTB supplied by the boot loader,
>> selecting BUILTIN_DTB still triggers additional build steps and may
>> add unnecessary code to the resulting uImage.
>> 
>> Note that BUILTIN_DTB controls the build process, not necessarily
>> whether a DTB is actually embedded in the kernel image. For example,
>> CONFIG_BUILTIN_DTB=y with CONFIG_BUILTIN_DTB_NAME="" still triggers
>> the generation of .builtin-dtbs.S, but does not embed a DTB.
>> 
>> The goal is to allow a configuration in which no .builtin-dtbs.S
>> is generated and no DTB is appended to or built into the zImage/uImage.
>> 
>> Fixes: f0f4a753079c ("MIPS: generic: Add support for Ingenic SoCs")
>> Fixes: 15205fc05482 ("MIPS: ingenic: Add support for appended devicetree")
> 
> I don't think you can have two Fixes: tags...

Oops. Must be the result of mechanically squashing commits...

Will be fixed for V3.
> 
> Cheers,
> -Paul

Same to you :)
Nikolaus

> 
>> Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com>
>> ---
>>  arch/mips/Kconfig | 1 -
>>  1 file changed, 1 deletion(-)
>> 
>> diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
>> index 92bca520cd5ae..2135a69f9962c 100644
>> --- a/arch/mips/Kconfig
>> +++ b/arch/mips/Kconfig
>> @@ -127,7 +127,6 @@ config MACH_INGENIC
>>   select GPIOLIB
>>   select COMMON_CLK
>>   select GENERIC_IRQ_CHIP
>> - select BUILTIN_DTB if MIPS_NO_APPENDED_DTB
>>   select USE_OF
>>   select CPU_SUPPORTS_CPUFREQ
>>   select MIPS_EXTERNAL_TIMER

[PATCH v2 4/9] MIPS: Ingenic: Add a new CPU_XBURST2 type

[H. Nikolaus Schaller]

From: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>

Add a new CPU_XBURST2 type for the MIPS32r5 compatible XBurst®2 CPU.

Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com>
---

Notes:
    This patch solves a build error in
    
    "MIPS: Ingenic: Update Ingenic XBurst implementation IDs"
    
    reported by kernel test robot.

 arch/mips/include/asm/cpu-type.h | 1 +
 arch/mips/include/asm/cpu.h      | 4 ++--
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/mips/include/asm/cpu-type.h b/arch/mips/include/asm/cpu-type.h
index fd37a44a2f199..25a181fd0eb7a 100644
--- a/arch/mips/include/asm/cpu-type.h
+++ b/arch/mips/include/asm/cpu-type.h
@@ -56,6 +56,7 @@ static inline int __pure __get_cpu_type(const int cpu_type)
 #ifdef CONFIG_SYS_HAS_CPU_MIPS32_R5
 	case CPU_M5150:
 	case CPU_P5600:
+	case CPU_XBURST2:
 #endif
 
 #if defined(CONFIG_SYS_HAS_CPU_MIPS32_R2) || \
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 0fd9f9bbd21f1..add26f08e8029 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -312,8 +312,8 @@ enum cpu_type_enum {
 	 */
 	CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,
 	CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350,
-	CPU_BMIPS4380, CPU_BMIPS5000, CPU_XBURST, CPU_LOONGSON32, CPU_M14KC,
-	CPU_M14KEC, CPU_INTERAPTIV, CPU_P5600, CPU_PROAPTIV, CPU_1074K,
+	CPU_BMIPS4380, CPU_BMIPS5000, CPU_XBURST, CPU_XBURST2, CPU_LOONGSON32,
+	CPU_M14KC, CPU_M14KEC, CPU_INTERAPTIV, CPU_P5600, CPU_PROAPTIV, CPU_1074K,
 	CPU_M5150, CPU_I6400, CPU_P6600, CPU_M6250,
 
 	/*
-- 
2.56.0

[PATCH v2 5/9] MIPS: Ingenic: Update Ingenic XBurst implementation IDs

[H. Nikolaus Schaller]

Add PRID implementation constants for Ingenic XBurst and XBurst II
processors and handle the corresponding implementation IDs in
cpu_probe_ingenic().

The PRID table is updated based on Programming Manuals and hardware tests:
- jz4780: 0x3ee1024f (confirmed on CI20 board)
- x1000:  0x2ed1024f (unconfirmed)
- x1600:  0x00d00000 (confirmed on LX16 board)
- X1830:  0x00d00100 (unconfirmed)
- X2000:  0x00132000 (read out from LX20 board)
- X2600:  0x001320xx (confirmed 0x00132000 on LX26 board)

Additionally, clean up extra spaces in the comments for
PRID_IMP_XBURST_REV2 and PRID_IMP_XBURST2.

Distinguish XBurst1 implementations with different SIMD ISA revisions
and identify XBurst II processors using PRID_IMP_XBURST2.
The XBurst II classification follows the Ingenic vendor kernel.

Keep the existing writecombine handling unchanged, since no
independent evidence justifies changing the cache attribute for
XBurst II.

Public references:
- Ingenic Community, public SoC datasheets and programming manuals:
  https://github.com/Ingenic-community/datasheets/tree/main/X
  Includes the X1600 programming manual (X1600_PM_20220117.pdf)
  and documentation for other X-series SoCs, including X1000,
  X1830 and X2000.
- Ingenic, XBurst1 CPU Core Programming Manual:
  https://cdn.hackaday.io/files/1855627939084608/XBurst1_Core_PM.pdf
  Documents the XBurst1 core architecture and CP0 configuration.
- Ingenic, XBurst Instruction Set Architecture Programming Manual:
  https://www.setphaserstostun.org/ci20/X1000_M200_XBurst_ISA_MXU_PM.pdf
  Documents the original XBurst SIMD instruction set.
- Ingenic, XBurst2 CPU Core Programming Manual:
  https://www.manualslib.com/manual/2646351/Ingenic-Xburst-2-Cpu-Core.html
  Documents the XBurst2 core architecture.
- Ingenic, MIPS-LINUX toolchain R6.0.0 release notes:
  https://www.ingenic.com.cn/news-detail/nid-343.html
  Distinguishes MSA, MXA and MXU/MXU2 support in the toolchain.
- Ingenic, MIPS-LINUX toolchain R6.2.1 release notes:
  https://www.ingenic.com.cn/news-detail/nid-348.html
  Documents MXU3 support and identifies X2000 as an MSA target.

The public references document the available CPU, SoC and ISA
information. The PRID implementation handling follows the Ingenic
vendor kernel.

AI assistance: ChatGPT was used to help review the PRID definitions,
compare the Ingenic vendor implementation with the upstream code,
and draft the commit message with public references. The code changes,
hardware observations, and final patch were reviewed by the authors.

Co-developed-by: Paul Boddie <paul@boddie.org.uk>
Signed-off-by: Paul Boddie <paul@boddie.org.uk>
Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com>
---

Notes:
    Changes in V2:
    - removed the PRID_IMP_XBURST2_R2 definition and hints for an x2100 as
      there is no public reference
    - merged into single commit changing the PRID definitions and code
    - reviewed details and rewrote commit message
    
    Open Issue:
    Olivier Louvignes <olivier@mgcrea.io> pointed out that he has
    simply reused the definition of the X1830 for the X1600. This
    sets c->writecombine differently (_CACHE_CACHABLE_WA) from
    _CACHE_UNCACHED_ACCELERATED as we do here.
    Both settings appear to work but it needs expert comment which
    is the right/better one.

 arch/mips/include/asm/cpu.h  | 9 +++++----
 arch/mips/kernel/cpu-probe.c | 7 +++++++
 2 files changed, 12 insertions(+), 4 deletions(-)

diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index add26f08e8029..79fd9a0747cf2 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -47,7 +47,7 @@
 #define PRID_COMP_CAVIUM	0x0d0000
 #define PRID_COMP_LOONGSON	0x140000
 #define PRID_COMP_INGENIC_13	0x130000	/* X2000, X2100 */
-#define PRID_COMP_INGENIC_D0	0xd00000	/* JZ4730, JZ4740, JZ4750, JZ4755, JZ4760, X1830 */
+#define PRID_COMP_INGENIC_D0	0xd00000	/* JZ4730, JZ4740, JZ4750, JZ4755, JZ4760, X1830, X1600 */
 #define PRID_COMP_INGENIC_D1	0xd10000	/* JZ4770, JZ4775, X1000 */
 #define PRID_COMP_INGENIC_E1	0xe10000	/* JZ4780 */
 
@@ -186,9 +186,10 @@
  * These are the PRID's for when 23:16 == PRID_COMP_INGENIC_*
  */
 
-#define PRID_IMP_XBURST_REV1	0x0200	/* XBurst®1 with MXU1.0/MXU1.1 SIMD ISA	*/
-#define PRID_IMP_XBURST_REV2	0x0100	/* XBurst®1 with MXU2.0 SIMD ISA		*/
-#define PRID_IMP_XBURST2		0x2000	/* XBurst®2 with MXU2.1 SIMD ISA		*/
+#define PRID_IMP_XBURST		0x0000	/* XBurst1 */
+#define PRID_IMP_XBURST_REV1	0x0200	/* XBurst1 with MXU1.0/MXU1.1 SIMD ISA */
+#define PRID_IMP_XBURST_REV2	0x0100	/* XBurst1 with MXU2.0 SIMD ISA */
+#define PRID_IMP_XBURST2	0x2000	/* XBurst2 with MXU2.1 SIMD ISA */
 
 /*
  * These are the PRID's for when 23:16 == PRID_COMP_NETLOGIC
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 489612ed9d498..69b68d00b66f7 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -1768,6 +1768,13 @@ static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
 
 	switch (c->processor_id & PRID_IMP_MASK) {
 
+	/* XBurst®1 with ISA */
+	case PRID_IMP_XBURST:
+		c->cputype = CPU_XBURST;
+		c->writecombine = _CACHE_UNCACHED_ACCELERATED;
+		__cpu_name[cpu] = "Ingenic XBurst";
+		break;
+
 	/* XBurst®1 with MXU1.0/MXU1.1 SIMD ISA */
 	case PRID_IMP_XBURST_REV1:
 
-- 
2.56.0

Re: [PATCH v2 5/9] MIPS: Ingenic: Update Ingenic XBurst implementation IDs

[Paul Cercueil]

Hi Nikolaus,

Le jeudi 12 novembre 2026 à 09:10 +0100, H. Nikolaus Schaller a écrit :
> Add PRID implementation constants for Ingenic XBurst and XBurst II
> processors and handle the corresponding implementation IDs in
> cpu_probe_ingenic().
> 
> The PRID table is updated based on Programming Manuals and hardware tests:
> - jz4780: 0x3ee1024f (confirmed on CI20 board)
> - x1000:  0x2ed1024f (unconfirmed)
> - x1600:  0x00d00000 (confirmed on LX16 board)
> - X1830:  0x00d00100 (unconfirmed)
> - X2000:  0x00132000 (read out from LX20 board)
> - X2600:  0x001320xx (confirmed 0x00132000 on LX26 board)
> 
> Additionally, clean up extra spaces in the comments for
> PRID_IMP_XBURST_REV2 and PRID_IMP_XBURST2.
> 
> Distinguish XBurst1 implementations with different SIMD ISA revisions
> and identify XBurst II processors using PRID_IMP_XBURST2.
> The XBurst II classification follows the Ingenic vendor kernel.
> 
> Keep the existing writecombine handling unchanged, since no
> independent evidence justifies changing the cache attribute for
> XBurst II.
> 
> Public references:
> - Ingenic Community, public SoC datasheets and programming manuals:
>   https://github.com/Ingenic-community/datasheets/tree/main/X
>   Includes the X1600 programming manual (X1600_PM_20220117.pdf)
>   and documentation for other X-series SoCs, including X1000,
>   X1830 and X2000.
> - Ingenic, XBurst1 CPU Core Programming Manual:
>   https://cdn.hackaday.io/files/1855627939084608/XBurst1_Core_PM.pdf
>   Documents the XBurst1 core architecture and CP0 configuration.
> - Ingenic, XBurst Instruction Set Architecture Programming Manual:
>   https://www.setphaserstostun.org/ci20/X1000_M200_XBurst_ISA_MXU_PM.pdf
>   Documents the original XBurst SIMD instruction set.
> - Ingenic, XBurst2 CPU Core Programming Manual:
>   https://www.manualslib.com/manual/2646351/Ingenic-Xburst-2-Cpu-Core.html
>   Documents the XBurst2 core architecture.
> - Ingenic, MIPS-LINUX toolchain R6.0.0 release notes:
>   https://www.ingenic.com.cn/news-detail/nid-343.html
>   Distinguishes MSA, MXA and MXU/MXU2 support in the toolchain.
> - Ingenic, MIPS-LINUX toolchain R6.2.1 release notes:
>   https://www.ingenic.com.cn/news-detail/nid-348.html
>   Documents MXU3 support and identifies X2000 as an MSA target.
> 
> The public references document the available CPU, SoC and ISA
> information. The PRID implementation handling follows the Ingenic
> vendor kernel.
> 
> AI assistance: ChatGPT was used to help review the PRID definitions,
> compare the Ingenic vendor implementation with the upstream code,
> and draft the commit message with public references. The code changes,
> hardware observations, and final patch were reviewed by the authors.
> 
> Co-developed-by: Paul Boddie <paul@boddie.org.uk>
> Signed-off-by: Paul Boddie <paul@boddie.org.uk>
> Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com>
> ---
> 
> Notes:
>     Changes in V2:
>     - removed the PRID_IMP_XBURST2_R2 definition and hints for an x2100 as
>       there is no public reference
>     - merged into single commit changing the PRID definitions and code
>     - reviewed details and rewrote commit message
>     
>     Open Issue:
>     Olivier Louvignes <olivier@mgcrea.io> pointed out that he has
>     simply reused the definition of the X1830 for the X1600. This
>     sets c->writecombine differently (_CACHE_CACHABLE_WA) from
>     _CACHE_UNCACHED_ACCELERATED as we do here.
>     Both settings appear to work but it needs expert comment which
>     is the right/better one.
> 
>  arch/mips/include/asm/cpu.h  | 9 +++++----
>  arch/mips/kernel/cpu-probe.c | 7 +++++++
>  2 files changed, 12 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
> index add26f08e8029..79fd9a0747cf2 100644
> --- a/arch/mips/include/asm/cpu.h
> +++ b/arch/mips/include/asm/cpu.h
> @@ -47,7 +47,7 @@
>  #define PRID_COMP_CAVIUM	0x0d0000
>  #define PRID_COMP_LOONGSON	0x140000
>  #define PRID_COMP_INGENIC_13	0x130000	/* X2000, X2100 */
> -#define PRID_COMP_INGENIC_D0	0xd00000	/* JZ4730, JZ4740, JZ4750,
> JZ4755, JZ4760, X1830 */
> +#define PRID_COMP_INGENIC_D0	0xd00000	/* JZ4730, JZ4740, JZ4750,
> JZ4755, JZ4760, X1830, X1600 */
>  #define PRID_COMP_INGENIC_D1	0xd10000	/* JZ4770, JZ4775, X1000 */
>  #define PRID_COMP_INGENIC_E1	0xe10000	/* JZ4780 */
>  
> @@ -186,9 +186,10 @@
>   * These are the PRID's for when 23:16 == PRID_COMP_INGENIC_*
>   */
>  
> -#define PRID_IMP_XBURST_REV1	0x0200	/* XBurst®1 with MXU1.0/MXU1.1 SIMD
> ISA	*/
> -#define PRID_IMP_XBURST_REV2	0x0100	/* XBurst®1 with MXU2.0 SIMD
> ISA		*/
> -#define PRID_IMP_XBURST2		0x2000	/* XBurst®2 with MXU2.1 SIMD
> ISA		*/
> +#define PRID_IMP_XBURST		0x0000	/* XBurst1 */
> +#define PRID_IMP_XBURST_REV1	0x0200	/* XBurst1 with MXU1.0/MXU1.1 SIMD
> ISA */
> +#define PRID_IMP_XBURST_REV2	0x0100	/* XBurst1 with MXU2.0 SIMD ISA */
> +#define PRID_IMP_XBURST2	0x2000	/* XBurst2 with MXU2.1 SIMD ISA */
>  
>  /*
>   * These are the PRID's for when 23:16 == PRID_COMP_NETLOGIC
> diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
> index 489612ed9d498..69b68d00b66f7 100644
> --- a/arch/mips/kernel/cpu-probe.c
> +++ b/arch/mips/kernel/cpu-probe.c
> @@ -1768,6 +1768,13 @@ static inline void cpu_probe_ingenic(struct
> cpuinfo_mips *c, unsigned int cpu)
>  
>  	switch (c->processor_id & PRID_IMP_MASK) {
>  
> +	/* XBurst®1 with ISA */
> +	case PRID_IMP_XBURST:
> +		c->cputype = CPU_XBURST;
> +		c->writecombine = _CACHE_UNCACHED_ACCELERATED;
> +		__cpu_name[cpu] = "Ingenic XBurst";
> +		break;

What SoCs actually use PRID_IMP_XBURST? The JZ4730?

If it's really used somewhere, you'll also need to add a compatible string for
it in Documentation/devicetree/bindings/mips/cpus.yaml. I guess just
"ingenic,xburst".

Cheers,
-Paul

Re: [PATCH v2 5/9] MIPS: Ingenic: Update Ingenic XBurst implementation IDs

[H. Nikolaus Schaller]

Hi Paul,

> Am 12.11.2026 um 15:03 schrieb Paul Cercueil <paul@crapouillou.net>:
> 
> Hi Nikolaus,
> 
> Le jeudi 12 novembre 2026 à 09:10 +0100, H. Nikolaus Schaller a écrit :
>> Add PRID implementation constants for Ingenic XBurst and XBurst II
>> processors and handle the corresponding implementation IDs in
>> cpu_probe_ingenic().
>> 
>> The PRID table is updated based on Programming Manuals and hardware tests:
>> - jz4780: 0x3ee1024f (confirmed on CI20 board)
>> - x1000:  0x2ed1024f (unconfirmed)
>> - x1600:  0x00d00000 (confirmed on LX16 board)
>> - X1830:  0x00d00100 (unconfirmed)
>> - X2000:  0x00132000 (read out from LX20 board)
>> - X2600:  0x001320xx (confirmed 0x00132000 on LX26 board)
>> 
>> Additionally, clean up extra spaces in the comments for
>> PRID_IMP_XBURST_REV2 and PRID_IMP_XBURST2.
>> 
>> Distinguish XBurst1 implementations with different SIMD ISA revisions
>> and identify XBurst II processors using PRID_IMP_XBURST2.
>> The XBurst II classification follows the Ingenic vendor kernel.
>> 
>> Keep the existing writecombine handling unchanged, since no
>> independent evidence justifies changing the cache attribute for
>> XBurst II.
>> 
>> Public references:
>> - Ingenic Community, public SoC datasheets and programming manuals:
>>   https://github.com/Ingenic-community/datasheets/tree/main/X
>>   Includes the X1600 programming manual (X1600_PM_20220117.pdf)
>>   and documentation for other X-series SoCs, including X1000,
>>   X1830 and X2000.
>> - Ingenic, XBurst1 CPU Core Programming Manual:
>>   https://cdn.hackaday.io/files/1855627939084608/XBurst1_Core_PM.pdf
>>   Documents the XBurst1 core architecture and CP0 configuration.
>> - Ingenic, XBurst Instruction Set Architecture Programming Manual:
>>   https://www.setphaserstostun.org/ci20/X1000_M200_XBurst_ISA_MXU_PM.pdf
>>   Documents the original XBurst SIMD instruction set.
>> - Ingenic, XBurst2 CPU Core Programming Manual:
>>   https://www.manualslib.com/manual/2646351/Ingenic-Xburst-2-Cpu-Core.html
>>   Documents the XBurst2 core architecture.
>> - Ingenic, MIPS-LINUX toolchain R6.0.0 release notes:
>>   https://www.ingenic.com.cn/news-detail/nid-343.html
>>   Distinguishes MSA, MXA and MXU/MXU2 support in the toolchain.
>> - Ingenic, MIPS-LINUX toolchain R6.2.1 release notes:
>>   https://www.ingenic.com.cn/news-detail/nid-348.html
>>   Documents MXU3 support and identifies X2000 as an MSA target.
>> 
>> The public references document the available CPU, SoC and ISA
>> information. The PRID implementation handling follows the Ingenic
>> vendor kernel.
>> 
>> AI assistance: ChatGPT was used to help review the PRID definitions,
>> compare the Ingenic vendor implementation with the upstream code,
>> and draft the commit message with public references. The code changes,
>> hardware observations, and final patch were reviewed by the authors.
>> 
>> Co-developed-by: Paul Boddie <paul@boddie.org.uk>
>> Signed-off-by: Paul Boddie <paul@boddie.org.uk>
>> Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com>
>> ---
>> 
>> Notes:
>>     Changes in V2:
>>     - removed the PRID_IMP_XBURST2_R2 definition and hints for an x2100 as
>>       there is no public reference
>>     - merged into single commit changing the PRID definitions and code
>>     - reviewed details and rewrote commit message
>>     
>>     Open Issue:
>>     Olivier Louvignes <olivier@mgcrea.io> pointed out that he has
>>     simply reused the definition of the X1830 for the X1600. This
>>     sets c->writecombine differently (_CACHE_CACHABLE_WA) from
>>     _CACHE_UNCACHED_ACCELERATED as we do here.
>>     Both settings appear to work but it needs expert comment which
>>     is the right/better one.
>> 
>>  arch/mips/include/asm/cpu.h  | 9 +++++----
>>  arch/mips/kernel/cpu-probe.c | 7 +++++++
>>  2 files changed, 12 insertions(+), 4 deletions(-)
>> 
>> diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
>> index add26f08e8029..79fd9a0747cf2 100644
>> --- a/arch/mips/include/asm/cpu.h
>> +++ b/arch/mips/include/asm/cpu.h
>> @@ -47,7 +47,7 @@
>>  #define PRID_COMP_CAVIUM 0x0d0000
>>  #define PRID_COMP_LOONGSON 0x140000
>>  #define PRID_COMP_INGENIC_13 0x130000 /* X2000, X2100 */
>> -#define PRID_COMP_INGENIC_D0 0xd00000 /* JZ4730, JZ4740, JZ4750,
>> JZ4755, JZ4760, X1830 */
>> +#define PRID_COMP_INGENIC_D0 0xd00000 /* JZ4730, JZ4740, JZ4750,
>> JZ4755, JZ4760, X1830, X1600 */
>>  #define PRID_COMP_INGENIC_D1 0xd10000 /* JZ4770, JZ4775, X1000 */
>>  #define PRID_COMP_INGENIC_E1 0xe10000 /* JZ4780 */
>>  
>> @@ -186,9 +186,10 @@
>>   * These are the PRID's for when 23:16 == PRID_COMP_INGENIC_*
>>   */
>>  
>> -#define PRID_IMP_XBURST_REV1 0x0200 /* XBurst®1 with MXU1.0/MXU1.1 SIMD
>> ISA */
>> -#define PRID_IMP_XBURST_REV2 0x0100 /* XBurst®1 with MXU2.0 SIMD
>> ISA */
>> -#define PRID_IMP_XBURST2 0x2000 /* XBurst®2 with MXU2.1 SIMD
>> ISA */
>> +#define PRID_IMP_XBURST 0x0000 /* XBurst1 */
>> +#define PRID_IMP_XBURST_REV1 0x0200 /* XBurst1 with MXU1.0/MXU1.1 SIMD
>> ISA */
>> +#define PRID_IMP_XBURST_REV2 0x0100 /* XBurst1 with MXU2.0 SIMD ISA */
>> +#define PRID_IMP_XBURST2 0x2000 /* XBurst2 with MXU2.1 SIMD ISA */
>>  
>>  /*
>>   * These are the PRID's for when 23:16 == PRID_COMP_NETLOGIC
>> diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
>> index 489612ed9d498..69b68d00b66f7 100644
>> --- a/arch/mips/kernel/cpu-probe.c
>> +++ b/arch/mips/kernel/cpu-probe.c
>> @@ -1768,6 +1768,13 @@ static inline void cpu_probe_ingenic(struct
>> cpuinfo_mips *c, unsigned int cpu)
>>  
>>   switch (c->processor_id & PRID_IMP_MASK) {
>>  
>> + /* XBurst®1 with ISA */
>> + case PRID_IMP_XBURST:
>> + c->cputype = CPU_XBURST;
>> + c->writecombine = _CACHE_UNCACHED_ACCELERATED;
>> + __cpu_name[cpu] = "Ingenic XBurst";
>> + break;
> 
> What SoCs actually use PRID_IMP_XBURST? The JZ4730?

The x1600 has a PRID of 0x00d00000.

It is a little confusing how these numbers have been assigned over time.

+#define PRID_IMP_XBURST 0x0000 /* XBurst1 */
+#define PRID_IMP_XBURST_REV1 0x0200 /* XBurst1 with MXU1.0/MXU1.1 SIMD ISA */
+#define PRID_IMP_XBURST_REV2 0x0100 /* XBurst1 with MXU2.0 SIMD ISA */

Obviously the x1600 is newer than X1830 (likely PRID_IMP_XBURST_REV2)
or jz4780 and x1000 being PRID_IMP_XBURST_REV1.

So it may or may not be a PRID_IMP_XBURST_REV3? But we don't know.

> 
> If it's really used somewhere, you'll also need to add a compatible string for
> it in Documentation/devicetree/bindings/mips/cpus.yaml. I guess just
> "ingenic,xburst".

Ok, will check.

BR and thanks,
Nikolaus

Re: [PATCH v2 5/9] MIPS: Ingenic: Update Ingenic XBurst implementation IDs

[Paul Cercueil]

Le jeudi 12 novembre 2026 à 16:37 +0100, H. Nikolaus Schaller a écrit :
> Hi Paul,
> 
> > Am 12.11.2026 um 15:03 schrieb Paul Cercueil <paul@crapouillou.net>:
> > 
> > Hi Nikolaus,
> > 
> > Le jeudi 12 novembre 2026 à 09:10 +0100, H. Nikolaus Schaller a écrit :
> > > Add PRID implementation constants for Ingenic XBurst and XBurst II
> > > processors and handle the corresponding implementation IDs in
> > > cpu_probe_ingenic().
> > > 
> > > The PRID table is updated based on Programming Manuals and hardware tests:
> > > - jz4780: 0x3ee1024f (confirmed on CI20 board)
> > > - x1000:  0x2ed1024f (unconfirmed)
> > > - x1600:  0x00d00000 (confirmed on LX16 board)
> > > - X1830:  0x00d00100 (unconfirmed)
> > > - X2000:  0x00132000 (read out from LX20 board)
> > > - X2600:  0x001320xx (confirmed 0x00132000 on LX26 board)
> > > 
> > > Additionally, clean up extra spaces in the comments for
> > > PRID_IMP_XBURST_REV2 and PRID_IMP_XBURST2.
> > > 
> > > Distinguish XBurst1 implementations with different SIMD ISA revisions
> > > and identify XBurst II processors using PRID_IMP_XBURST2.
> > > The XBurst II classification follows the Ingenic vendor kernel.
> > > 
> > > Keep the existing writecombine handling unchanged, since no
> > > independent evidence justifies changing the cache attribute for
> > > XBurst II.
> > > 
> > > Public references:
> > > - Ingenic Community, public SoC datasheets and programming manuals:
> > >   https://github.com/Ingenic-community/datasheets/tree/main/X
> > >   Includes the X1600 programming manual (X1600_PM_20220117.pdf)
> > >   and documentation for other X-series SoCs, including X1000,
> > >   X1830 and X2000.
> > > - Ingenic, XBurst1 CPU Core Programming Manual:
> > >   https://cdn.hackaday.io/files/1855627939084608/XBurst1_Core_PM.pdf
> > >   Documents the XBurst1 core architecture and CP0 configuration.
> > > - Ingenic, XBurst Instruction Set Architecture Programming Manual:
> > >   https://www.setphaserstostun.org/ci20/X1000_M200_XBurst_ISA_MXU_PM.pdf
> > >   Documents the original XBurst SIMD instruction set.
> > > - Ingenic, XBurst2 CPU Core Programming Manual:
> > >   https://www.manualslib.com/manual/2646351/Ingenic-Xburst-2-Cpu-Core.html
> > >   Documents the XBurst2 core architecture.
> > > - Ingenic, MIPS-LINUX toolchain R6.0.0 release notes:
> > >   https://www.ingenic.com.cn/news-detail/nid-343.html
> > >   Distinguishes MSA, MXA and MXU/MXU2 support in the toolchain.
> > > - Ingenic, MIPS-LINUX toolchain R6.2.1 release notes:
> > >   https://www.ingenic.com.cn/news-detail/nid-348.html
> > >   Documents MXU3 support and identifies X2000 as an MSA target.
> > > 
> > > The public references document the available CPU, SoC and ISA
> > > information. The PRID implementation handling follows the Ingenic
> > > vendor kernel.
> > > 
> > > AI assistance: ChatGPT was used to help review the PRID definitions,
> > > compare the Ingenic vendor implementation with the upstream code,
> > > and draft the commit message with public references. The code changes,
> > > hardware observations, and final patch were reviewed by the authors.
> > > 
> > > Co-developed-by: Paul Boddie <paul@boddie.org.uk>
> > > Signed-off-by: Paul Boddie <paul@boddie.org.uk>
> > > Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com>
> > > ---
> > > 
> > > Notes:
> > >     Changes in V2:
> > >     - removed the PRID_IMP_XBURST2_R2 definition and hints for an x2100 as
> > >       there is no public reference
> > >     - merged into single commit changing the PRID definitions and code
> > >     - reviewed details and rewrote commit message
> > >     
> > >     Open Issue:
> > >     Olivier Louvignes <olivier@mgcrea.io> pointed out that he has
> > >     simply reused the definition of the X1830 for the X1600. This
> > >     sets c->writecombine differently (_CACHE_CACHABLE_WA) from
> > >     _CACHE_UNCACHED_ACCELERATED as we do here.
> > >     Both settings appear to work but it needs expert comment which
> > >     is the right/better one.
> > > 
> > >  arch/mips/include/asm/cpu.h  | 9 +++++----
> > >  arch/mips/kernel/cpu-probe.c | 7 +++++++
> > >  2 files changed, 12 insertions(+), 4 deletions(-)
> > > 
> > > diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
> > > index add26f08e8029..79fd9a0747cf2 100644
> > > --- a/arch/mips/include/asm/cpu.h
> > > +++ b/arch/mips/include/asm/cpu.h
> > > @@ -47,7 +47,7 @@
> > >  #define PRID_COMP_CAVIUM 0x0d0000
> > >  #define PRID_COMP_LOONGSON 0x140000
> > >  #define PRID_COMP_INGENIC_13 0x130000 /* X2000, X2100 */
> > > -#define PRID_COMP_INGENIC_D0 0xd00000 /* JZ4730, JZ4740, JZ4750,
> > > JZ4755, JZ4760, X1830 */
> > > +#define PRID_COMP_INGENIC_D0 0xd00000 /* JZ4730, JZ4740, JZ4750,
> > > JZ4755, JZ4760, X1830, X1600 */
> > >  #define PRID_COMP_INGENIC_D1 0xd10000 /* JZ4770, JZ4775, X1000 */
> > >  #define PRID_COMP_INGENIC_E1 0xe10000 /* JZ4780 */
> > >  
> > > @@ -186,9 +186,10 @@
> > >   * These are the PRID's for when 23:16 == PRID_COMP_INGENIC_*
> > >   */
> > >  
> > > -#define PRID_IMP_XBURST_REV1 0x0200 /* XBurst®1 with MXU1.0/MXU1.1 SIMD
> > > ISA */
> > > -#define PRID_IMP_XBURST_REV2 0x0100 /* XBurst®1 with MXU2.0 SIMD
> > > ISA */
> > > -#define PRID_IMP_XBURST2 0x2000 /* XBurst®2 with MXU2.1 SIMD
> > > ISA */
> > > +#define PRID_IMP_XBURST 0x0000 /* XBurst1 */
> > > +#define PRID_IMP_XBURST_REV1 0x0200 /* XBurst1 with MXU1.0/MXU1.1 SIMD
> > > ISA */
> > > +#define PRID_IMP_XBURST_REV2 0x0100 /* XBurst1 with MXU2.0 SIMD ISA */
> > > +#define PRID_IMP_XBURST2 0x2000 /* XBurst2 with MXU2.1 SIMD ISA */
> > >  
> > >  /*
> > >   * These are the PRID's for when 23:16 == PRID_COMP_NETLOGIC
> > > diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
> > > index 489612ed9d498..69b68d00b66f7 100644
> > > --- a/arch/mips/kernel/cpu-probe.c
> > > +++ b/arch/mips/kernel/cpu-probe.c
> > > @@ -1768,6 +1768,13 @@ static inline void cpu_probe_ingenic(struct
> > > cpuinfo_mips *c, unsigned int cpu)
> > >  
> > >   switch (c->processor_id & PRID_IMP_MASK) {
> > >  
> > > + /* XBurst®1 with ISA */
> > > + case PRID_IMP_XBURST:
> > > + c->cputype = CPU_XBURST;
> > > + c->writecombine = _CACHE_UNCACHED_ACCELERATED;
> > > + __cpu_name[cpu] = "Ingenic XBurst";
> > > + break;
> > 
> > What SoCs actually use PRID_IMP_XBURST? The JZ4730?
> 
> The x1600 has a PRID of 0x00d00000.
> 
> It is a little confusing how these numbers have been assigned over time.
> 
> +#define PRID_IMP_XBURST 0x0000 /* XBurst1 */
> +#define PRID_IMP_XBURST_REV1 0x0200 /* XBurst1 with MXU1.0/MXU1.1 SIMD ISA */
> +#define PRID_IMP_XBURST_REV2 0x0100 /* XBurst1 with MXU2.0 SIMD ISA */
> 
> Obviously the x1600 is newer than X1830 (likely PRID_IMP_XBURST_REV2)

Obviously? ;)

I thought that their SoC versions were ordered, with the only exception being
the JZ4725B being newer than the JZ4740 as a sort-of beta JZ4750.

> or jz4780 and x1000 being PRID_IMP_XBURST_REV1.
> 
> So it may or may not be a PRID_IMP_XBURST_REV3? But we don't know.

Can you check if the X1600 supports MXU? A IMP value of 0 might mean a Xburst
CPU with no XMU support, maybe?

> > 
> > If it's really used somewhere, you'll also need to add a compatible string
> > for
> > it in Documentation/devicetree/bindings/mips/cpus.yaml. I guess just
> > "ingenic,xburst".
> 
> Ok, will check.

"ingenic,xburst" if it does not support MXU, I should clarify.

Cheers,
-Paul

[PATCH v2 6/9] MIPS: generic: Add MACH_INGENIC type and compatible for X1600 and X2600

[H. Nikolaus Schaller]

Add support for the Ingenic/Lumissil X1600 and X2600 SoC by introducing
new machine types.

Update the system type string mapping and add the "ingenic,x1600" and
"ingenic,x2600" compatible strings to the DT match table in the generic
Ingenic board support.

Note that we do not separate between e.g. X1600, X1600E, X1600H since
they differ only in built-in memory size which can be handled by the
boot loader.

Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com>
---

Notes:
    Note that there is no bindings document for any of the compatible values
    so we don't add them.

 arch/mips/generic/board-ingenic.c | 8 +++++++-
 arch/mips/include/asm/bootinfo.h  | 2 ++
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/arch/mips/generic/board-ingenic.c b/arch/mips/generic/board-ingenic.c
index 1f4906875e7bc..5840293913977 100644
--- a/arch/mips/generic/board-ingenic.c
+++ b/arch/mips/generic/board-ingenic.c
@@ -24,6 +24,8 @@
 static __init char *ingenic_get_system_type(unsigned long machtype)
 {
 	switch (machtype) {
+	case MACH_INGENIC_X2600:
+		return "X2600";
 	case MACH_INGENIC_X2100:
 		return "X2100";
 	case MACH_INGENIC_X2000H:
@@ -34,6 +36,8 @@ static __init char *ingenic_get_system_type(unsigned long machtype)
 		return "X2000";
 	case MACH_INGENIC_X1830:
 		return "X1830";
+	case MACH_INGENIC_X1600:
+		return "X1600";
 	case MACH_INGENIC_X1000E:
 		return "X1000E";
 	case MACH_INGENIC_X1000:
@@ -146,11 +150,13 @@ static const struct of_device_id ingenic_of_match[] __initconst = {
 	{ .compatible = "ingenic,jz4780", .data = (void *)MACH_INGENIC_JZ4780 },
 	{ .compatible = "ingenic,x1000", .data = (void *)MACH_INGENIC_X1000 },
 	{ .compatible = "ingenic,x1000e", .data = (void *)MACH_INGENIC_X1000E },
+	{ .compatible = "ingenic,x1600", .data = (void *)MACH_INGENIC_X1600 },
 	{ .compatible = "ingenic,x1830", .data = (void *)MACH_INGENIC_X1830 },
 	{ .compatible = "ingenic,x2000", .data = (void *)MACH_INGENIC_X2000 },
 	{ .compatible = "ingenic,x2000e", .data = (void *)MACH_INGENIC_X2000E },
 	{ .compatible = "ingenic,x2000h", .data = (void *)MACH_INGENIC_X2000H },
 	{ .compatible = "ingenic,x2100", .data = (void *)MACH_INGENIC_X2100 },
+	{ .compatible = "ingenic,x2600", .data = (void *)MACH_INGENIC_X2600 },
 	{}
 };
 
@@ -188,7 +194,7 @@ static const struct platform_suspend_ops ingenic_pm_ops = {
 
 static int __init ingenic_pm_init(void)
 {
-	if (boot_cpu_type() == CPU_XBURST) {
+	if (boot_cpu_type() == CPU_XBURST || boot_cpu_type() == CPU_XBURST2) {
 		if (IS_ENABLED(CONFIG_PM_SLEEP))
 			suspend_set_ops(&ingenic_pm_ops);
 		_machine_halt = ingenic_halt;
diff --git a/arch/mips/include/asm/bootinfo.h b/arch/mips/include/asm/bootinfo.h
index 2128ba9033911..f6ae983577f6f 100644
--- a/arch/mips/include/asm/bootinfo.h
+++ b/arch/mips/include/asm/bootinfo.h
@@ -81,11 +81,13 @@ enum ingenic_machine_type {
 	MACH_INGENIC_JZ4780,
 	MACH_INGENIC_X1000,
 	MACH_INGENIC_X1000E,
+	MACH_INGENIC_X1600,
 	MACH_INGENIC_X1830,
 	MACH_INGENIC_X2000,
 	MACH_INGENIC_X2000E,
 	MACH_INGENIC_X2000H,
 	MACH_INGENIC_X2100,
+	MACH_INGENIC_X2600,
 };
 
 extern char *system_type;
-- 
2.56.0

Re: [PATCH v2 6/9] MIPS: generic: Add MACH_INGENIC type and compatible for X1600 and X2600

[Paul Cercueil]

Hi Nikolaus,

Le jeudi 12 novembre 2026 à 09:10 +0100, H. Nikolaus Schaller a écrit :
> Add support for the Ingenic/Lumissil X1600 and X2600 SoC by introducing
> new machine types.
> 
> Update the system type string mapping and add the "ingenic,x1600" and
> "ingenic,x2600" compatible strings to the DT match table in the generic
> Ingenic board support.
> 
> Note that we do not separate between e.g. X1600, X1600E, X1600H since
> they differ only in built-in memory size which can be handled by the
> boot loader.
> 
> Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com>
> ---
> 
> Notes:
>     Note that there is no bindings document for any of the compatible values
>     so we don't add them.
> 
>  arch/mips/generic/board-ingenic.c | 8 +++++++-
>  arch/mips/include/asm/bootinfo.h  | 2 ++
>  2 files changed, 9 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/mips/generic/board-ingenic.c b/arch/mips/generic/board-
> ingenic.c
> index 1f4906875e7bc..5840293913977 100644
> --- a/arch/mips/generic/board-ingenic.c
> +++ b/arch/mips/generic/board-ingenic.c
> @@ -24,6 +24,8 @@
>  static __init char *ingenic_get_system_type(unsigned long machtype)
>  {
>  	switch (machtype) {
> +	case MACH_INGENIC_X2600:
> +		return "X2600";
>  	case MACH_INGENIC_X2100:
>  		return "X2100";
>  	case MACH_INGENIC_X2000H:
> @@ -34,6 +36,8 @@ static __init char *ingenic_get_system_type(unsigned long
> machtype)
>  		return "X2000";
>  	case MACH_INGENIC_X1830:
>  		return "X1830";
> +	case MACH_INGENIC_X1600:
> +		return "X1600";
>  	case MACH_INGENIC_X1000E:
>  		return "X1000E";
>  	case MACH_INGENIC_X1000:
> @@ -146,11 +150,13 @@ static const struct of_device_id ingenic_of_match[]
> __initconst = {
>  	{ .compatible = "ingenic,jz4780", .data = (void *)MACH_INGENIC_JZ4780
> },
>  	{ .compatible = "ingenic,x1000", .data = (void *)MACH_INGENIC_X1000
> },
>  	{ .compatible = "ingenic,x1000e", .data = (void *)MACH_INGENIC_X1000E
> },
> +	{ .compatible = "ingenic,x1600", .data = (void *)MACH_INGENIC_X1600
> },
>  	{ .compatible = "ingenic,x1830", .data = (void *)MACH_INGENIC_X1830
> },
>  	{ .compatible = "ingenic,x2000", .data = (void *)MACH_INGENIC_X2000
> },
>  	{ .compatible = "ingenic,x2000e", .data = (void *)MACH_INGENIC_X2000E
> },
>  	{ .compatible = "ingenic,x2000h", .data = (void *)MACH_INGENIC_X2000H
> },
>  	{ .compatible = "ingenic,x2100", .data = (void *)MACH_INGENIC_X2100
> },
> +	{ .compatible = "ingenic,x2600", .data = (void *)MACH_INGENIC_X2600
> },

I was going to say that if you add compatibles here you'll also need to add them
to the bindings documentation, but it seems we don't have one?

We have Documentation/devicetree/bindings/mips/ingenic/devices.yaml for boards
but most SoCs listed here don't have an accompanying board.

Given that it's not your mess I'm OK with the patch, but we should really fix
this at some point.

Cheers,
-Paul

>  	{}
>  };
>  
> @@ -188,7 +194,7 @@ static const struct platform_suspend_ops ingenic_pm_ops =
> {
>  
>  static int __init ingenic_pm_init(void)
>  {
> -	if (boot_cpu_type() == CPU_XBURST) {
> +	if (boot_cpu_type() == CPU_XBURST || boot_cpu_type() == CPU_XBURST2)
> {
>  		if (IS_ENABLED(CONFIG_PM_SLEEP))
>  			suspend_set_ops(&ingenic_pm_ops);
>  		_machine_halt = ingenic_halt;
> diff --git a/arch/mips/include/asm/bootinfo.h
> b/arch/mips/include/asm/bootinfo.h
> index 2128ba9033911..f6ae983577f6f 100644
> --- a/arch/mips/include/asm/bootinfo.h
> +++ b/arch/mips/include/asm/bootinfo.h
> @@ -81,11 +81,13 @@ enum ingenic_machine_type {
>  	MACH_INGENIC_JZ4780,
>  	MACH_INGENIC_X1000,
>  	MACH_INGENIC_X1000E,
> +	MACH_INGENIC_X1600,
>  	MACH_INGENIC_X1830,
>  	MACH_INGENIC_X2000,
>  	MACH_INGENIC_X2000E,
>  	MACH_INGENIC_X2000H,
>  	MACH_INGENIC_X2100,
> +	MACH_INGENIC_X2600,
>  };
>  
>  extern char *system_type;

Re: [PATCH v2 6/9] MIPS: generic: Add MACH_INGENIC type and compatible for X1600 and X2600

[H. Nikolaus Schaller]

Hi Paul,


> Am 12.11.2026 um 15:09 schrieb Paul Cercueil <paul@crapouillou.net>:
> 
> Hi Nikolaus,
> 
> Le jeudi 12 novembre 2026 à 09:10 +0100, H. Nikolaus Schaller a écrit :
>> Add support for the Ingenic/Lumissil X1600 and X2600 SoC by introducing
>> new machine types.
>> 
>> Update the system type string mapping and add the "ingenic,x1600" and
>> "ingenic,x2600" compatible strings to the DT match table in the generic
>> Ingenic board support.
>> 
>> Note that we do not separate between e.g. X1600, X1600E, X1600H since
>> they differ only in built-in memory size which can be handled by the
>> boot loader.
>> 
>> Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com>
>> ---
>> 
>> Notes:
>>     Note that there is no bindings document for any of the compatible values
>>     so we don't add them.
>> 
>>  arch/mips/generic/board-ingenic.c | 8 +++++++-
>>  arch/mips/include/asm/bootinfo.h  | 2 ++
>>  2 files changed, 9 insertions(+), 1 deletion(-)
>> 
>> diff --git a/arch/mips/generic/board-ingenic.c b/arch/mips/generic/board-
>> ingenic.c
>> index 1f4906875e7bc..5840293913977 100644
>> --- a/arch/mips/generic/board-ingenic.c
>> +++ b/arch/mips/generic/board-ingenic.c
>> @@ -24,6 +24,8 @@
>>  static __init char *ingenic_get_system_type(unsigned long machtype)
>>  {
>>   switch (machtype) {
>> + case MACH_INGENIC_X2600:
>> + return "X2600";
>>   case MACH_INGENIC_X2100:
>>   return "X2100";
>>   case MACH_INGENIC_X2000H:
>> @@ -34,6 +36,8 @@ static __init char *ingenic_get_system_type(unsigned long
>> machtype)
>>   return "X2000";
>>   case MACH_INGENIC_X1830:
>>   return "X1830";
>> + case MACH_INGENIC_X1600:
>> + return "X1600";
>>   case MACH_INGENIC_X1000E:
>>   return "X1000E";
>>   case MACH_INGENIC_X1000:
>> @@ -146,11 +150,13 @@ static const struct of_device_id ingenic_of_match[]
>> __initconst = {
>>   { .compatible = "ingenic,jz4780", .data = (void *)MACH_INGENIC_JZ4780
>> },
>>   { .compatible = "ingenic,x1000", .data = (void *)MACH_INGENIC_X1000
>> },
>>   { .compatible = "ingenic,x1000e", .data = (void *)MACH_INGENIC_X1000E
>> },
>> + { .compatible = "ingenic,x1600", .data = (void *)MACH_INGENIC_X1600
>> },
>>   { .compatible = "ingenic,x1830", .data = (void *)MACH_INGENIC_X1830
>> },
>>   { .compatible = "ingenic,x2000", .data = (void *)MACH_INGENIC_X2000
>> },
>>   { .compatible = "ingenic,x2000e", .data = (void *)MACH_INGENIC_X2000E
>> },
>>   { .compatible = "ingenic,x2000h", .data = (void *)MACH_INGENIC_X2000H
>> },
>>   { .compatible = "ingenic,x2100", .data = (void *)MACH_INGENIC_X2100
>> },
>> + { .compatible = "ingenic,x2600", .data = (void *)MACH_INGENIC_X2600
>> },
> 
> I was going to say that if you add compatibles here you'll also need to add them
> to the bindings documentation, but it seems we don't have one?

Indeed... Checkpatch even reported about.

I added that to the Notes section of the commit that we have no bindings doc.

> 
> We have Documentation/devicetree/bindings/mips/ingenic/devices.yaml for boards
> but most SoCs listed here don't have an accompanying board.
> 
> Given that it's not your mess I'm OK with the patch, but we should really fix
> this at some point.

Agreed. Should not be too complex, I guess.

BR and thanks,
Nikolaus

> 
> Cheers,
> -Paul
> 
>>   {}
>>  };
>>  
>> @@ -188,7 +194,7 @@ static const struct platform_suspend_ops ingenic_pm_ops =
>> {
>>  
>>  static int __init ingenic_pm_init(void)
>>  {
>> - if (boot_cpu_type() == CPU_XBURST) {
>> + if (boot_cpu_type() == CPU_XBURST || boot_cpu_type() == CPU_XBURST2)
>> {
>>   if (IS_ENABLED(CONFIG_PM_SLEEP))
>>   suspend_set_ops(&ingenic_pm_ops);
>>   _machine_halt = ingenic_halt;
>> diff --git a/arch/mips/include/asm/bootinfo.h
>> b/arch/mips/include/asm/bootinfo.h
>> index 2128ba9033911..f6ae983577f6f 100644
>> --- a/arch/mips/include/asm/bootinfo.h
>> +++ b/arch/mips/include/asm/bootinfo.h
>> @@ -81,11 +81,13 @@ enum ingenic_machine_type {
>>   MACH_INGENIC_JZ4780,
>>   MACH_INGENIC_X1000,
>>   MACH_INGENIC_X1000E,
>> + MACH_INGENIC_X1600,
>>   MACH_INGENIC_X1830,
>>   MACH_INGENIC_X2000,
>>   MACH_INGENIC_X2000E,
>>   MACH_INGENIC_X2000H,
>>   MACH_INGENIC_X2100,
>> + MACH_INGENIC_X2600,
>>  };
>>  
>>  extern char *system_type;

[PATCH v2 7/9] MIPS: Ingenic: Expand Kconfig for X1600, X2000, and X2600 SoCs

[H. Nikolaus Schaller]

Expand MACH_INGENIC_GENERIC to select all existing and newly added
machine variants (including JZ4750/55/60/75, X1500, X1600, X2000,
X2100, and X2600).

Introduce individual Kconfig blocks for the following SoCs:
- MACH_X1600: Selects MIPS32_R2 and HIGHMEM.
- MACH_X2000 / MACH_X2600: Selects MIPS32_R5, SMP support, broadcast
  clockevents, O32 FP64 support, and weak ordering optimizations.

In parts developed by Reimu NotMoe <reimu@sudomaker.com>

Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com>
---
 arch/mips/ingenic/Kconfig | 38 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 38 insertions(+)

diff --git a/arch/mips/ingenic/Kconfig b/arch/mips/ingenic/Kconfig
index f595b339a4b84..5d351b42bbc9b 100644
--- a/arch/mips/ingenic/Kconfig
+++ b/arch/mips/ingenic/Kconfig
@@ -5,10 +5,19 @@ config MACH_INGENIC_GENERIC
 	select MACH_INGENIC
 	select MACH_JZ4740
 	select MACH_JZ4725B
+	select MACH_JZ4750
+	select MACH_JZ4755
+	select MACH_JZ4760
 	select MACH_JZ4770
+	select MACH_JZ4775
 	select MACH_JZ4780
 	select MACH_X1000
+	select MACH_X1500
+	select MACH_X1600
 	select MACH_X1830
+	select MACH_X2000
+	select MACH_X2100
+	select MACH_X2600
 
 choice
 	prompt "Machine type"
@@ -62,8 +71,10 @@ config MACH_JZ4770
 config MACH_JZ4780
 	bool
 	select MIPS_CPU_SCACHE
+	select GENERIC_CLOCKEVENTS_BROADCAST if SMP
 	select SYS_HAS_CPU_MIPS32_R2
 	select SYS_SUPPORTS_HIGHMEM
+	select SYS_SUPPORTS_SMP
 
 config MACH_X1000
 	bool
@@ -71,8 +82,35 @@ config MACH_X1000
 	select SYS_HAS_CPU_MIPS32_R2
 	select SYS_SUPPORTS_HIGHMEM
 
+config MACH_X1600
+	bool
+	select SYS_HAS_CPU_MIPS32_R2
+	select SYS_SUPPORTS_HIGHMEM
+
 config MACH_X1830
 	bool
 	select MIPS_CPU_SCACHE
 	select SYS_HAS_CPU_MIPS32_R2
 	select SYS_SUPPORTS_HIGHMEM
+
+config MACH_X2000
+	bool
+	select MIPS_CPU_SCACHE
+	select GENERIC_CLOCKEVENTS_BROADCAST if SMP
+	select SYS_HAS_CPU_MIPS32_R5
+	select SYS_SUPPORTS_HIGHMEM
+	select SYS_SUPPORTS_SMP
+	select MIPS_O32_FP64_SUPPORT
+	select WEAK_ORDERING
+	select WEAK_REORDERING_BEYOND_LLSC
+
+config MACH_X2600
+	bool
+	select MIPS_CPU_SCACHE
+	select GENERIC_CLOCKEVENTS_BROADCAST if SMP
+	select SYS_HAS_CPU_MIPS32_R5
+	select SYS_SUPPORTS_HIGHMEM
+	select SYS_SUPPORTS_SMP
+	select MIPS_O32_FP64_SUPPORT
+	select WEAK_ORDERING
+	select WEAK_REORDERING_BEYOND_LLSC
-- 
2.56.0

Re: [PATCH v2 7/9] MIPS: Ingenic: Expand Kconfig for X1600, X2000, and X2600 SoCs

[Paul Cercueil]

Le jeudi 12 novembre 2026 à 09:10 +0100, H. Nikolaus Schaller a écrit :
> Expand MACH_INGENIC_GENERIC to select all existing and newly added
> machine variants (including JZ4750/55/60/75, X1500, X1600, X2000,
> X2100, and X2600).
> 
> Introduce individual Kconfig blocks for the following SoCs:
> - MACH_X1600: Selects MIPS32_R2 and HIGHMEM.
> - MACH_X2000 / MACH_X2600: Selects MIPS32_R5, SMP support, broadcast
>   clockevents, O32 FP64 support, and weak ordering optimizations.
> 
> In parts developed by Reimu NotMoe <reimu@sudomaker.com>

Co-developed-by? (+ his Sob)

> Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com>
> ---
>  arch/mips/ingenic/Kconfig | 38 ++++++++++++++++++++++++++++++++++++++
>  1 file changed, 38 insertions(+)
> 
> diff --git a/arch/mips/ingenic/Kconfig b/arch/mips/ingenic/Kconfig
> index f595b339a4b84..5d351b42bbc9b 100644
> --- a/arch/mips/ingenic/Kconfig
> +++ b/arch/mips/ingenic/Kconfig
> @@ -5,10 +5,19 @@ config MACH_INGENIC_GENERIC
>  	select MACH_INGENIC
>  	select MACH_JZ4740
>  	select MACH_JZ4725B
> +	select MACH_JZ4750
> +	select MACH_JZ4755
> +	select MACH_JZ4760
>  	select MACH_JZ4770
> +	select MACH_JZ4775
>  	select MACH_JZ4780
>  	select MACH_X1000
> +	select MACH_X1500

You select MACH_X1500 but there's no CONFIG_MACH_X1500 symbol. No entry in enum
ingenic_machine_type either, or compatible string for it.

Your patch didn't add a CONFIG_MACH_X2100 either.

> +	select MACH_X1600
>  	select MACH_X1830
> +	select MACH_X2000
> +	select MACH_X2100
> +	select MACH_X2600
>  
>  choice
>  	prompt "Machine type"
> @@ -62,8 +71,10 @@ config MACH_JZ4770
>  config MACH_JZ4780
>  	bool
>  	select MIPS_CPU_SCACHE
> +	select GENERIC_CLOCKEVENTS_BROADCAST if SMP
>  	select SYS_HAS_CPU_MIPS32_R2
>  	select SYS_SUPPORTS_HIGHMEM
> +	select SYS_SUPPORTS_SMP
>  
>  config MACH_X1000
>  	bool
> @@ -71,8 +82,35 @@ config MACH_X1000
>  	select SYS_HAS_CPU_MIPS32_R2
>  	select SYS_SUPPORTS_HIGHMEM
>  
> +config MACH_X1600
> +	bool
> +	select SYS_HAS_CPU_MIPS32_R2
> +	select SYS_SUPPORTS_HIGHMEM
> +
>  config MACH_X1830
>  	bool
>  	select MIPS_CPU_SCACHE
>  	select SYS_HAS_CPU_MIPS32_R2
>  	select SYS_SUPPORTS_HIGHMEM
> +
> +config MACH_X2000
> +	bool
> +	select MIPS_CPU_SCACHE
> +	select GENERIC_CLOCKEVENTS_BROADCAST if SMP
> +	select SYS_HAS_CPU_MIPS32_R5
> +	select SYS_SUPPORTS_HIGHMEM
> +	select SYS_SUPPORTS_SMP
> +	select MIPS_O32_FP64_SUPPORT

I know MIPS_O32_FP64_SUPPORT was supported on the JZ4770, and most likely on the
JZ4760 too (the first one with a FPU AFAIK). So this could probably be moved to
CONFIG_MACH_INGENIC.

Cheers,
-Paul

> +	select WEAK_ORDERING
> +	select WEAK_REORDERING_BEYOND_LLSC
> +
> +config MACH_X2600
> +	bool
> +	select MIPS_CPU_SCACHE
> +	select GENERIC_CLOCKEVENTS_BROADCAST if SMP
> +	select SYS_HAS_CPU_MIPS32_R5
> +	select SYS_SUPPORTS_HIGHMEM
> +	select SYS_SUPPORTS_SMP
> +	select MIPS_O32_FP64_SUPPORT
> +	select WEAK_ORDERING
> +	select WEAK_REORDERING_BEYOND_LLSC

Re: [PATCH v2 7/9] MIPS: Ingenic: Expand Kconfig for X1600, X2000, and X2600 SoCs

[H. Nikolaus Schaller]

> Am 12.11.2026 um 15:16 schrieb Paul Cercueil <paul@crapouillou.net>:
> 
> Le jeudi 12 novembre 2026 à 09:10 +0100, H. Nikolaus Schaller a écrit :
>> Expand MACH_INGENIC_GENERIC to select all existing and newly added
>> machine variants (including JZ4750/55/60/75, X1500, X1600, X2000,
>> X2100, and X2600).
>> 
>> Introduce individual Kconfig blocks for the following SoCs:
>> - MACH_X1600: Selects MIPS32_R2 and HIGHMEM.
>> - MACH_X2000 / MACH_X2600: Selects MIPS32_R5, SMP support, broadcast
>>   clockevents, O32 FP64 support, and weak ordering optimizations.
>> 
>> In parts developed by Reimu NotMoe <reimu@sudomaker.com>
> 
> Co-developed-by? (+ his Sob)

I have to check what he really has developed. I think we did take this from
his github tree (https://github.com/Ingenic-community/linux/tree/v6.1.y) but
were never in contact with him. So I am not sure if we can get a SoB:.

> 
>> Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com>
>> ---
>>  arch/mips/ingenic/Kconfig | 38 ++++++++++++++++++++++++++++++++++++++
>>  1 file changed, 38 insertions(+)
>> 
>> diff --git a/arch/mips/ingenic/Kconfig b/arch/mips/ingenic/Kconfig
>> index f595b339a4b84..5d351b42bbc9b 100644
>> --- a/arch/mips/ingenic/Kconfig
>> +++ b/arch/mips/ingenic/Kconfig
>> @@ -5,10 +5,19 @@ config MACH_INGENIC_GENERIC
>>   select MACH_INGENIC
>>   select MACH_JZ4740
>>   select MACH_JZ4725B
>> + select MACH_JZ4750
>> + select MACH_JZ4755
>> + select MACH_JZ4760
>>   select MACH_JZ4770
>> + select MACH_JZ4775
>>   select MACH_JZ4780
>>   select MACH_X1000
>> + select MACH_X1500
> 
> You select MACH_X1500 but there's no CONFIG_MACH_X1500 symbol. No entry in enum
> ingenic_machine_type either, or compatible string for it.
> 
> Your patch didn't add a CONFIG_MACH_X2100 either.

Ok, that may be from taking the Reimu NotMoe patch without cross-checking.

Will be removed in V3.

> 
>> + select MACH_X1600
>>   select MACH_X1830
>> + select MACH_X2000
>> + select MACH_X2100
>> + select MACH_X2600
>>  
>>  choice
>>   prompt "Machine type"
>> @@ -62,8 +71,10 @@ config MACH_JZ4770
>>  config MACH_JZ4780
>>   bool
>>   select MIPS_CPU_SCACHE
>> + select GENERIC_CLOCKEVENTS_BROADCAST if SMP
>>   select SYS_HAS_CPU_MIPS32_R2
>>   select SYS_SUPPORTS_HIGHMEM
>> + select SYS_SUPPORTS_SMP
>>  
>>  config MACH_X1000
>>   bool
>> @@ -71,8 +82,35 @@ config MACH_X1000
>>   select SYS_HAS_CPU_MIPS32_R2
>>   select SYS_SUPPORTS_HIGHMEM
>>  
>> +config MACH_X1600
>> + bool
>> + select SYS_HAS_CPU_MIPS32_R2
>> + select SYS_SUPPORTS_HIGHMEM
>> +
>>  config MACH_X1830
>>   bool
>>   select MIPS_CPU_SCACHE
>>   select SYS_HAS_CPU_MIPS32_R2
>>   select SYS_SUPPORTS_HIGHMEM
>> +
>> +config MACH_X2000
>> + bool
>> + select MIPS_CPU_SCACHE
>> + select GENERIC_CLOCKEVENTS_BROADCAST if SMP
>> + select SYS_HAS_CPU_MIPS32_R5
>> + select SYS_SUPPORTS_HIGHMEM
>> + select SYS_SUPPORTS_SMP
>> + select MIPS_O32_FP64_SUPPORT
> 
> I know MIPS_O32_FP64_SUPPORT was supported on the JZ4770, and most likely on the
> JZ4760 too (the first one with a FPU AFAIK). So this could probably be moved to
> CONFIG_MACH_INGENIC.

That should be clearly checked. If I find a little time I can add it
or it can be done later.

BR and thanks,
Nikolaus

> 
> Cheers,
> -Paul
> 
>> + select WEAK_ORDERING
>> + select WEAK_REORDERING_BEYOND_LLSC
>> +
>> +config MACH_X2600
>> + bool
>> + select MIPS_CPU_SCACHE
>> + select GENERIC_CLOCKEVENTS_BROADCAST if SMP
>> + select SYS_HAS_CPU_MIPS32_R5
>> + select SYS_SUPPORTS_HIGHMEM
>> + select SYS_SUPPORTS_SMP
>> + select MIPS_O32_FP64_SUPPORT
>> + select WEAK_ORDERING
>> + select WEAK_REORDERING_BEYOND_LLSC

[PATCH v2 8/9] MIPS: Ingenic: Expand Kconfig by MACH_JZ4730

[H. Nikolaus Schaller]

The jz4730 is a single core SoC by Ingenic with peripherals
like LCD controller, NAND controller, Timers, PWM, GPIOs

Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com>
---
 arch/mips/ingenic/Kconfig | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/mips/ingenic/Kconfig b/arch/mips/ingenic/Kconfig
index 5d351b42bbc9b..62b494ad77a61 100644
--- a/arch/mips/ingenic/Kconfig
+++ b/arch/mips/ingenic/Kconfig
@@ -3,6 +3,7 @@
 config MACH_INGENIC_GENERIC
 	bool
 	select MACH_INGENIC
+	select MACH_JZ4730
 	select MACH_JZ4740
 	select MACH_JZ4725B
 	select MACH_JZ4750
@@ -58,6 +59,10 @@ config MACH_JZ4725B
 	bool
 	select SYS_HAS_CPU_MIPS32_R1
 
+config MACH_JZ4730
+	bool
+	select SYS_HAS_CPU_MIPS32_R1
+
 config MACH_JZ4740
 	bool
 	select SYS_HAS_CPU_MIPS32_R1
-- 
2.56.0

[PATCH v2 9/9] MIPS: Ingenic: Add Platform makefile and load addresses for X1600, X2000, X2600

[H. Nikolaus Schaller]

Introduce the arch/mips/ingenic/Platform file to define the default
kernel load addresses for X1600, X2000 and X2600 SoCs.

All platforms are configured to use 0xffffffff80010000.

Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com>
---
 arch/mips/ingenic/Platform | 3 +++
 1 file changed, 3 insertions(+)
 create mode 100644 arch/mips/ingenic/Platform

diff --git a/arch/mips/ingenic/Platform b/arch/mips/ingenic/Platform
new file mode 100644
index 0000000000000..bffb4529d799d
--- /dev/null
+++ b/arch/mips/ingenic/Platform
@@ -0,0 +1,3 @@
+load-$(CONFIG_MACH_X1600)	:= 0xffffffff80010000
+load-$(CONFIG_MACH_X2000)	:= 0xffffffff80010000
+load-$(CONFIG_MACH_X2600)	:= 0xffffffff80010000
-- 
2.56.0