* [PATCH v10 1/4] soc: mediatek: mmsys: add support for MDP
[not found] <20211202061322.19917-1-moudy.ho@mediatek.com>
@ 2021-12-02 6:13 ` Moudy Ho
2021-12-02 6:13 ` [PATCH v10 2/4] soc: mediatek: mmsys: add support for ISP control Moudy Ho
` (2 subsequent siblings)
3 siblings, 0 replies; 6+ messages in thread
From: Moudy Ho @ 2021-12-02 6:13 UTC (permalink / raw)
To: Mauro Carvalho Chehab, Rob Herring, Matthias Brugger,
Hans Verkuil, Jernej Skrabec
Cc: Chun-Kuang Hu, Geert Uytterhoeven, Rob Landley, Laurent Pinchart,
linux-media, devicetree, linux-arm-kernel, linux-mediatek,
linux-kernel, Alexandre Courbot, tfiga, drinkcat, pihsun, hsinyi,
AngeloGioacchino Del Regno, Maoguang Meng, daoyuan huang,
Ping-Hsun Wu, menghui.lin, sj.huang, allen-kh.cheng, randy.wu,
moudy.ho, jason-jh.lin, roy-cw.yeh, river.cheng, srv_heupstream
For the purpose of module independence, related settings should be moved
from MDP to the corresponding driver.
This patch adds more 8183 MDP settings and interface. and MDP
related settings must be set via CMDQ to avoid frame unsynchronized.
Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/soc/mediatek/Kconfig | 1 +
drivers/soc/mediatek/mt8183-mmsys.h | 268 +++++++++++++++++++++++++
drivers/soc/mediatek/mtk-mmsys.c | 56 ++++++
drivers/soc/mediatek/mtk-mmsys.h | 2 +
include/linux/soc/mediatek/mtk-mmsys.h | 56 ++++++
5 files changed, 383 insertions(+)
diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig
index fdd8bc08569e..172bc7828aca 100644
--- a/drivers/soc/mediatek/Kconfig
+++ b/drivers/soc/mediatek/Kconfig
@@ -69,6 +69,7 @@ config MTK_MMSYS
bool "MediaTek MMSYS Support"
default ARCH_MEDIATEK
depends on HAS_IOMEM
+ select MTK_CMDQ
help
Say yes here to add support for the MediaTek Multimedia
Subsystem (MMSYS).
diff --git a/drivers/soc/mediatek/mt8183-mmsys.h b/drivers/soc/mediatek/mt8183-mmsys.h
index 9dee485807c9..48865973314d 100644
--- a/drivers/soc/mediatek/mt8183-mmsys.h
+++ b/drivers/soc/mediatek/mt8183-mmsys.h
@@ -12,6 +12,25 @@
#define MT8183_DISP_DPI0_SEL_IN 0xf30
#define MT8183_DISP_RDMA0_SOUT_SEL_IN 0xf50
#define MT8183_DISP_RDMA1_SOUT_SEL_IN 0xf54
+#define MT8183_MDP_ISP_MOUT_EN 0xf80
+#define MT8183_MDP_RDMA0_MOUT_EN 0xf84
+#define MT8183_MDP_PRZ0_MOUT_EN 0xf8c
+#define MT8183_MDP_PRZ1_MOUT_EN 0xf90
+#define MT8183_MDP_COLOR_MOUT_EN 0xf94
+#define MT8183_MDP_IPU_MOUT_EN 0xf98
+#define MT8183_MDP_PATH0_SOUT_SEL 0xfa8
+#define MT8183_MDP_PATH1_SOUT_SEL 0xfac
+#define MT8183_MDP_PRZ0_SEL_IN 0xfc0
+#define MT8183_MDP_PRZ1_SEL_IN 0xfc4
+#define MT8183_MDP_TDSHP_SEL_IN 0xfc8
+#define MT8183_MDP_WROT0_SEL_IN 0xfd0
+#define MT8183_MDP_WDMA_SEL_IN 0xfd4
+#define MT8183_MDP_PATH0_SEL_IN 0xfe0
+#define MT8183_MDP_PATH1_SEL_IN 0xfe4
+#define MT8183_MDP_AAL_MOUT_EN 0xfe8
+#define MT8183_MDP_AAL_SEL_IN 0xfec
+#define MT8183_MDP_CCORR_SEL_IN 0xff0
+#define MT8183_MDP_CCORR_SOUT_SEL 0xff4
#define MT8183_OVL0_MOUT_EN_OVL0_2L BIT(4)
#define MT8183_OVL0_2L_MOUT_EN_DISP_PATH0 BIT(0)
@@ -24,6 +43,55 @@
#define MT8183_DPI0_SEL_IN_RDMA1 0x2
#define MT8183_RDMA0_SOUT_COLOR0 0x1
#define MT8183_RDMA1_SOUT_DSI0 0x1
+#define MT8183_MDP_ISP_MOUT_EN_CCORR0 BIT(0)
+#define MT8183_MDP_ISP_MOUT_EN_RSZ1 BIT(1)
+#define MT8183_MDP_ISP_MOUT_EN_AAL0 BIT(2)
+#define MT8183_MDP_IPU_MOUT_EN_CCORR0 BIT(0)
+#define MT8183_MDP_IPU_MOUT_EN_RSZ1 BIT(1)
+#define MT8183_MDP_IPU_MOUT_EN_AAL0 BIT(2)
+#define MT8183_MDP_RDMA0_MOUT_EN_CCORR0 BIT(0)
+#define MT8183_MDP_RDMA0_MOUT_EN_RSZ1 BIT(1)
+#define MT8183_MDP_RDMA0_MOUT_EN_PATH0_OUT BIT(2)
+#define MT8183_MDP_RDMA0_MOUT_EN_AAL0 BIT(3)
+#define MT8183_MDP_AAL_MOUT_EN_CCORR0 BIT(0)
+#define MT8183_MDP_AAL_MOUT_EN_RSZ1 BIT(1)
+#define MT8183_MDP_AAL_MOUT_EN_RSZ0 BIT(2)
+#define MT8183_MDP_PRZ0_MOUT_EN_PATH0_OUT BIT(0)
+#define MT8183_MDP_PRZ0_MOUT_EN_TDSHP0 BIT(1)
+#define MT8183_MDP_PRZ1_MOUT_EN_PATH0_OUT BIT(0)
+#define MT8183_MDP_PRZ1_MOUT_EN_TDSHP0 BIT(1)
+#define MT8183_MDP_PRZ1_MOUT_EN_PATH1_OUT BIT(2)
+#define MT8183_MDP_PRZ1_MOUT_EN_COLOR0 BIT(4)
+#define MT8183_MDP_COLOR_MOUT_EN_PATH0_OUT BIT(0)
+#define MT8183_MDP_COLOR_MOUT_EN_PATH1_OUT BIT(1)
+#define MT8183_MDP_AAL_SEL_IN_CAMIN 0
+#define MT8183_MDP_AAL_SEL_IN_RDMA0 1
+#define MT8183_MDP_AAL_SEL_IN_CAMIN2 2
+#define MT8183_MDP_AAL_SEL_IN_CCORR0 3
+#define MT8183_MDP_CCORR_SEL_IN_CAMIN 0
+#define MT8183_MDP_CCORR_SEL_IN_RDMA0 1
+#define MT8183_MDP_CCORR_SEL_IN_CAMIN2 3
+#define MT8183_MDP_CCORR_SEL_IN_AAL0 4
+#define MT8183_MDP_PRZ0_SEL_IN_AAL0 0
+#define MT8183_MDP_PRZ0_SEL_IN_CCORR0 1
+#define MT8183_MDP_PRZ1_SEL_IN_CAMIN 0
+#define MT8183_MDP_PRZ1_SEL_IN_RDMA0 1
+#define MT8183_MDP_PRZ1_SEL_IN_CAMIN2 4
+#define MT8183_MDP_PRZ1_SEL_IN_AAL0 5
+#define MT8183_MDP_TDSHP_SEL_IN_RSZ0 0
+#define MT8183_MDP_TDSHP_SEL_IN_RSZ1 1
+#define MT8183_MDP_PATH0_SEL_IN_RSZ0 0
+#define MT8183_MDP_PATH0_SEL_IN_RSZ1 1
+#define MT8183_MDP_PATH0_SEL_IN_COLOR0 2
+#define MT8183_MDP_PATH0_SEL_IN_RDMA0 3
+#define MT8183_MDP_PATH1_SEL_IN_RSZ1 0
+#define MT8183_MDP_PATH1_SEL_IN_COLOR0 1
+#define MT8183_MDP_WROT0_SEL_IN_PATH0_OUT 0
+#define MT8183_MDP_WDMA_SEL_IN_PATH1_OUT 0
+#define MT8183_MDP_CCORR_SOUT_SEL_AAL0 0
+#define MT8183_MDP_CCORR_SOUT_SEL_RSZ0 1
+#define MT8183_MDP_PATH0_SOUT_SEL_WROT0 0
+#define MT8183_MDP_PATH1_SOUT_SEL_WDMA 0
static const struct mtk_mmsys_routes mmsys_mt8183_routing_table[] = {
{
@@ -57,5 +125,205 @@ static const struct mtk_mmsys_routes mmsys_mt8183_routing_table[] = {
}
};
+static const struct mtk_mmsys_routes mmsys_mt8183_mdp_routing_table[] = {
+ {
+ MDP_COMP_CAMIN, MDP_COMP_CCORR0,
+ MT8183_MDP_ISP_MOUT_EN, MT8183_MDP_ISP_MOUT_EN_CCORR0,
+ MT8183_MDP_ISP_MOUT_EN_CCORR0
+ }, {
+ MDP_COMP_CAMIN, MDP_COMP_RSZ1,
+ MT8183_MDP_ISP_MOUT_EN, MT8183_MDP_ISP_MOUT_EN_RSZ1,
+ MT8183_MDP_ISP_MOUT_EN_RSZ1
+ }, {
+ MDP_COMP_CAMIN, MDP_COMP_AAL0,
+ MT8183_MDP_ISP_MOUT_EN, MT8183_MDP_ISP_MOUT_EN_AAL0,
+ MT8183_MDP_ISP_MOUT_EN_AAL0
+ }, {
+ MDP_COMP_CAMIN2, MDP_COMP_CCORR0,
+ MT8183_MDP_IPU_MOUT_EN, MT8183_MDP_IPU_MOUT_EN_CCORR0,
+ MT8183_MDP_IPU_MOUT_EN_CCORR0
+ }, {
+ MDP_COMP_CAMIN2, MDP_COMP_RSZ1,
+ MT8183_MDP_IPU_MOUT_EN, MT8183_MDP_IPU_MOUT_EN_RSZ1,
+ MT8183_MDP_IPU_MOUT_EN_RSZ1
+ }, {
+ MDP_COMP_CAMIN2, MDP_COMP_AAL0,
+ MT8183_MDP_IPU_MOUT_EN, MT8183_MDP_IPU_MOUT_EN_AAL0,
+ MT8183_MDP_IPU_MOUT_EN_AAL0
+ }, {
+ MDP_COMP_RDMA0, MDP_COMP_CCORR0,
+ MT8183_MDP_RDMA0_MOUT_EN, MT8183_MDP_RDMA0_MOUT_EN_CCORR0,
+ MT8183_MDP_RDMA0_MOUT_EN_CCORR0
+ }, {
+ MDP_COMP_RDMA0, MDP_COMP_RSZ1,
+ MT8183_MDP_RDMA0_MOUT_EN, MT8183_MDP_RDMA0_MOUT_EN_RSZ1,
+ MT8183_MDP_RDMA0_MOUT_EN_RSZ1
+ }, {
+ MDP_COMP_RDMA0, MDP_COMP_PATH0_SOUT,
+ MT8183_MDP_RDMA0_MOUT_EN, MT8183_MDP_RDMA0_MOUT_EN_PATH0_OUT,
+ MT8183_MDP_RDMA0_MOUT_EN_PATH0_OUT
+ }, {
+ MDP_COMP_RDMA0, MDP_COMP_AAL0,
+ MT8183_MDP_RDMA0_MOUT_EN, MT8183_MDP_RDMA0_MOUT_EN_AAL0,
+ MT8183_MDP_RDMA0_MOUT_EN_AAL0
+ }, {
+ MDP_COMP_AAL0, MDP_COMP_CCORR0,
+ MT8183_MDP_AAL_MOUT_EN, MT8183_MDP_AAL_MOUT_EN_CCORR0,
+ MT8183_MDP_AAL_MOUT_EN_CCORR0
+ }, {
+ MDP_COMP_AAL0, MDP_COMP_RSZ1,
+ MT8183_MDP_AAL_MOUT_EN, MT8183_MDP_AAL_MOUT_EN_RSZ1,
+ MT8183_MDP_AAL_MOUT_EN_RSZ1
+ }, {
+ MDP_COMP_AAL0, MDP_COMP_RSZ0,
+ MT8183_MDP_AAL_MOUT_EN, MT8183_MDP_AAL_MOUT_EN_RSZ0,
+ MT8183_MDP_AAL_MOUT_EN_RSZ0
+ }, {
+ MDP_COMP_RSZ0, MDP_COMP_PATH0_SOUT,
+ MT8183_MDP_PRZ0_MOUT_EN, MT8183_MDP_PRZ0_MOUT_EN_PATH0_OUT,
+ MT8183_MDP_PRZ0_MOUT_EN_PATH0_OUT
+ }, {
+ MDP_COMP_RSZ0, MDP_COMP_TDSHP0,
+ MT8183_MDP_PRZ0_MOUT_EN, MT8183_MDP_PRZ0_MOUT_EN_TDSHP0,
+ MT8183_MDP_PRZ0_MOUT_EN_TDSHP0
+ }, {
+ MDP_COMP_RSZ1, MDP_COMP_PATH0_SOUT,
+ MT8183_MDP_PRZ1_MOUT_EN, MT8183_MDP_PRZ1_MOUT_EN_PATH0_OUT,
+ MT8183_MDP_PRZ1_MOUT_EN_PATH0_OUT
+ }, {
+ MDP_COMP_RSZ1, MDP_COMP_TDSHP0,
+ MT8183_MDP_PRZ1_MOUT_EN, MT8183_MDP_PRZ1_MOUT_EN_TDSHP0,
+ MT8183_MDP_PRZ1_MOUT_EN_TDSHP0
+ }, {
+ MDP_COMP_RSZ1, MDP_COMP_PATH1_SOUT,
+ MT8183_MDP_PRZ1_MOUT_EN, MT8183_MDP_PRZ1_MOUT_EN_PATH1_OUT,
+ MT8183_MDP_PRZ1_MOUT_EN_PATH1_OUT
+ }, {
+ MDP_COMP_RSZ1, MDP_COMP_COLOR0,
+ MT8183_MDP_PRZ1_MOUT_EN, MT8183_MDP_PRZ1_MOUT_EN_COLOR0,
+ MT8183_MDP_PRZ1_MOUT_EN_COLOR0
+ }, {
+ MDP_COMP_COLOR0, MDP_COMP_PATH0_SOUT,
+ MT8183_MDP_COLOR_MOUT_EN, MT8183_MDP_COLOR_MOUT_EN_PATH0_OUT,
+ MT8183_MDP_COLOR_MOUT_EN_PATH0_OUT
+ }, {
+ MDP_COMP_COLOR0, MDP_COMP_PATH1_SOUT,
+ MT8183_MDP_COLOR_MOUT_EN, MT8183_MDP_COLOR_MOUT_EN_PATH1_OUT,
+ MT8183_MDP_COLOR_MOUT_EN_PATH1_OUT
+ }, {
+ MDP_COMP_CAMIN, MDP_COMP_AAL0,
+ MT8183_MDP_AAL_SEL_IN, MT8183_MDP_AAL_SEL_IN_CAMIN,
+ MT8183_MDP_AAL_SEL_IN_CAMIN
+ }, {
+ MDP_COMP_RDMA0, MDP_COMP_AAL0,
+ MT8183_MDP_AAL_SEL_IN, MT8183_MDP_AAL_SEL_IN_RDMA0,
+ MT8183_MDP_AAL_SEL_IN_RDMA0
+ }, {
+ MDP_COMP_CAMIN2, MDP_COMP_AAL0,
+ MT8183_MDP_AAL_SEL_IN, MT8183_MDP_AAL_SEL_IN_CAMIN2,
+ MT8183_MDP_AAL_SEL_IN_CAMIN2
+ }, {
+ MDP_COMP_CCORR0, MDP_COMP_AAL0,
+ MT8183_MDP_AAL_SEL_IN, MT8183_MDP_AAL_SEL_IN_CCORR0,
+ MT8183_MDP_AAL_SEL_IN_CCORR0
+ }, {
+ MDP_COMP_CAMIN, MDP_COMP_CCORR0,
+ MT8183_MDP_CCORR_SEL_IN, MT8183_MDP_CCORR_SEL_IN_CAMIN,
+ MT8183_MDP_CCORR_SEL_IN_CAMIN
+ }, {
+ MDP_COMP_RDMA0, MDP_COMP_CCORR0,
+ MT8183_MDP_CCORR_SEL_IN, MT8183_MDP_CCORR_SEL_IN_RDMA0,
+ MT8183_MDP_CCORR_SEL_IN_RDMA0
+ }, {
+ MDP_COMP_CAMIN2, MDP_COMP_CCORR0,
+ MT8183_MDP_CCORR_SEL_IN, MT8183_MDP_CCORR_SEL_IN_CAMIN2,
+ MT8183_MDP_CCORR_SEL_IN_CAMIN2
+ }, {
+ MDP_COMP_AAL0, MDP_COMP_CCORR0,
+ MT8183_MDP_CCORR_SEL_IN, MT8183_MDP_CCORR_SEL_IN_AAL0,
+ MT8183_MDP_CCORR_SEL_IN_AAL0
+ }, {
+ MDP_COMP_AAL0, MDP_COMP_RSZ0,
+ MT8183_MDP_PRZ0_SEL_IN, MT8183_MDP_PRZ0_SEL_IN_AAL0,
+ MT8183_MDP_PRZ0_SEL_IN_AAL0
+ }, {
+ MDP_COMP_CCORR0, MDP_COMP_RSZ0,
+ MT8183_MDP_PRZ0_SEL_IN, MT8183_MDP_PRZ0_SEL_IN_CCORR0,
+ MT8183_MDP_PRZ0_SEL_IN_CCORR0
+ }, {
+ MDP_COMP_CAMIN, MDP_COMP_RSZ1,
+ MT8183_MDP_PRZ1_SEL_IN, MT8183_MDP_PRZ1_SEL_IN_CAMIN,
+ MT8183_MDP_PRZ1_SEL_IN_CAMIN
+ }, {
+ MDP_COMP_RDMA0, MDP_COMP_RSZ1,
+ MT8183_MDP_PRZ1_SEL_IN, MT8183_MDP_PRZ1_SEL_IN_RDMA0,
+ MT8183_MDP_PRZ1_SEL_IN_RDMA0
+ }, {
+ MDP_COMP_CAMIN2, MDP_COMP_RSZ1,
+ MT8183_MDP_PRZ1_SEL_IN, MT8183_MDP_PRZ1_SEL_IN_CAMIN2,
+ MT8183_MDP_PRZ1_SEL_IN_CAMIN2
+ }, {
+ MDP_COMP_AAL0, MDP_COMP_RSZ1,
+ MT8183_MDP_PRZ1_SEL_IN, MT8183_MDP_PRZ1_SEL_IN_AAL0,
+ MT8183_MDP_PRZ1_SEL_IN_AAL0
+ }, {
+ MDP_COMP_RSZ0, MDP_COMP_TDSHP0,
+ MT8183_MDP_TDSHP_SEL_IN, MT8183_MDP_TDSHP_SEL_IN_RSZ0,
+ MT8183_MDP_TDSHP_SEL_IN_RSZ0
+ }, {
+ MDP_COMP_RSZ1, MDP_COMP_TDSHP0,
+ MT8183_MDP_TDSHP_SEL_IN, MT8183_MDP_TDSHP_SEL_IN_RSZ1,
+ MT8183_MDP_TDSHP_SEL_IN_RSZ1
+ }, {
+ MDP_COMP_RSZ0, MDP_COMP_PATH0_SOUT,
+ MT8183_MDP_PATH0_SEL_IN, MT8183_MDP_PATH0_SEL_IN_RSZ0,
+ MT8183_MDP_PATH0_SEL_IN_RSZ0
+ }, {
+ MDP_COMP_RSZ1, MDP_COMP_PATH0_SOUT,
+ MT8183_MDP_PATH0_SEL_IN, MT8183_MDP_PATH0_SEL_IN_RSZ1,
+ MT8183_MDP_PATH0_SEL_IN_RSZ1
+ }, {
+ MDP_COMP_COLOR0, MDP_COMP_PATH0_SOUT,
+ MT8183_MDP_PATH0_SEL_IN, MT8183_MDP_PATH0_SEL_IN_COLOR0,
+ MT8183_MDP_PATH0_SEL_IN_COLOR0
+ }, {
+ MDP_COMP_RDMA0, MDP_COMP_PATH0_SOUT,
+ MT8183_MDP_PATH0_SEL_IN, MT8183_MDP_PATH0_SEL_IN_RDMA0,
+ MT8183_MDP_PATH0_SEL_IN_RDMA0
+ }, {
+ MDP_COMP_RSZ1, MDP_COMP_PATH1_SOUT,
+ MT8183_MDP_PATH1_SEL_IN, MT8183_MDP_PATH1_SEL_IN_RSZ1,
+ MT8183_MDP_PATH1_SEL_IN_RSZ1
+ }, {
+ MDP_COMP_COLOR0, MDP_COMP_PATH1_SOUT,
+ MT8183_MDP_PATH1_SEL_IN, MT8183_MDP_PATH1_SEL_IN_COLOR0,
+ MT8183_MDP_PATH1_SEL_IN_COLOR0
+ }, {
+ MDP_COMP_PATH0_SOUT, MDP_COMP_WROT0,
+ MT8183_MDP_WROT0_SEL_IN, MT8183_MDP_WROT0_SEL_IN_PATH0_OUT,
+ MT8183_MDP_WROT0_SEL_IN_PATH0_OUT
+ }, {
+ MDP_COMP_PATH1_SOUT, MDP_COMP_WDMA,
+ MT8183_MDP_WDMA_SEL_IN, MT8183_MDP_WDMA_SEL_IN_PATH1_OUT,
+ MT8183_MDP_WDMA_SEL_IN_PATH1_OUT
+ }, {
+ MDP_COMP_CCORR0, MDP_COMP_AAL0,
+ MT8183_MDP_CCORR_SOUT_SEL, MT8183_MDP_CCORR_SOUT_SEL_AAL0,
+ MT8183_MDP_CCORR_SOUT_SEL_AAL0
+ }, {
+ MDP_COMP_CCORR0, MDP_COMP_RSZ0,
+ MT8183_MDP_CCORR_SOUT_SEL, MT8183_MDP_CCORR_SOUT_SEL_RSZ0,
+ MT8183_MDP_CCORR_SOUT_SEL_RSZ0
+ }, {
+ MDP_COMP_PATH0_SOUT, MDP_COMP_WROT0,
+ MT8183_MDP_PATH0_SOUT_SEL, MT8183_MDP_PATH0_SOUT_SEL_WROT0,
+ MT8183_MDP_PATH0_SOUT_SEL_WROT0
+ }, {
+ MDP_COMP_PATH1_SOUT, MDP_COMP_WDMA,
+ MT8183_MDP_PATH1_SOUT_SEL, MT8183_MDP_PATH1_SOUT_SEL_WDMA,
+ MT8183_MDP_PATH1_SOUT_SEL_WDMA
+ }
+};
+
#endif /* __SOC_MEDIATEK_MT8183_MMSYS_H */
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 1e448f1ffefb..905847d6e16c 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -8,9 +8,11 @@
#include <linux/device.h>
#include <linux/io.h>
#include <linux/of_device.h>
+#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/reset-controller.h>
#include <linux/soc/mediatek/mtk-mmsys.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
#include "mtk-mmsys.h"
#include "mt8167-mmsys.h"
@@ -54,6 +56,8 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
.clk_driver = "clk-mt8183-mm",
.routes = mmsys_mt8183_routing_table,
.num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
+ .mdp_routes = mmsys_mt8183_mdp_routing_table,
+ .mdp_num_routes = ARRAY_SIZE(mmsys_mt8183_mdp_routing_table),
};
static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
@@ -73,6 +77,8 @@ struct mtk_mmsys {
const struct mtk_mmsys_driver_data *data;
spinlock_t lock; /* protects mmsys_sw_rst_b reg */
struct reset_controller_dev rcdev;
+ phys_addr_t addr;
+ u8 subsys_id;
};
void mtk_mmsys_ddp_connect(struct device *dev,
@@ -112,6 +118,45 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
}
EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
+void mtk_mmsys_mdp_connect(struct device *dev, struct mmsys_cmdq_cmd *cmd,
+ enum mtk_mdp_comp_id cur,
+ enum mtk_mdp_comp_id next)
+{
+ struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
+ const struct mtk_mmsys_routes *routes = mmsys->data->mdp_routes;
+ int i;
+
+ if (!routes) {
+ WARN_ON(!routes);
+ return;
+ }
+
+ WARN_ON(mmsys->subsys_id == 0);
+ for (i = 0; i < mmsys->data->mdp_num_routes; i++)
+ if (cur == routes[i].from_comp && next == routes[i].to_comp)
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id,
+ mmsys->addr + routes[i].addr,
+ routes[i].val, routes[i].mask);
+}
+EXPORT_SYMBOL_GPL(mtk_mmsys_mdp_connect);
+
+void mtk_mmsys_mdp_disconnect(struct device *dev, struct mmsys_cmdq_cmd *cmd,
+ enum mtk_mdp_comp_id cur,
+ enum mtk_mdp_comp_id next)
+{
+ struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
+ const struct mtk_mmsys_routes *routes = mmsys->data->mdp_routes;
+ int i;
+
+ WARN_ON(mmsys->subsys_id == 0);
+ for (i = 0; i < mmsys->data->mdp_num_routes; i++)
+ if (cur == routes[i].from_comp && next == routes[i].to_comp)
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id,
+ mmsys->addr + routes[i].addr,
+ 0, routes[i].mask);
+}
+EXPORT_SYMBOL_GPL(mtk_mmsys_mdp_disconnect);
+
static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned long id,
bool assert)
{
@@ -170,6 +215,8 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
struct platform_device *clks;
struct platform_device *drm;
struct mtk_mmsys *mmsys;
+ struct resource res;
+ struct cmdq_client_reg cmdq_reg;
int ret;
mmsys = devm_kzalloc(dev, sizeof(*mmsys), GFP_KERNEL);
@@ -195,6 +242,15 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
return ret;
}
+ if (of_address_to_resource(dev->of_node, 0, &res) < 0)
+ mmsys->addr = 0L;
+ else
+ mmsys->addr = res.start;
+
+ if (cmdq_dev_get_client_reg(dev, &cmdq_reg, 0) != 0)
+ dev_info(dev, "cmdq subsys id has not been set\n");
+ mmsys->subsys_id = cmdq_reg.subsys;
+
mmsys->data = of_device_get_match_data(&pdev->dev);
platform_set_drvdata(pdev, mmsys);
diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
index 8b0ed05117ea..7ec2107b9823 100644
--- a/drivers/soc/mediatek/mtk-mmsys.h
+++ b/drivers/soc/mediatek/mtk-mmsys.h
@@ -92,6 +92,8 @@ struct mtk_mmsys_driver_data {
const char *clk_driver;
const struct mtk_mmsys_routes *routes;
const unsigned int num_routes;
+ const struct mtk_mmsys_routes *mdp_routes;
+ const unsigned int mdp_num_routes;
};
/*
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 4bba275e235a..c5a4d6b181ce 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -7,8 +7,14 @@
#define __MTK_MMSYS_H
enum mtk_ddp_comp_id;
+enum mtk_mdp_comp_id;
struct device;
+struct mmsys_cmdq_cmd {
+ struct cmdq_pkt *pkt;
+ s32 *event;
+};
+
enum mtk_ddp_comp_id {
DDP_COMPONENT_AAL0,
DDP_COMPONENT_AAL1,
@@ -45,6 +51,46 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_ID_MAX,
};
+enum mtk_mdp_comp_id {
+ MDP_COMP_NONE = -1, /* Invalid engine */
+
+ /* ISP */
+ MDP_COMP_WPEI = 0,
+ MDP_COMP_WPEO, /* 1 */
+ MDP_COMP_WPEI2, /* 2 */
+ MDP_COMP_WPEO2, /* 3 */
+ MDP_COMP_ISP_IMGI, /* 4 */
+ MDP_COMP_ISP_IMGO, /* 5 */
+ MDP_COMP_ISP_IMG2O, /* 6 */
+
+ /* IPU */
+ MDP_COMP_IPUI, /* 7 */
+ MDP_COMP_IPUO, /* 8 */
+
+ /* MDP */
+ MDP_COMP_CAMIN, /* 9 */
+ MDP_COMP_CAMIN2, /* 10 */
+ MDP_COMP_RDMA0, /* 11 */
+ MDP_COMP_AAL0, /* 12 */
+ MDP_COMP_CCORR0, /* 13 */
+ MDP_COMP_RSZ0, /* 14 */
+ MDP_COMP_RSZ1, /* 15 */
+ MDP_COMP_TDSHP0, /* 16 */
+ MDP_COMP_COLOR0, /* 17 */
+ MDP_COMP_PATH0_SOUT, /* 18 */
+ MDP_COMP_PATH1_SOUT, /* 19 */
+ MDP_COMP_WROT0, /* 20 */
+ MDP_COMP_WDMA, /* 21 */
+
+ /* Dummy Engine */
+ MDP_COMP_RDMA1, /* 22 */
+ MDP_COMP_RSZ2, /* 23 */
+ MDP_COMP_TDSHP1, /* 24 */
+ MDP_COMP_WROT1, /* 25 */
+
+ MDP_MAX_COMP_COUNT /* ALWAYS keep at the end */
+};
+
void mtk_mmsys_ddp_connect(struct device *dev,
enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next);
@@ -53,4 +99,14 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next);
+void mtk_mmsys_mdp_connect(struct device *dev,
+ struct mmsys_cmdq_cmd *cmd,
+ enum mtk_mdp_comp_id cur,
+ enum mtk_mdp_comp_id next);
+
+void mtk_mmsys_mdp_disconnect(struct device *dev,
+ struct mmsys_cmdq_cmd *cmd,
+ enum mtk_mdp_comp_id cur,
+ enum mtk_mdp_comp_id next);
+
#endif /* __MTK_MMSYS_H */
--
2.18.0
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH v10 2/4] soc: mediatek: mmsys: add support for ISP control
[not found] <20211202061322.19917-1-moudy.ho@mediatek.com>
2021-12-02 6:13 ` [PATCH v10 1/4] soc: mediatek: mmsys: add support for MDP Moudy Ho
@ 2021-12-02 6:13 ` Moudy Ho
2021-12-02 12:12 ` AngeloGioacchino Del Regno
2021-12-02 6:13 ` [PATCH v10 3/4] soc: mediatek: mutex: add support for MDP Moudy Ho
2021-12-02 6:13 ` [PATCH v10 4/4] soc: mediatek: mutex: add functions that operate registers by CMDQ Moudy Ho
3 siblings, 1 reply; 6+ messages in thread
From: Moudy Ho @ 2021-12-02 6:13 UTC (permalink / raw)
To: Mauro Carvalho Chehab, Rob Herring, Matthias Brugger,
Hans Verkuil, Jernej Skrabec
Cc: Chun-Kuang Hu, Geert Uytterhoeven, Rob Landley, Laurent Pinchart,
linux-media, devicetree, linux-arm-kernel, linux-mediatek,
linux-kernel, Alexandre Courbot, tfiga, drinkcat, pihsun, hsinyi,
AngeloGioacchino Del Regno, Maoguang Meng, daoyuan huang,
Ping-Hsun Wu, menghui.lin, sj.huang, allen-kh.cheng, randy.wu,
moudy.ho, jason-jh.lin, roy-cw.yeh, river.cheng, srv_heupstream
This patch adds 8183 ISP settings in MMSYS domain and interface.
Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
---
drivers/soc/mediatek/mt8183-mmsys.h | 26 ++++++
drivers/soc/mediatek/mtk-mmsys.c | 117 +++++++++++++++++++++++++
drivers/soc/mediatek/mtk-mmsys.h | 1 +
include/linux/soc/mediatek/mtk-mmsys.h | 30 +++++++
4 files changed, 174 insertions(+)
diff --git a/drivers/soc/mediatek/mt8183-mmsys.h b/drivers/soc/mediatek/mt8183-mmsys.h
index 48865973314d..afc98c4dac95 100644
--- a/drivers/soc/mediatek/mt8183-mmsys.h
+++ b/drivers/soc/mediatek/mt8183-mmsys.h
@@ -32,6 +32,18 @@
#define MT8183_MDP_CCORR_SEL_IN 0xff0
#define MT8183_MDP_CCORR_SOUT_SEL 0xff4
+#define MT8183_ISP_REG_MMSYS_SW0_RST_B 0x140
+#define MT8183_ISP_REG_MMSYS_SW1_RST_B 0x144
+#define MT8183_ISP_REG_MDP_ASYNC_CFG_WD 0x934
+#define MT8183_ISP_REG_MDP_ASYNC_IPU_CFG_WD 0x93C
+#define MT8183_ISP_REG_ISP_RELAY_CFG_WD 0x994
+#define MT8183_ISP_REG_IPU_RELAY_CFG_WD 0x9a0
+#define MT8183_ISP_BIT_MDP_DL_ASYNC_TX BIT(3)
+#define MT8183_ISP_BIT_MDP_DL_ASYNC_TX2 BIT(4)
+#define MT8183_ISP_BIT_MDP_DL_ASYNC_RX BIT(10)
+#define MT8183_ISP_BIT_MDP_DL_ASYNC_RX2 BIT(11)
+#define MT8183_ISP_BIT_NO_SOF_MODE BIT(31)
+
#define MT8183_OVL0_MOUT_EN_OVL0_2L BIT(4)
#define MT8183_OVL0_2L_MOUT_EN_DISP_PATH0 BIT(0)
#define MT8183_OVL1_2L_MOUT_EN_RDMA1 BIT(4)
@@ -325,5 +337,19 @@ static const struct mtk_mmsys_routes mmsys_mt8183_mdp_routing_table[] = {
}
};
+static const unsigned int mmsys_mt8183_mdp_isp_ctrl_table[ISP_CTRL_MAX] = {
+ [ISP_REG_MMSYS_SW0_RST_B] = MT8183_ISP_REG_MMSYS_SW0_RST_B,
+ [ISP_REG_MMSYS_SW1_RST_B] = MT8183_ISP_REG_MMSYS_SW1_RST_B,
+ [ISP_REG_MDP_ASYNC_CFG_WD] = MT8183_ISP_REG_MDP_ASYNC_CFG_WD,
+ [ISP_REG_MDP_ASYNC_IPU_CFG_WD] = MT8183_ISP_REG_MDP_ASYNC_IPU_CFG_WD,
+ [ISP_REG_ISP_RELAY_CFG_WD] = MT8183_ISP_REG_ISP_RELAY_CFG_WD,
+ [ISP_REG_IPU_RELAY_CFG_WD] = MT8183_ISP_REG_IPU_RELAY_CFG_WD,
+ [ISP_BIT_MDP_DL_ASYNC_TX] = MT8183_ISP_BIT_MDP_DL_ASYNC_TX,
+ [ISP_BIT_MDP_DL_ASYNC_TX2] = MT8183_ISP_BIT_MDP_DL_ASYNC_TX2,
+ [ISP_BIT_MDP_DL_ASYNC_RX] = MT8183_ISP_BIT_MDP_DL_ASYNC_RX,
+ [ISP_BIT_MDP_DL_ASYNC_RX2] = MT8183_ISP_BIT_MDP_DL_ASYNC_RX2,
+ [ISP_BIT_NO_SOF_MODE] = MT8183_ISP_BIT_NO_SOF_MODE,
+};
+
#endif /* __SOC_MEDIATEK_MT8183_MMSYS_H */
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 905847d6e16c..cfbf36e6e0ad 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -58,6 +58,7 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
.num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
.mdp_routes = mmsys_mt8183_mdp_routing_table,
.mdp_num_routes = ARRAY_SIZE(mmsys_mt8183_mdp_routing_table),
+ .mdp_isp_ctrl = mmsys_mt8183_mdp_isp_ctrl_table,
};
static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
@@ -157,6 +158,122 @@ void mtk_mmsys_mdp_disconnect(struct device *dev, struct mmsys_cmdq_cmd *cmd,
}
EXPORT_SYMBOL_GPL(mtk_mmsys_mdp_disconnect);
+void mtk_mmsys_mdp_isp_ctrl(struct device *dev, struct mmsys_cmdq_cmd *cmd,
+ enum mtk_mdp_comp_id id)
+{
+ struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
+ const unsigned int *isp_ctrl = mmsys->data->mdp_isp_ctrl;
+ u32 reg;
+
+ WARN_ON(mmsys->subsys_id == 0);
+ /* Direct link */
+ if (id == MDP_COMP_CAMIN) {
+ /* Reset MDP_DL_ASYNC_TX */
+ if (isp_ctrl[ISP_REG_MMSYS_SW0_RST_B]) {
+ reg = mmsys->addr + isp_ctrl[ISP_REG_MMSYS_SW0_RST_B];
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id, reg,
+ 0x0,
+ isp_ctrl[ISP_BIT_MDP_DL_ASYNC_TX]);
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id, reg,
+ isp_ctrl[ISP_BIT_MDP_DL_ASYNC_TX],
+ isp_ctrl[ISP_BIT_MDP_DL_ASYNC_TX]);
+ }
+
+ /* Reset MDP_DL_ASYNC_RX */
+ if (isp_ctrl[ISP_REG_MMSYS_SW1_RST_B]) {
+ reg = mmsys->addr + isp_ctrl[ISP_REG_MMSYS_SW1_RST_B];
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id, reg,
+ 0x0,
+ isp_ctrl[ISP_BIT_MDP_DL_ASYNC_RX]);
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id, reg,
+ isp_ctrl[ISP_BIT_MDP_DL_ASYNC_RX],
+ isp_ctrl[ISP_BIT_MDP_DL_ASYNC_RX]);
+ }
+
+ /* Enable sof mode */
+ if (isp_ctrl[ISP_REG_ISP_RELAY_CFG_WD]) {
+ reg = mmsys->addr + isp_ctrl[ISP_REG_ISP_RELAY_CFG_WD];
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id, reg,
+ 0x0,
+ isp_ctrl[ISP_BIT_NO_SOF_MODE]);
+ }
+ }
+
+ if (id == MDP_COMP_CAMIN2) {
+ /* Reset MDP_DL_ASYNC2_TX */
+ if (isp_ctrl[ISP_REG_MMSYS_SW0_RST_B]) {
+ reg = mmsys->addr + isp_ctrl[ISP_REG_MMSYS_SW0_RST_B];
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id, reg,
+ 0x0,
+ isp_ctrl[ISP_BIT_MDP_DL_ASYNC_TX2]);
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id, reg,
+ isp_ctrl[ISP_BIT_MDP_DL_ASYNC_TX2],
+ isp_ctrl[ISP_BIT_MDP_DL_ASYNC_TX2]);
+ }
+
+ /* Reset MDP_DL_ASYNC2_RX */
+ if (isp_ctrl[ISP_REG_MMSYS_SW1_RST_B]) {
+ reg = mmsys->addr + isp_ctrl[ISP_REG_MMSYS_SW1_RST_B];
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id, reg,
+ 0x0,
+ isp_ctrl[ISP_BIT_MDP_DL_ASYNC_RX2]);
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id, reg,
+ isp_ctrl[ISP_BIT_MDP_DL_ASYNC_RX2],
+ isp_ctrl[ISP_BIT_MDP_DL_ASYNC_RX2]);
+ }
+
+ /* Enable sof mode */
+ if (isp_ctrl[ISP_REG_IPU_RELAY_CFG_WD]) {
+ reg = mmsys->addr + isp_ctrl[ISP_REG_IPU_RELAY_CFG_WD];
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id, reg,
+ 0x0,
+ isp_ctrl[ISP_BIT_NO_SOF_MODE]);
+ }
+ }
+}
+EXPORT_SYMBOL_GPL(mtk_mmsys_mdp_isp_ctrl);
+
+void mtk_mmsys_mdp_camin_ctrl(struct device *dev, struct mmsys_cmdq_cmd *cmd,
+ enum mtk_mdp_comp_id id, u32 camin_w, u32 camin_h)
+{
+ struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
+ const unsigned int *isp_ctrl = mmsys->data->mdp_isp_ctrl;
+ u32 reg;
+
+ WARN_ON(mmsys->subsys_id == 0);
+ /* Config for direct link */
+ if (id == MDP_COMP_CAMIN) {
+ if (isp_ctrl[ISP_REG_MDP_ASYNC_CFG_WD]) {
+ reg = mmsys->addr + isp_ctrl[ISP_REG_MDP_ASYNC_CFG_WD];
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id, reg,
+ (camin_h << 16) + camin_w,
+ 0x3FFF3FFF);
+ }
+
+ if (isp_ctrl[ISP_REG_ISP_RELAY_CFG_WD]) {
+ reg = mmsys->addr + isp_ctrl[ISP_REG_ISP_RELAY_CFG_WD];
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id, reg,
+ (camin_h << 16) + camin_w,
+ 0x3FFF3FFF);
+ }
+ }
+ if (id == MDP_COMP_CAMIN2) {
+ if (isp_ctrl[ISP_REG_MDP_ASYNC_IPU_CFG_WD]) {
+ reg = mmsys->addr + isp_ctrl[ISP_REG_MDP_ASYNC_IPU_CFG_WD];
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id, reg,
+ (camin_h << 16) + camin_w,
+ 0x3FFF3FFF);
+ }
+ if (isp_ctrl[ISP_REG_IPU_RELAY_CFG_WD]) {
+ reg = mmsys->addr + isp_ctrl[ISP_REG_IPU_RELAY_CFG_WD];
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id, reg,
+ (camin_h << 16) + camin_w,
+ 0x3FFF3FFF);
+ }
+ }
+}
+EXPORT_SYMBOL_GPL(mtk_mmsys_mdp_camin_ctrl);
+
static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned long id,
bool assert)
{
diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
index 7ec2107b9823..61baec9409de 100644
--- a/drivers/soc/mediatek/mtk-mmsys.h
+++ b/drivers/soc/mediatek/mtk-mmsys.h
@@ -94,6 +94,7 @@ struct mtk_mmsys_driver_data {
const unsigned int num_routes;
const struct mtk_mmsys_routes *mdp_routes;
const unsigned int mdp_num_routes;
+ const unsigned int *mdp_isp_ctrl;
};
/*
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index c5a4d6b181ce..1938428369f2 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -91,6 +91,29 @@ enum mtk_mdp_comp_id {
MDP_MAX_COMP_COUNT /* ALWAYS keep at the end */
};
+enum mtk_mdp_pipe_id {
+ MDP_PIPE_RDMA0,
+ MDP_PIPE_IMGI,
+ MDP_PIPE_WPEI,
+ MDP_PIPE_WPEI2,
+ MDP_PIPE_MAX
+};
+
+enum mtk_isp_ctrl {
+ ISP_REG_MMSYS_SW0_RST_B,
+ ISP_REG_MMSYS_SW1_RST_B,
+ ISP_REG_MDP_ASYNC_CFG_WD,
+ ISP_REG_MDP_ASYNC_IPU_CFG_WD,
+ ISP_REG_ISP_RELAY_CFG_WD,
+ ISP_REG_IPU_RELAY_CFG_WD,
+ ISP_BIT_MDP_DL_ASYNC_TX,
+ ISP_BIT_MDP_DL_ASYNC_TX2,
+ ISP_BIT_MDP_DL_ASYNC_RX,
+ ISP_BIT_MDP_DL_ASYNC_RX2,
+ ISP_BIT_NO_SOF_MODE,
+ ISP_CTRL_MAX
+};
+
void mtk_mmsys_ddp_connect(struct device *dev,
enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next);
@@ -109,4 +132,11 @@ void mtk_mmsys_mdp_disconnect(struct device *dev,
enum mtk_mdp_comp_id cur,
enum mtk_mdp_comp_id next);
+void mtk_mmsys_mdp_isp_ctrl(struct device *dev, struct mmsys_cmdq_cmd *cmd,
+ enum mtk_mdp_comp_id id);
+
+void mtk_mmsys_mdp_camin_ctrl(struct device *dev, struct mmsys_cmdq_cmd *cmd,
+ enum mtk_mdp_comp_id id,
+ u32 camin_w, u32 camin_h);
+
#endif /* __MTK_MMSYS_H */
--
2.18.0
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH v10 3/4] soc: mediatek: mutex: add support for MDP
[not found] <20211202061322.19917-1-moudy.ho@mediatek.com>
2021-12-02 6:13 ` [PATCH v10 1/4] soc: mediatek: mmsys: add support for MDP Moudy Ho
2021-12-02 6:13 ` [PATCH v10 2/4] soc: mediatek: mmsys: add support for ISP control Moudy Ho
@ 2021-12-02 6:13 ` Moudy Ho
2021-12-02 6:13 ` [PATCH v10 4/4] soc: mediatek: mutex: add functions that operate registers by CMDQ Moudy Ho
3 siblings, 0 replies; 6+ messages in thread
From: Moudy Ho @ 2021-12-02 6:13 UTC (permalink / raw)
To: Mauro Carvalho Chehab, Rob Herring, Matthias Brugger,
Hans Verkuil, Jernej Skrabec
Cc: Chun-Kuang Hu, Geert Uytterhoeven, Rob Landley, Laurent Pinchart,
linux-media, devicetree, linux-arm-kernel, linux-mediatek,
linux-kernel, Alexandre Courbot, tfiga, drinkcat, pihsun, hsinyi,
AngeloGioacchino Del Regno, Maoguang Meng, daoyuan huang,
Ping-Hsun Wu, menghui.lin, sj.huang, allen-kh.cheng, randy.wu,
moudy.ho, jason-jh.lin, roy-cw.yeh, river.cheng, srv_heupstream
For the purpose of module independence, related settings should be moved
from MDP to the corresponding driver.
This patch adds more 8183 MDP settings and interface.
Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/soc/mediatek/mtk-mutex.c | 68 ++++++++++++++++++++++++++
include/linux/soc/mediatek/mtk-mutex.h | 3 ++
2 files changed, 71 insertions(+)
diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index 2ca55bb5a8be..5525c5dbfe8e 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -119,6 +119,18 @@
#define MT8183_MUTEX_EOF_DSI0 (MT8183_MUTEX_SOF_DSI0 << 6)
#define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6)
+#define MT8183_MUTEX_MDP_START 5
+#define MT8183_MUTEX_MDP_MOD_MASK 0x07FFFFFF
+#define MT8183_MUTEX_MDP_SOF_MASK 0x00000007
+#define MT8183_MUTEX_MOD_MDP_RDMA0 BIT(2)
+#define MT8183_MUTEX_MOD_MDP_RSZ0 BIT(4)
+#define MT8183_MUTEX_MOD_MDP_RSZ1 BIT(5)
+#define MT8183_MUTEX_MOD_MDP_TDSHP0 BIT(6)
+#define MT8183_MUTEX_MOD_MDP_WROT0 BIT(7)
+#define MT8183_MUTEX_MOD_MDP_WDMA BIT(8)
+#define MT8183_MUTEX_MOD_MDP_AAL0 BIT(23)
+#define MT8183_MUTEX_MOD_MDP_CCORR0 BIT(24)
+
struct mtk_mutex {
int id;
bool claimed;
@@ -139,6 +151,10 @@ struct mtk_mutex_data {
const unsigned int *mutex_sof;
const unsigned int mutex_mod_reg;
const unsigned int mutex_sof_reg;
+ const unsigned int *mutex_mdp_offset;
+ const unsigned int *mutex_mdp_mod;
+ const unsigned int mutex_mdp_mod_mask;
+ const unsigned int mutex_mdp_sof_mask;
const bool no_clk;
};
@@ -226,6 +242,17 @@ static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0,
};
+static const unsigned int mt8183_mutex_mdp_mod[MDP_MAX_COMP_COUNT] = {
+ [MDP_COMP_RDMA0] = MT8183_MUTEX_MOD_MDP_RDMA0,
+ [MDP_COMP_RSZ0] = MT8183_MUTEX_MOD_MDP_RSZ0,
+ [MDP_COMP_RSZ1] = MT8183_MUTEX_MOD_MDP_RSZ1,
+ [MDP_COMP_TDSHP0] = MT8183_MUTEX_MOD_MDP_TDSHP0,
+ [MDP_COMP_WROT0] = MT8183_MUTEX_MOD_MDP_WROT0,
+ [MDP_COMP_WDMA] = MT8183_MUTEX_MOD_MDP_WDMA,
+ [MDP_COMP_AAL0] = MT8183_MUTEX_MOD_MDP_AAL0,
+ [MDP_COMP_CCORR0] = MT8183_MUTEX_MOD_MDP_CCORR0,
+};
+
static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT8192_MUTEX_MOD_DISP_AAL0,
[DDP_COMPONENT_CCORR] = MT8192_MUTEX_MOD_DISP_CCORR0,
@@ -264,6 +291,14 @@ static const unsigned int mt8183_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
[MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0,
};
+/* indicate which mutex is used by each pipepline */
+static const unsigned int mt8183_mutex_mdp_offset[MDP_PIPE_MAX] = {
+ [MDP_PIPE_IMGI] = MT8183_MUTEX_MDP_START,
+ [MDP_PIPE_RDMA0] = MT8183_MUTEX_MDP_START + 1,
+ [MDP_PIPE_WPEI] = MT8183_MUTEX_MDP_START + 2,
+ [MDP_PIPE_WPEI2] = MT8183_MUTEX_MDP_START + 3
+};
+
static const struct mtk_mutex_data mt2701_mutex_driver_data = {
.mutex_mod = mt2701_mutex_mod,
.mutex_sof = mt2712_mutex_sof,
@@ -298,6 +333,10 @@ static const struct mtk_mutex_data mt8183_mutex_driver_data = {
.mutex_sof = mt8183_mutex_sof,
.mutex_mod_reg = MT8183_MUTEX0_MOD0,
.mutex_sof_reg = MT8183_MUTEX0_SOF0,
+ .mutex_mdp_offset = mt8183_mutex_mdp_offset,
+ .mutex_mdp_mod = mt8183_mutex_mdp_mod,
+ .mutex_mdp_mod_mask = MT8183_MUTEX_MDP_MOD_MASK,
+ .mutex_mdp_sof_mask = MT8183_MUTEX_MDP_SOF_MASK,
.no_clk = true,
};
@@ -323,6 +362,21 @@ struct mtk_mutex *mtk_mutex_get(struct device *dev)
}
EXPORT_SYMBOL_GPL(mtk_mutex_get);
+struct mtk_mutex *mtk_mutex_mdp_get(struct device *dev,
+ enum mtk_mdp_pipe_id id)
+{
+ struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev);
+ int i = mtx->data->mutex_mdp_offset[id];
+
+ if (!mtx->mutex[i].claimed) {
+ mtx->mutex[i].claimed = true;
+ return &mtx->mutex[i];
+ }
+
+ return ERR_PTR(-EBUSY);
+}
+EXPORT_SYMBOL_GPL(mtk_mutex_mdp_get);
+
void mtk_mutex_put(struct mtk_mutex *mutex)
{
struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
@@ -442,6 +496,20 @@ void mtk_mutex_remove_comp(struct mtk_mutex *mutex,
}
EXPORT_SYMBOL_GPL(mtk_mutex_remove_comp);
+u32 mtk_mutex_get_mdp_mod(struct mtk_mutex *mutex,enum mtk_mdp_comp_id id)
+{
+ struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
+ mutex[mutex->id]);
+
+ WARN_ON(&mtx->mutex[mutex->id] != mutex);
+
+ if (mtx->data->mutex_mdp_mod)
+ return mtx->data->mutex_mdp_mod[id];
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(mtk_mutex_get_mdp_mod);
+
void mtk_mutex_enable(struct mtk_mutex *mutex)
{
struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
diff --git a/include/linux/soc/mediatek/mtk-mutex.h b/include/linux/soc/mediatek/mtk-mutex.h
index 6fe4ffbde290..b2608f4220ee 100644
--- a/include/linux/soc/mediatek/mtk-mutex.h
+++ b/include/linux/soc/mediatek/mtk-mutex.h
@@ -11,9 +11,12 @@ struct device;
struct mtk_mutex;
struct mtk_mutex *mtk_mutex_get(struct device *dev);
+struct mtk_mutex *mtk_mutex_mdp_get(struct device *dev,
+ enum mtk_mdp_pipe_id id);
int mtk_mutex_prepare(struct mtk_mutex *mutex);
void mtk_mutex_add_comp(struct mtk_mutex *mutex,
enum mtk_ddp_comp_id id);
+u32 mtk_mutex_get_mdp_mod(struct mtk_mutex *mutex, enum mtk_mdp_comp_id id);
void mtk_mutex_enable(struct mtk_mutex *mutex);
void mtk_mutex_disable(struct mtk_mutex *mutex);
void mtk_mutex_remove_comp(struct mtk_mutex *mutex,
--
2.18.0
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH v10 4/4] soc: mediatek: mutex: add functions that operate registers by CMDQ
[not found] <20211202061322.19917-1-moudy.ho@mediatek.com>
` (2 preceding siblings ...)
2021-12-02 6:13 ` [PATCH v10 3/4] soc: mediatek: mutex: add support for MDP Moudy Ho
@ 2021-12-02 6:13 ` Moudy Ho
2021-12-02 12:11 ` AngeloGioacchino Del Regno
3 siblings, 1 reply; 6+ messages in thread
From: Moudy Ho @ 2021-12-02 6:13 UTC (permalink / raw)
To: Mauro Carvalho Chehab, Rob Herring, Matthias Brugger,
Hans Verkuil, Jernej Skrabec
Cc: Chun-Kuang Hu, Geert Uytterhoeven, Rob Landley, Laurent Pinchart,
linux-media, devicetree, linux-arm-kernel, linux-mediatek,
linux-kernel, Alexandre Courbot, tfiga, drinkcat, pihsun, hsinyi,
AngeloGioacchino Del Regno, Maoguang Meng, daoyuan huang,
Ping-Hsun Wu, menghui.lin, sj.huang, allen-kh.cheng, randy.wu,
moudy.ho, jason-jh.lin, roy-cw.yeh, river.cheng, srv_heupstream
Considering that some functions have timing requirements
in specific situation, this patch adds several interface that
operate registers by CMDQ.
Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
---
drivers/soc/mediatek/mtk-mutex.c | 65 +++++++++++++++++++++++++-
include/linux/soc/mediatek/mtk-mutex.h | 6 +++
2 files changed, 70 insertions(+), 1 deletion(-)
diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index 5525c5dbfe8e..92a0e2bbd356 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -7,10 +7,14 @@
#include <linux/iopoll.h>
#include <linux/module.h>
#include <linux/of_device.h>
+#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/soc/mediatek/mtk-mmsys.h>
#include <linux/soc/mediatek/mtk-mutex.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
+
+#define MTK_MUTEX_ENABLE BIT(0)
#define MT2701_MUTEX0_MOD0 0x2c
#define MT2701_MUTEX0_SOF0 0x30
@@ -164,6 +168,8 @@ struct mtk_mutex_ctx {
void __iomem *regs;
struct mtk_mutex mutex[10];
const struct mtk_mutex_data *data;
+ phys_addr_t addr;
+ u8 subsys_id;
};
static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = {
@@ -510,6 +516,25 @@ u32 mtk_mutex_get_mdp_mod(struct mtk_mutex *mutex,enum mtk_mdp_comp_id id)
}
EXPORT_SYMBOL_GPL(mtk_mutex_get_mdp_mod);
+void mtk_mutex_add_mod_by_cmdq(struct mtk_mutex *mutex, u32 mod,
+ struct mmsys_cmdq_cmd *cmd)
+{
+ struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
+ mutex[mutex->id]);
+ unsigned int offset;
+
+ WARN_ON(&mtx->mutex[mutex->id] != mutex);
+
+ offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg, mutex->id);
+ cmdq_pkt_write_mask(cmd->pkt, mtx->subsys_id, mtx->addr + offset,
+ mod, mtx->data->mutex_mdp_mod_mask);
+
+ offset = DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg, mutex->id);
+ cmdq_pkt_write_mask(cmd->pkt, mtx->subsys_id, mtx->addr + offset,
+ 0, mtx->data->mutex_mdp_sof_mask);
+}
+EXPORT_SYMBOL_GPL(mtk_mutex_add_mod_by_cmdq);
+
void mtk_mutex_enable(struct mtk_mutex *mutex)
{
struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
@@ -521,6 +546,20 @@ void mtk_mutex_enable(struct mtk_mutex *mutex)
}
EXPORT_SYMBOL_GPL(mtk_mutex_enable);
+void mtk_mutex_enable_by_cmdq(struct mtk_mutex *mutex,
+ struct mmsys_cmdq_cmd *cmd)
+{
+ struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
+ mutex[mutex->id]);
+
+ WARN_ON(&mtx->mutex[mutex->id] != mutex);
+
+ cmdq_pkt_write_mask(cmd->pkt, mtx->subsys_id,
+ mtx->addr + DISP_REG_MUTEX_EN(mutex->id),
+ MTK_MUTEX_ENABLE, MTK_MUTEX_ENABLE);
+}
+EXPORT_SYMBOL_GPL(mtk_mutex_enable_by_cmdq);
+
void mtk_mutex_disable(struct mtk_mutex *mutex)
{
struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
@@ -532,6 +571,20 @@ void mtk_mutex_disable(struct mtk_mutex *mutex)
}
EXPORT_SYMBOL_GPL(mtk_mutex_disable);
+void mtk_mutex_disable_by_cmdq(struct mtk_mutex *mutex,
+ struct mmsys_cmdq_cmd *cmd)
+{
+ struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
+ mutex[mutex->id]);
+
+ WARN_ON(&mtx->mutex[mutex->id] != mutex);
+
+ cmdq_pkt_write_mask(cmd->pkt, mtx->subsys_id,
+ mtx->addr + DISP_REG_MUTEX_EN(mutex->id),
+ 0x0, MTK_MUTEX_ENABLE);
+}
+EXPORT_SYMBOL_GPL(mtk_mutex_disable_by_cmdq);
+
void mtk_mutex_acquire(struct mtk_mutex *mutex)
{
struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
@@ -559,7 +612,8 @@ static int mtk_mutex_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct mtk_mutex_ctx *mtx;
- struct resource *regs;
+ struct cmdq_client_reg cmdq_reg;
+ struct resource *regs, addr;
int i;
mtx = devm_kzalloc(dev, sizeof(*mtx), GFP_KERNEL);
@@ -580,6 +634,15 @@ static int mtk_mutex_probe(struct platform_device *pdev)
}
}
+ if (of_address_to_resource(dev->of_node, 0, &addr) < 0)
+ mtx->addr = 0L;
+ else
+ mtx->addr = addr.start;
+
+ if (cmdq_dev_get_client_reg(dev, &cmdq_reg, 0) != 0)
+ dev_info(dev, "cmdq subsys id has not been set\n");
+ mtx->subsys_id = cmdq_reg.subsys;
+
regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
mtx->regs = devm_ioremap_resource(dev, regs);
if (IS_ERR(mtx->regs)) {
diff --git a/include/linux/soc/mediatek/mtk-mutex.h b/include/linux/soc/mediatek/mtk-mutex.h
index b2608f4220ee..05de7ad4a124 100644
--- a/include/linux/soc/mediatek/mtk-mutex.h
+++ b/include/linux/soc/mediatek/mtk-mutex.h
@@ -17,8 +17,14 @@ int mtk_mutex_prepare(struct mtk_mutex *mutex);
void mtk_mutex_add_comp(struct mtk_mutex *mutex,
enum mtk_ddp_comp_id id);
u32 mtk_mutex_get_mdp_mod(struct mtk_mutex *mutex, enum mtk_mdp_comp_id id);
+void mtk_mutex_add_mod_by_cmdq(struct mtk_mutex *mutex, u32 mod,
+ struct mmsys_cmdq_cmd *cmd);
void mtk_mutex_enable(struct mtk_mutex *mutex);
+void mtk_mutex_enable_by_cmdq(struct mtk_mutex *mutex,
+ struct mmsys_cmdq_cmd *cmd);
void mtk_mutex_disable(struct mtk_mutex *mutex);
+void mtk_mutex_disable_by_cmdq(struct mtk_mutex *mutex,
+ struct mmsys_cmdq_cmd *cmd);
void mtk_mutex_remove_comp(struct mtk_mutex *mutex,
enum mtk_ddp_comp_id id);
void mtk_mutex_unprepare(struct mtk_mutex *mutex);
--
2.18.0
^ permalink raw reply related [flat|nested] 6+ messages in thread