Re: [PATCH 1/2] dt-bindings: cache: qcom,llcc: Document Eliza LLCC block

Re: [PATCH 1/2] dt-bindings: cache: qcom,llcc: Document Eliza LLCC block

[Krzysztof Kozlowski]

On Mon, May 04, 2026 at 01:00:07PM +0300, Abel Vesa wrote:
> Document the Last Level Cache Controller on Eliza SoC. Eliza LLCC has 2
> base register regions and an additional AND, OR broadcast region, total 4
> register regions.
> 
> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
> ---
>  .../devicetree/bindings/cache/qcom,llcc.yaml       | 22 ++++++++++++++++++++++
>  1 file changed, 22 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
> index 995d57815781..90f5a54b76e3 100644
> --- a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
> +++ b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
> @@ -20,6 +20,7 @@ description: |
>  properties:
>    compatible:
>      enum:
> +      - qcom,eliza-llcc
>        - qcom,glymur-llcc
>        - qcom,ipq5424-llcc
>        - qcom,kaanapali-llcc
> @@ -341,6 +342,27 @@ allOf:
>              - const: llcc_broadcast_base
>              - const: llcc_broadcast_and_base
>  
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            enum:
> +              - qcom,eliza-llcc
> +    then:
> +      properties:
> +        reg:
> +          items:
> +            - description: LLCC0 base register region
> +            - description: LLCC2 base register region

LLCC1?

> +            - description: LLCC broadcast OR register region
> +            - description: LLCC broadcast AND register region
> +        reg-names:
> +          items:
> +            - const: llcc0_base
> +            - const: llcc2_base

llcc1_base?

Best regards,
Krzysztof

Re: [PATCH 1/2] dt-bindings: cache: qcom,llcc: Document Eliza LLCC block

[Konrad Dybcio]

On 5/6/26 10:25 AM, Krzysztof Kozlowski wrote:
> On Mon, May 04, 2026 at 01:00:07PM +0300, Abel Vesa wrote:
>> Document the Last Level Cache Controller on Eliza SoC. Eliza LLCC has 2
>> base register regions and an additional AND, OR broadcast region, total 4
>> register regions.
>>
>> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
>> ---
>>  .../devicetree/bindings/cache/qcom,llcc.yaml       | 22 ++++++++++++++++++++++
>>  1 file changed, 22 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
>> index 995d57815781..90f5a54b76e3 100644
>> --- a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
>> +++ b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
>> @@ -20,6 +20,7 @@ description: |
>>  properties:
>>    compatible:
>>      enum:
>> +      - qcom,eliza-llcc
>>        - qcom,glymur-llcc
>>        - qcom,ipq5424-llcc
>>        - qcom,kaanapali-llcc
>> @@ -341,6 +342,27 @@ allOf:
>>              - const: llcc_broadcast_base
>>              - const: llcc_broadcast_and_base
>>  
>> +  - if:
>> +      properties:
>> +        compatible:
>> +          contains:
>> +            enum:
>> +              - qcom,eliza-llcc
>> +    then:
>> +      properties:
>> +        reg:
>> +          items:
>> +            - description: LLCC0 base register region
>> +            - description: LLCC2 base register region
> 
> LLCC1?

Unfortunately not

Konrad

Re: [PATCH 1/2] dt-bindings: cache: qcom,llcc: Document Eliza LLCC block

[Krzysztof Kozlowski]

On 06/05/2026 10:49, Konrad Dybcio wrote:
> On 5/6/26 10:25 AM, Krzysztof Kozlowski wrote:
>> On Mon, May 04, 2026 at 01:00:07PM +0300, Abel Vesa wrote:
>>> Document the Last Level Cache Controller on Eliza SoC. Eliza LLCC has 2
>>> base register regions and an additional AND, OR broadcast region, total 4
>>> register regions.
>>>
>>> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
>>> ---
>>>  .../devicetree/bindings/cache/qcom,llcc.yaml       | 22 ++++++++++++++++++++++
>>>  1 file changed, 22 insertions(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
>>> index 995d57815781..90f5a54b76e3 100644
>>> --- a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
>>> +++ b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
>>> @@ -20,6 +20,7 @@ description: |
>>>  properties:
>>>    compatible:
>>>      enum:
>>> +      - qcom,eliza-llcc
>>>        - qcom,glymur-llcc
>>>        - qcom,ipq5424-llcc
>>>        - qcom,kaanapali-llcc
>>> @@ -341,6 +342,27 @@ allOf:
>>>              - const: llcc_broadcast_base
>>>              - const: llcc_broadcast_and_base
>>>  
>>> +  - if:
>>> +      properties:
>>> +        compatible:
>>> +          contains:
>>> +            enum:
>>> +              - qcom,eliza-llcc
>>> +    then:
>>> +      properties:
>>> +        reg:
>>> +          items:
>>> +            - description: LLCC0 base register region
>>> +            - description: LLCC2 base register region
>>
>> LLCC1?
> 
> Unfortunately not

Then let's just skip the names, because it will cause unnecessary
confusion when name is llcc1 (since it is the NEXT entry) but it points
to block called LLCC2 in the manual.


Best regards,
Krzysztof

Re: [PATCH 1/2] dt-bindings: cache: qcom,llcc: Document Eliza LLCC block

[Konrad Dybcio]

On 5/6/26 11:56 AM, Krzysztof Kozlowski wrote:
> On 06/05/2026 10:49, Konrad Dybcio wrote:
>> On 5/6/26 10:25 AM, Krzysztof Kozlowski wrote:
>>> On Mon, May 04, 2026 at 01:00:07PM +0300, Abel Vesa wrote:
>>>> Document the Last Level Cache Controller on Eliza SoC. Eliza LLCC has 2
>>>> base register regions and an additional AND, OR broadcast region, total 4
>>>> register regions.
>>>>
>>>> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
>>>> ---
>>>>  .../devicetree/bindings/cache/qcom,llcc.yaml       | 22 ++++++++++++++++++++++
>>>>  1 file changed, 22 insertions(+)
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
>>>> index 995d57815781..90f5a54b76e3 100644
>>>> --- a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
>>>> +++ b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
>>>> @@ -20,6 +20,7 @@ description: |
>>>>  properties:
>>>>    compatible:
>>>>      enum:
>>>> +      - qcom,eliza-llcc
>>>>        - qcom,glymur-llcc
>>>>        - qcom,ipq5424-llcc
>>>>        - qcom,kaanapali-llcc
>>>> @@ -341,6 +342,27 @@ allOf:
>>>>              - const: llcc_broadcast_base
>>>>              - const: llcc_broadcast_and_base
>>>>  
>>>> +  - if:
>>>> +      properties:
>>>> +        compatible:
>>>> +          contains:
>>>> +            enum:
>>>> +              - qcom,eliza-llcc
>>>> +    then:
>>>> +      properties:
>>>> +        reg:
>>>> +          items:
>>>> +            - description: LLCC0 base register region
>>>> +            - description: LLCC2 base register region
>>>
>>> LLCC1?
>>
>> Unfortunately not
> 
> Then let's just skip the names, because it will cause unnecessary
> confusion when name is llcc1 (since it is the NEXT entry) but it points
> to block called LLCC2 in the manual.

I don't think skipping the names is a good idea, especially since if
we keep them, we could teach the driver what channel the region actually
corresponds to

Konrad

Re: [PATCH 1/2] dt-bindings: cache: qcom,llcc: Document Eliza LLCC block

[Krzysztof Kozlowski]

On 06/05/2026 12:47, Konrad Dybcio wrote:
> On 5/6/26 11:56 AM, Krzysztof Kozlowski wrote:
>>>>> +    then:
>>>>> +      properties:
>>>>> +        reg:
>>>>> +          items:
>>>>> +            - description: LLCC0 base register region
>>>>> +            - description: LLCC2 base register region
>>>>
>>>> LLCC1?
>>>
>>> Unfortunately not
>>
>> Then let's just skip the names, because it will cause unnecessary
>> confusion when name is llcc1 (since it is the NEXT entry) but it points
>> to block called LLCC2 in the manual.
> 
> I don't think skipping the names is a good idea, especially since if
> we keep them, we could teach the driver what channel the region actually
> corresponds to

You still can do it, because indices are fixed. Names are only helper
and makes that easier.

The problem looks to me purely doc-related, because this is logically
second channel, so LLCC1, just like qcom,sc7280-llcc or
qcom,sdm670-llcc. Does naming it as third channel (LLCC2) is relevant
for programming interface? Imagine driver taking LLCCx and using the 'x'
as offset?

I tried to find something in HPG but no luck.


Best regards,
Krzysztof

Re: [PATCH 1/2] dt-bindings: cache: qcom,llcc: Document Eliza LLCC block

[Abel Vesa]

On 26-05-06 14:15:57, Krzysztof Kozlowski wrote:
> On 06/05/2026 12:47, Konrad Dybcio wrote:
> > On 5/6/26 11:56 AM, Krzysztof Kozlowski wrote:
> >>>>> +    then:
> >>>>> +      properties:
> >>>>> +        reg:
> >>>>> +          items:
> >>>>> +            - description: LLCC0 base register region
> >>>>> +            - description: LLCC2 base register region
> >>>>
> >>>> LLCC1?
> >>>
> >>> Unfortunately not
> >>
> >> Then let's just skip the names, because it will cause unnecessary
> >> confusion when name is llcc1 (since it is the NEXT entry) but it points
> >> to block called LLCC2 in the manual.
> > 
> > I don't think skipping the names is a good idea, especially since if
> > we keep them, we could teach the driver what channel the region actually
> > corresponds to
> 
> You still can do it, because indices are fixed. Names are only helper
> and makes that easier.
> 
> The problem looks to me purely doc-related, because this is logically
> second channel, so LLCC1, just like qcom,sc7280-llcc or
> qcom,sdm670-llcc. Does naming it as third channel (LLCC2) is relevant
> for programming interface? Imagine driver taking LLCCx and using the 'x'
> as offset?

I think it creats confusion for someone else who will consult the
internal doc and see the difference in naming.

Re: [PATCH 1/2] dt-bindings: cache: qcom,llcc: Document Eliza LLCC block

[Konrad Dybcio]

On 5/6/26 2:15 PM, Krzysztof Kozlowski wrote:
> On 06/05/2026 12:47, Konrad Dybcio wrote:
>> On 5/6/26 11:56 AM, Krzysztof Kozlowski wrote:
>>>>>> +    then:
>>>>>> +      properties:
>>>>>> +        reg:
>>>>>> +          items:
>>>>>> +            - description: LLCC0 base register region
>>>>>> +            - description: LLCC2 base register region
>>>>>
>>>>> LLCC1?
>>>>
>>>> Unfortunately not
>>>
>>> Then let's just skip the names, because it will cause unnecessary
>>> confusion when name is llcc1 (since it is the NEXT entry) but it points
>>> to block called LLCC2 in the manual.
>>
>> I don't think skipping the names is a good idea, especially since if
>> we keep them, we could teach the driver what channel the region actually
>> corresponds to
> 
> You still can do it, because indices are fixed. Names are only helper
> and makes that easier.
> 
> The problem looks to me purely doc-related, because this is logically
> second channel, so LLCC1, just like qcom,sc7280-llcc or
> qcom,sdm670-llcc. Does naming it as third channel (LLCC2) is relevant
> for programming interface? Imagine driver taking LLCCx and using the 'x'
> as offset?
> 
> I tried to find something in HPG but no luck.

On recent platforms, channels 0/2 and 1/3 are paired, perhaps that's
where it comes from

Konrad

Re: [PATCH 1/2] dt-bindings: cache: qcom,llcc: Document Eliza LLCC block

[Abel Vesa]

On 26-05-07 12:47:25, Konrad Dybcio wrote:
> On 5/6/26 2:15 PM, Krzysztof Kozlowski wrote:
> > On 06/05/2026 12:47, Konrad Dybcio wrote:
> >> On 5/6/26 11:56 AM, Krzysztof Kozlowski wrote:
> >>>>>> +    then:
> >>>>>> +      properties:
> >>>>>> +        reg:
> >>>>>> +          items:
> >>>>>> +            - description: LLCC0 base register region
> >>>>>> +            - description: LLCC2 base register region
> >>>>>
> >>>>> LLCC1?
> >>>>
> >>>> Unfortunately not
> >>>
> >>> Then let's just skip the names, because it will cause unnecessary
> >>> confusion when name is llcc1 (since it is the NEXT entry) but it points
> >>> to block called LLCC2 in the manual.
> >>
> >> I don't think skipping the names is a good idea, especially since if
> >> we keep them, we could teach the driver what channel the region actually
> >> corresponds to
> > 
> > You still can do it, because indices are fixed. Names are only helper
> > and makes that easier.
> > 
> > The problem looks to me purely doc-related, because this is logically
> > second channel, so LLCC1, just like qcom,sc7280-llcc or
> > qcom,sdm670-llcc. Does naming it as third channel (LLCC2) is relevant
> > for programming interface? Imagine driver taking LLCCx and using the 'x'
> > as offset?
> > 
> > I tried to find something in HPG but no luck.
> 
> On recent platforms, channels 0/2 and 1/3 are paired, perhaps that's
> where it comes from

So what is the suggestion here? Do we keep 0 and 2 ? Or should I rename
LLCC2 to LLCC1 ?

Re: [PATCH 1/2] dt-bindings: cache: qcom,llcc: Document Eliza LLCC block

[Krzysztof Kozlowski]

On 07/05/2026 12:47, Konrad Dybcio wrote:
> On 5/6/26 2:15 PM, Krzysztof Kozlowski wrote:
>> On 06/05/2026 12:47, Konrad Dybcio wrote:
>>> On 5/6/26 11:56 AM, Krzysztof Kozlowski wrote:
>>>>>>> +    then:
>>>>>>> +      properties:
>>>>>>> +        reg:
>>>>>>> +          items:
>>>>>>> +            - description: LLCC0 base register region
>>>>>>> +            - description: LLCC2 base register region
>>>>>>
>>>>>> LLCC1?
>>>>>
>>>>> Unfortunately not
>>>>
>>>> Then let's just skip the names, because it will cause unnecessary
>>>> confusion when name is llcc1 (since it is the NEXT entry) but it points
>>>> to block called LLCC2 in the manual.
>>>
>>> I don't think skipping the names is a good idea, especially since if
>>> we keep them, we could teach the driver what channel the region actually
>>> corresponds to
>>
>> You still can do it, because indices are fixed. Names are only helper
>> and makes that easier.
>>
>> The problem looks to me purely doc-related, because this is logically
>> second channel, so LLCC1, just like qcom,sc7280-llcc or
>> qcom,sdm670-llcc. Does naming it as third channel (LLCC2) is relevant
>> for programming interface? Imagine driver taking LLCCx and using the 'x'
>> as offset?
>>
>> I tried to find something in HPG but no luck.
> 
> On recent platforms, channels 0/2 and 1/3 are paired, perhaps that's
> where it comes from

Yes and since there is no 1 and 3, what are the pairs here? No pairs.
It's only first (LLCC0) and second (LLCC1), even though the docs call it
differently.

However as Abel suggested better to stay consistent with the manual, so
I guess LLCC2 makes more sense.

Best regards,
Krzysztof

Re: [PATCH 1/2] dt-bindings: cache: qcom,llcc: Document Eliza LLCC block

[Krzysztof Kozlowski]

On 04/05/2026 12:00, Abel Vesa wrote:
> Document the Last Level Cache Controller on Eliza SoC. Eliza LLCC has 2
> base register regions and an additional AND, OR broadcast region, total 4
> register regions.
> 
> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
> ---
>  .../devicetree/bindings/cache/qcom,llcc.yaml       | 22 ++++++++++++++++++++++
>  1 file changed, 22 insertions(+)
> 

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>

Best regards,
Krzysztof