Re: [PATCH] clk: qcom: ipq9574: Update the alpha PLL type for GPLLs

[Stephen Boyd <sboyd@kernel.org>]

Quoting Amandeep Singh (2024-08-05 02:11:16)
> On 8/3/2024 6:35 AM, Stephen Boyd wrote:
> > Quoting Amandeep Singh (2024-08-01 04:00:40)
> >> From: devi priya <quic_devipriy@quicinc.com>
> >>
> >> Update PLL offsets to DEFAULT_EVO to configure MDIO to 800MHz.
> > 
> > Is this fixing a problem? I can't figure out how urgent this patch is
> > from the one sentence commit text.
> 
> The incorrect clock frequency leads to an incorrect MDIO clock. This,
> in turn, affects the MDIO hardware configurations as the divider is 
> calculated from the MDIO clock frequency. If the clock frequency is
> not as expected, the MDIO register fails due to the generation of an 
> incorrect MDIO frequency.
> 
> This issue is critical as it results in incorrect MDIO configurations 
> and ultimately leads to the MDIO function not working. This results in
> a complete feature failure affecting all Ethernet PHYs. Specifically,
> Ethernet will not work on IPQ9574 due to this issue.
> 
> Currently, the clock frequency is set to CLK_ALPHA_PLL_TYPE_DEFAULT. 
> However, this setting does not yield the expected clock frequency. To 
> rectify this, we need to change this to CLK_ALPHA_PLL_TYPE_DEFAULT_EVO.
> 
> This modification ensures that the clock frequency aligns with our 
> expectations, thereby resolving the MDIO register failure and ensuring 
> the proper functioning of the Ethernet on IPQ9574.

Wow! Please include these details in the commit text.