* [PATCH RFT 01/14] soc: qcom: Add UBWC config provider
2025-05-08 18:12 [RFT PATCH 00/14] Add a single source of truth for UBWC configuration data Konrad Dybcio
@ 2025-05-08 18:12 ` Konrad Dybcio
2025-05-08 20:12 ` Connor Abbott
2025-05-11 22:21 ` Bjorn Andersson
2025-05-08 18:12 ` [PATCH RFT 02/14] drm/msm: Use the central UBWC config database Konrad Dybcio
` (12 subsequent siblings)
13 siblings, 2 replies; 43+ messages in thread
From: Konrad Dybcio @ 2025-05-08 18:12 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Clark, Abhinav Kumar,
Dmitry Baryshkov, Akhil P Oommen, Sean Paul, David Airlie,
Simona Vetter
Cc: Marijn Suijten, linux-kernel, linux-arm-msm, dri-devel, freedreno,
Konrad Dybcio
From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Add a file that will serve as a single source of truth for UBWC
configuration data for various multimedia blocks.
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
---
drivers/soc/qcom/Kconfig | 8 ++
drivers/soc/qcom/Makefile | 1 +
drivers/soc/qcom/ubwc_config.c | 255 +++++++++++++++++++++++++++++++++++++++++
include/linux/soc/qcom/ubwc.h | 31 +++++
4 files changed, 295 insertions(+)
diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig
index 58e63cf0036ba8554e4082da5184a620ca807a9e..2caadbbcf8307ff94f5afbdd1481e5e5e291749f 100644
--- a/drivers/soc/qcom/Kconfig
+++ b/drivers/soc/qcom/Kconfig
@@ -296,3 +296,11 @@ config QCOM_PBS
PBS trigger event to the PBS RAM.
endmenu
+
+config QCOM_UBWC_CONFIG
+ tristate
+ help
+ Most Qualcomm SoCs feature a number of Universal Bandwidth Compression
+ (UBWC) engines across various IP blocks, which need to be initialized
+ with coherent configuration data. This module functions as a single
+ source of truth for that information.
diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile
index acbca2ab5cc2a9ab3dce1ff38efd048ba2fab31e..b7f1d2a5736748b8772c090fd24462fa91f321c6 100644
--- a/drivers/soc/qcom/Makefile
+++ b/drivers/soc/qcom/Makefile
@@ -39,3 +39,4 @@ obj-$(CONFIG_QCOM_ICC_BWMON) += icc-bwmon.o
qcom_ice-objs += ice.o
obj-$(CONFIG_QCOM_INLINE_CRYPTO_ENGINE) += qcom_ice.o
obj-$(CONFIG_QCOM_PBS) += qcom-pbs.o
+obj-$(CONFIG_QCOM_UBWC_CONFIG) += ubwc_config.o
diff --git a/drivers/soc/qcom/ubwc_config.c b/drivers/soc/qcom/ubwc_config.c
new file mode 100644
index 0000000000000000000000000000000000000000..3f81fb2aab284dc9a5bcf53e5d638aaba44b6f2d
--- /dev/null
+++ b/drivers/soc/qcom/ubwc_config.c
@@ -0,0 +1,255 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#include <linux/debugfs.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+
+#include <linux/soc/qcom/ubwc.h>
+
+static const struct qcom_ubwc_cfg_data msm8937_data = {
+ .ubwc_enc_version = UBWC_1_0,
+ .ubwc_dec_version = UBWC_1_0,
+ .highest_bank_bit = 1,
+ .mdss_reg_bus_bw = 76800,
+};
+
+static const struct qcom_ubwc_cfg_data msm8998_data = {
+ .ubwc_enc_version = UBWC_1_0,
+ .ubwc_dec_version = UBWC_1_0,
+ .highest_bank_bit = 2,
+ .mdss_reg_bus_bw = 76800,
+};
+
+static const struct qcom_ubwc_cfg_data qcm2290_data = {
+ /* no UBWC */
+ .highest_bank_bit = 2,
+ .mdss_reg_bus_bw = 76800,
+};
+
+static const struct qcom_ubwc_cfg_data sa8775p_data = {
+ .ubwc_enc_version = UBWC_4_0,
+ .ubwc_dec_version = UBWC_4_0,
+ .ubwc_swizzle = 4,
+ .ubwc_bank_spread = true,
+ .highest_bank_bit = 0,
+ .macrotile_mode = true,
+ .mdss_reg_bus_bw = 74000,
+};
+
+static const struct qcom_ubwc_cfg_data sar2130p_data = {
+ .ubwc_enc_version = UBWC_3_0, /* 4.0.2 in hw */
+ .ubwc_dec_version = UBWC_4_3,
+ .ubwc_swizzle = 6,
+ .ubwc_bank_spread = true,
+ .highest_bank_bit = 0,
+ .macrotile_mode = true,
+ .mdss_reg_bus_bw = 74000,
+};
+
+static const struct qcom_ubwc_cfg_data sc7180_data = {
+ .ubwc_enc_version = UBWC_2_0,
+ .ubwc_dec_version = UBWC_2_0,
+ .ubwc_swizzle = 6,
+ .ubwc_bank_spread = true,
+ .highest_bank_bit = 1,
+ .mdss_reg_bus_bw = 76800,
+};
+
+static const struct qcom_ubwc_cfg_data sc7280_data = {
+ .ubwc_enc_version = UBWC_3_0,
+ .ubwc_dec_version = UBWC_4_0,
+ .ubwc_swizzle = 6,
+ .ubwc_bank_spread = true,
+ .highest_bank_bit = 1,
+ .macrotile_mode = true,
+ .mdss_reg_bus_bw = 74000,
+};
+
+static const struct qcom_ubwc_cfg_data sc8180x_data = {
+ .ubwc_enc_version = UBWC_3_0,
+ .ubwc_dec_version = UBWC_3_0,
+ .highest_bank_bit = 3,
+ .macrotile_mode = true,
+ .mdss_reg_bus_bw = 76800,
+};
+
+static const struct qcom_ubwc_cfg_data sc8280xp_data = {
+ .ubwc_enc_version = UBWC_4_0,
+ .ubwc_dec_version = UBWC_4_0,
+ .ubwc_swizzle = 6,
+ .ubwc_bank_spread = true,
+ .highest_bank_bit = 3,
+ .macrotile_mode = true,
+ .mdss_reg_bus_bw = 76800,
+};
+
+static const struct qcom_ubwc_cfg_data sdm670_data = {
+ .ubwc_enc_version = UBWC_2_0,
+ .ubwc_dec_version = UBWC_2_0,
+ .highest_bank_bit = 1,
+ .mdss_reg_bus_bw = 76800,
+};
+
+static const struct qcom_ubwc_cfg_data sdm845_data = {
+ .ubwc_enc_version = UBWC_2_0,
+ .ubwc_dec_version = UBWC_2_0,
+ .highest_bank_bit = 2,
+ .mdss_reg_bus_bw = 76800,
+};
+
+static const struct qcom_ubwc_cfg_data sm6115_data = {
+ .ubwc_enc_version = UBWC_1_0,
+ .ubwc_dec_version = UBWC_2_0,
+ .ubwc_swizzle = 7,
+ .ubwc_bank_spread = true,
+ .highest_bank_bit = 1,
+ .mdss_reg_bus_bw = 76800,
+};
+
+static const struct qcom_ubwc_cfg_data sm6125_data = {
+ .ubwc_enc_version = UBWC_1_0,
+ .ubwc_dec_version = UBWC_3_0,
+ .ubwc_swizzle = 1,
+ .highest_bank_bit = 1,
+};
+
+static const struct qcom_ubwc_cfg_data sm6150_data = {
+ .ubwc_enc_version = UBWC_2_0,
+ .ubwc_dec_version = UBWC_2_0,
+ .highest_bank_bit = 1,
+ .mdss_reg_bus_bw = 76800,
+};
+
+static const struct qcom_ubwc_cfg_data sm6350_data = {
+ .ubwc_enc_version = UBWC_2_0,
+ .ubwc_dec_version = UBWC_2_0,
+ .ubwc_swizzle = 6,
+ .ubwc_bank_spread = true,
+ .highest_bank_bit = 1,
+ .mdss_reg_bus_bw = 76800,
+};
+
+static const struct qcom_ubwc_cfg_data sm7150_data = {
+ .ubwc_enc_version = UBWC_2_0,
+ .ubwc_dec_version = UBWC_2_0,
+ .highest_bank_bit = 1,
+ .mdss_reg_bus_bw = 76800,
+};
+
+static const struct qcom_ubwc_cfg_data sm8150_data = {
+ .ubwc_enc_version = UBWC_3_0,
+ .ubwc_dec_version = UBWC_3_0,
+ .highest_bank_bit = 2,
+ .mdss_reg_bus_bw = 76800,
+};
+
+static const struct qcom_ubwc_cfg_data sm8250_data = {
+ .ubwc_enc_version = UBWC_4_0,
+ .ubwc_dec_version = UBWC_4_0,
+ .ubwc_swizzle = 6,
+ .ubwc_bank_spread = true,
+ /* TODO: highest_bank_bit = 2 for LP_DDR4 */
+ .highest_bank_bit = 3,
+ .macrotile_mode = true,
+ .mdss_reg_bus_bw = 76800,
+};
+
+static const struct qcom_ubwc_cfg_data sm8350_data = {
+ .ubwc_enc_version = UBWC_4_0,
+ .ubwc_dec_version = UBWC_4_0,
+ .ubwc_swizzle = 6,
+ .ubwc_bank_spread = true,
+ /* TODO: highest_bank_bit = 2 for LP_DDR4 */
+ .highest_bank_bit = 3,
+ .macrotile_mode = true,
+ .mdss_reg_bus_bw = 74000,
+};
+
+static const struct qcom_ubwc_cfg_data sm8550_data = {
+ .ubwc_enc_version = UBWC_4_0,
+ .ubwc_dec_version = UBWC_4_3,
+ .ubwc_swizzle = 6,
+ .ubwc_bank_spread = true,
+ /* TODO: highest_bank_bit = 2 for LP_DDR4 */
+ .highest_bank_bit = 3,
+ .macrotile_mode = true,
+ .mdss_reg_bus_bw = 57000,
+};
+
+static const struct qcom_ubwc_cfg_data x1e80100_data = {
+ .ubwc_enc_version = UBWC_4_0,
+ .ubwc_dec_version = UBWC_4_3,
+ .ubwc_swizzle = 6,
+ .ubwc_bank_spread = true,
+ /* TODO: highest_bank_bit = 2 for LP_DDR4 */
+ .highest_bank_bit = 3,
+ .macrotile_mode = true,
+ /* TODO: Add mdss_reg_bus_bw with real value */
+};
+
+static const struct of_device_id qcom_ubwc_configs[] __maybe_unused = {
+ { .compatible = "qcom,apq8096", .data = &msm8998_data },
+ { .compatible = "qcom,msm8917", .data = &msm8937_data },
+ { .compatible = "qcom,msm8937", .data = &msm8937_data },
+ { .compatible = "qcom,msm8953", .data = &msm8937_data },
+ { .compatible = "qcom,msm8956", .data = &msm8937_data },
+ { .compatible = "qcom,msm8976", .data = &msm8937_data },
+ { .compatible = "qcom,msm8996", .data = &msm8998_data },
+ { .compatible = "qcom,msm8998", .data = &msm8998_data },
+ { .compatible = "qcom,qcm2290", .data = &qcm2290_data, },
+ { .compatible = "qcom,qcm6490", .data = &sc7280_data, },
+ { .compatible = "qcom,sa8155p", .data = &sm8150_data, },
+ { .compatible = "qcom,sa8540p", .data = &sc8280xp_data, },
+ { .compatible = "qcom,sa8775p", .data = &sa8775p_data, },
+ { .compatible = "qcom,sc7180", .data = &sc7180_data },
+ { .compatible = "qcom,sc7280", .data = &sc7280_data, },
+ { .compatible = "qcom,sc8180x", .data = &sc8180x_data, },
+ { .compatible = "qcom,sc8280xp", .data = &sc8280xp_data, },
+ { .compatible = "qcom,sdm630", .data = &msm8937_data },
+ { .compatible = "qcom,sdm636", .data = &msm8937_data },
+ { .compatible = "qcom,sdm660", .data = &msm8937_data },
+ { .compatible = "qcom,sdm670", .data = &sdm670_data, },
+ { .compatible = "qcom,sdm845", .data = &sdm845_data, },
+ { .compatible = "qcom,sm4250", .data = &sm6115_data, },
+ { .compatible = "qcom,sm6115", .data = &sm6115_data, },
+ { .compatible = "qcom,sm6125", .data = &sm6125_data, },
+ { .compatible = "qcom,sm6150", .data = &sm6150_data, },
+ { .compatible = "qcom,sm6350", .data = &sm6350_data, },
+ { .compatible = "qcom,sm6375", .data = &sm6350_data, },
+ { .compatible = "qcom,sm7125", .data = &sc7180_data },
+ { .compatible = "qcom,sm7150", .data = &sm7150_data, },
+ { .compatible = "qcom,sm8150", .data = &sm8150_data, },
+ { .compatible = "qcom,sm8250", .data = &sm8250_data, },
+ { .compatible = "qcom,sm8350", .data = &sm8350_data, },
+ { .compatible = "qcom,sm8450", .data = &sm8350_data, },
+ { .compatible = "qcom,sm8550", .data = &sm8550_data, },
+ { .compatible = "qcom,sm8650", .data = &sm8550_data, },
+ { .compatible = "qcom,x1e80100", .data = &x1e80100_data, },
+ { .compatible = "qcom,x1p42100", .data = &x1e80100_data, },
+ { }
+};
+
+const struct qcom_ubwc_cfg_data *qcom_ubwc_config_get_data(void)
+{
+ const struct of_device_id *match;
+ struct device_node *root;
+
+ root = of_find_node_by_path("/");
+ if (!root)
+ return ERR_PTR(-ENODEV);
+
+ match = of_match_node(qcom_ubwc_configs, root);
+ of_node_put(root);
+ if (!match) {
+ pr_err("Couldn't find UBWC config data for this platform!\n");
+ return ERR_PTR(-EINVAL);
+ }
+
+ return match->data;
+}
diff --git a/include/linux/soc/qcom/ubwc.h b/include/linux/soc/qcom/ubwc.h
new file mode 100644
index 0000000000000000000000000000000000000000..450106e6aea06f9f752bb7312ec3074e375eee4d
--- /dev/null
+++ b/include/linux/soc/qcom/ubwc.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2018, The Linux Foundation
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef __QCOM_UBWC_H__
+#define __QCOM_UBWC_H__
+
+#include <linux/types.h>
+
+struct qcom_ubwc_cfg_data {
+ u32 ubwc_enc_version;
+ /* Can be read from MDSS_BASE + 0x58 */
+ u32 ubwc_dec_version;
+ u32 ubwc_swizzle;
+ int highest_bank_bit;
+ bool ubwc_bank_spread;
+ bool macrotile_mode;
+ u32 mdss_reg_bus_bw;
+};
+
+#define UBWC_1_0 0x10000000
+#define UBWC_2_0 0x20000000
+#define UBWC_3_0 0x30000000
+#define UBWC_4_0 0x40000000
+#define UBWC_4_3 0x40030000
+
+const struct qcom_ubwc_cfg_data *qcom_ubwc_config_get_data(void);
+
+#endif /* __QCOM_UBWC_H__ */
--
2.49.0
^ permalink raw reply related [flat|nested] 43+ messages in thread* Re: [PATCH RFT 01/14] soc: qcom: Add UBWC config provider
2025-05-08 18:12 ` [PATCH RFT 01/14] soc: qcom: Add UBWC config provider Konrad Dybcio
@ 2025-05-08 20:12 ` Connor Abbott
2025-05-09 12:28 ` Konrad Dybcio
2025-05-11 22:21 ` Bjorn Andersson
1 sibling, 1 reply; 43+ messages in thread
From: Connor Abbott @ 2025-05-08 20:12 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Bjorn Andersson, Rob Clark, Abhinav Kumar, Dmitry Baryshkov,
Akhil P Oommen, Sean Paul, David Airlie, Simona Vetter,
Marijn Suijten, linux-kernel, linux-arm-msm, dri-devel, freedreno,
Konrad Dybcio
On Thu, May 8, 2025 at 2:13 PM Konrad Dybcio <konradybcio@kernel.org> wrote:
>
> From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>
> Add a file that will serve as a single source of truth for UBWC
> configuration data for various multimedia blocks.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> ---
> drivers/soc/qcom/Kconfig | 8 ++
> drivers/soc/qcom/Makefile | 1 +
> drivers/soc/qcom/ubwc_config.c | 255 +++++++++++++++++++++++++++++++++++++++++
> include/linux/soc/qcom/ubwc.h | 31 +++++
> 4 files changed, 295 insertions(+)
>
> diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig
> index 58e63cf0036ba8554e4082da5184a620ca807a9e..2caadbbcf8307ff94f5afbdd1481e5e5e291749f 100644
> --- a/drivers/soc/qcom/Kconfig
> +++ b/drivers/soc/qcom/Kconfig
> @@ -296,3 +296,11 @@ config QCOM_PBS
> PBS trigger event to the PBS RAM.
>
> endmenu
> +
> +config QCOM_UBWC_CONFIG
> + tristate
> + help
> + Most Qualcomm SoCs feature a number of Universal Bandwidth Compression
> + (UBWC) engines across various IP blocks, which need to be initialized
> + with coherent configuration data. This module functions as a single
> + source of truth for that information.
> diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile
> index acbca2ab5cc2a9ab3dce1ff38efd048ba2fab31e..b7f1d2a5736748b8772c090fd24462fa91f321c6 100644
> --- a/drivers/soc/qcom/Makefile
> +++ b/drivers/soc/qcom/Makefile
> @@ -39,3 +39,4 @@ obj-$(CONFIG_QCOM_ICC_BWMON) += icc-bwmon.o
> qcom_ice-objs += ice.o
> obj-$(CONFIG_QCOM_INLINE_CRYPTO_ENGINE) += qcom_ice.o
> obj-$(CONFIG_QCOM_PBS) += qcom-pbs.o
> +obj-$(CONFIG_QCOM_UBWC_CONFIG) += ubwc_config.o
> diff --git a/drivers/soc/qcom/ubwc_config.c b/drivers/soc/qcom/ubwc_config.c
> new file mode 100644
> index 0000000000000000000000000000000000000000..3f81fb2aab284dc9a5bcf53e5d638aaba44b6f2d
> --- /dev/null
> +++ b/drivers/soc/qcom/ubwc_config.c
> @@ -0,0 +1,255 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
> + */
> +
> +#include <linux/debugfs.h>
> +#include <linux/io.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/platform_device.h>
> +
> +#include <linux/soc/qcom/ubwc.h>
> +
> +static const struct qcom_ubwc_cfg_data msm8937_data = {
> + .ubwc_enc_version = UBWC_1_0,
> + .ubwc_dec_version = UBWC_1_0,
> + .highest_bank_bit = 1,
> + .mdss_reg_bus_bw = 76800,
> +};
> +
> +static const struct qcom_ubwc_cfg_data msm8998_data = {
> + .ubwc_enc_version = UBWC_1_0,
> + .ubwc_dec_version = UBWC_1_0,
> + .highest_bank_bit = 2,
> + .mdss_reg_bus_bw = 76800,
> +};
> +
> +static const struct qcom_ubwc_cfg_data qcm2290_data = {
> + /* no UBWC */
> + .highest_bank_bit = 2,
> + .mdss_reg_bus_bw = 76800,
> +};
> +
> +static const struct qcom_ubwc_cfg_data sa8775p_data = {
> + .ubwc_enc_version = UBWC_4_0,
> + .ubwc_dec_version = UBWC_4_0,
> + .ubwc_swizzle = 4,
> + .ubwc_bank_spread = true,
> + .highest_bank_bit = 0,
> + .macrotile_mode = true,
> + .mdss_reg_bus_bw = 74000,
> +};
> +
> +static const struct qcom_ubwc_cfg_data sar2130p_data = {
> + .ubwc_enc_version = UBWC_3_0, /* 4.0.2 in hw */
> + .ubwc_dec_version = UBWC_4_3,
> + .ubwc_swizzle = 6,
> + .ubwc_bank_spread = true,
> + .highest_bank_bit = 0,
> + .macrotile_mode = true,
> + .mdss_reg_bus_bw = 74000,
> +};
> +
> +static const struct qcom_ubwc_cfg_data sc7180_data = {
> + .ubwc_enc_version = UBWC_2_0,
> + .ubwc_dec_version = UBWC_2_0,
> + .ubwc_swizzle = 6,
> + .ubwc_bank_spread = true,
> + .highest_bank_bit = 1,
> + .mdss_reg_bus_bw = 76800,
> +};
> +
> +static const struct qcom_ubwc_cfg_data sc7280_data = {
> + .ubwc_enc_version = UBWC_3_0,
> + .ubwc_dec_version = UBWC_4_0,
> + .ubwc_swizzle = 6,
> + .ubwc_bank_spread = true,
> + .highest_bank_bit = 1,
> + .macrotile_mode = true,
> + .mdss_reg_bus_bw = 74000,
> +};
> +
> +static const struct qcom_ubwc_cfg_data sc8180x_data = {
> + .ubwc_enc_version = UBWC_3_0,
> + .ubwc_dec_version = UBWC_3_0,
> + .highest_bank_bit = 3,
> + .macrotile_mode = true,
> + .mdss_reg_bus_bw = 76800,
> +};
> +
> +static const struct qcom_ubwc_cfg_data sc8280xp_data = {
> + .ubwc_enc_version = UBWC_4_0,
> + .ubwc_dec_version = UBWC_4_0,
> + .ubwc_swizzle = 6,
> + .ubwc_bank_spread = true,
> + .highest_bank_bit = 3,
> + .macrotile_mode = true,
> + .mdss_reg_bus_bw = 76800,
> +};
> +
> +static const struct qcom_ubwc_cfg_data sdm670_data = {
> + .ubwc_enc_version = UBWC_2_0,
> + .ubwc_dec_version = UBWC_2_0,
> + .highest_bank_bit = 1,
> + .mdss_reg_bus_bw = 76800,
> +};
> +
> +static const struct qcom_ubwc_cfg_data sdm845_data = {
> + .ubwc_enc_version = UBWC_2_0,
> + .ubwc_dec_version = UBWC_2_0,
> + .highest_bank_bit = 2,
> + .mdss_reg_bus_bw = 76800,
> +};
> +
> +static const struct qcom_ubwc_cfg_data sm6115_data = {
> + .ubwc_enc_version = UBWC_1_0,
> + .ubwc_dec_version = UBWC_2_0,
> + .ubwc_swizzle = 7,
> + .ubwc_bank_spread = true,
> + .highest_bank_bit = 1,
> + .mdss_reg_bus_bw = 76800,
> +};
> +
> +static const struct qcom_ubwc_cfg_data sm6125_data = {
> + .ubwc_enc_version = UBWC_1_0,
> + .ubwc_dec_version = UBWC_3_0,
> + .ubwc_swizzle = 1,
> + .highest_bank_bit = 1,
> +};
> +
> +static const struct qcom_ubwc_cfg_data sm6150_data = {
> + .ubwc_enc_version = UBWC_2_0,
> + .ubwc_dec_version = UBWC_2_0,
> + .highest_bank_bit = 1,
> + .mdss_reg_bus_bw = 76800,
> +};
> +
> +static const struct qcom_ubwc_cfg_data sm6350_data = {
> + .ubwc_enc_version = UBWC_2_0,
> + .ubwc_dec_version = UBWC_2_0,
> + .ubwc_swizzle = 6,
> + .ubwc_bank_spread = true,
> + .highest_bank_bit = 1,
> + .mdss_reg_bus_bw = 76800,
> +};
> +
> +static const struct qcom_ubwc_cfg_data sm7150_data = {
> + .ubwc_enc_version = UBWC_2_0,
> + .ubwc_dec_version = UBWC_2_0,
> + .highest_bank_bit = 1,
> + .mdss_reg_bus_bw = 76800,
> +};
> +
> +static const struct qcom_ubwc_cfg_data sm8150_data = {
> + .ubwc_enc_version = UBWC_3_0,
> + .ubwc_dec_version = UBWC_3_0,
> + .highest_bank_bit = 2,
> + .mdss_reg_bus_bw = 76800,
> +};
> +
> +static const struct qcom_ubwc_cfg_data sm8250_data = {
> + .ubwc_enc_version = UBWC_4_0,
> + .ubwc_dec_version = UBWC_4_0,
> + .ubwc_swizzle = 6,
> + .ubwc_bank_spread = true,
> + /* TODO: highest_bank_bit = 2 for LP_DDR4 */
> + .highest_bank_bit = 3,
> + .macrotile_mode = true,
> + .mdss_reg_bus_bw = 76800,
> +};
> +
> +static const struct qcom_ubwc_cfg_data sm8350_data = {
> + .ubwc_enc_version = UBWC_4_0,
> + .ubwc_dec_version = UBWC_4_0,
> + .ubwc_swizzle = 6,
> + .ubwc_bank_spread = true,
> + /* TODO: highest_bank_bit = 2 for LP_DDR4 */
> + .highest_bank_bit = 3,
> + .macrotile_mode = true,
> + .mdss_reg_bus_bw = 74000,
> +};
> +
> +static const struct qcom_ubwc_cfg_data sm8550_data = {
> + .ubwc_enc_version = UBWC_4_0,
> + .ubwc_dec_version = UBWC_4_3,
> + .ubwc_swizzle = 6,
> + .ubwc_bank_spread = true,
> + /* TODO: highest_bank_bit = 2 for LP_DDR4 */
> + .highest_bank_bit = 3,
> + .macrotile_mode = true,
> + .mdss_reg_bus_bw = 57000,
> +};
> +
> +static const struct qcom_ubwc_cfg_data x1e80100_data = {
> + .ubwc_enc_version = UBWC_4_0,
> + .ubwc_dec_version = UBWC_4_3,
> + .ubwc_swizzle = 6,
> + .ubwc_bank_spread = true,
> + /* TODO: highest_bank_bit = 2 for LP_DDR4 */
> + .highest_bank_bit = 3,
> + .macrotile_mode = true,
> + /* TODO: Add mdss_reg_bus_bw with real value */
> +};
> +
> +static const struct of_device_id qcom_ubwc_configs[] __maybe_unused = {
> + { .compatible = "qcom,apq8096", .data = &msm8998_data },
> + { .compatible = "qcom,msm8917", .data = &msm8937_data },
> + { .compatible = "qcom,msm8937", .data = &msm8937_data },
> + { .compatible = "qcom,msm8953", .data = &msm8937_data },
> + { .compatible = "qcom,msm8956", .data = &msm8937_data },
> + { .compatible = "qcom,msm8976", .data = &msm8937_data },
> + { .compatible = "qcom,msm8996", .data = &msm8998_data },
> + { .compatible = "qcom,msm8998", .data = &msm8998_data },
> + { .compatible = "qcom,qcm2290", .data = &qcm2290_data, },
> + { .compatible = "qcom,qcm6490", .data = &sc7280_data, },
> + { .compatible = "qcom,sa8155p", .data = &sm8150_data, },
> + { .compatible = "qcom,sa8540p", .data = &sc8280xp_data, },
> + { .compatible = "qcom,sa8775p", .data = &sa8775p_data, },
> + { .compatible = "qcom,sc7180", .data = &sc7180_data },
> + { .compatible = "qcom,sc7280", .data = &sc7280_data, },
> + { .compatible = "qcom,sc8180x", .data = &sc8180x_data, },
> + { .compatible = "qcom,sc8280xp", .data = &sc8280xp_data, },
> + { .compatible = "qcom,sdm630", .data = &msm8937_data },
> + { .compatible = "qcom,sdm636", .data = &msm8937_data },
> + { .compatible = "qcom,sdm660", .data = &msm8937_data },
> + { .compatible = "qcom,sdm670", .data = &sdm670_data, },
> + { .compatible = "qcom,sdm845", .data = &sdm845_data, },
> + { .compatible = "qcom,sm4250", .data = &sm6115_data, },
> + { .compatible = "qcom,sm6115", .data = &sm6115_data, },
> + { .compatible = "qcom,sm6125", .data = &sm6125_data, },
> + { .compatible = "qcom,sm6150", .data = &sm6150_data, },
> + { .compatible = "qcom,sm6350", .data = &sm6350_data, },
> + { .compatible = "qcom,sm6375", .data = &sm6350_data, },
> + { .compatible = "qcom,sm7125", .data = &sc7180_data },
> + { .compatible = "qcom,sm7150", .data = &sm7150_data, },
> + { .compatible = "qcom,sm8150", .data = &sm8150_data, },
> + { .compatible = "qcom,sm8250", .data = &sm8250_data, },
> + { .compatible = "qcom,sm8350", .data = &sm8350_data, },
> + { .compatible = "qcom,sm8450", .data = &sm8350_data, },
> + { .compatible = "qcom,sm8550", .data = &sm8550_data, },
> + { .compatible = "qcom,sm8650", .data = &sm8550_data, },
> + { .compatible = "qcom,x1e80100", .data = &x1e80100_data, },
> + { .compatible = "qcom,x1p42100", .data = &x1e80100_data, },
> + { }
> +};
> +
> +const struct qcom_ubwc_cfg_data *qcom_ubwc_config_get_data(void)
> +{
> + const struct of_device_id *match;
> + struct device_node *root;
> +
> + root = of_find_node_by_path("/");
> + if (!root)
> + return ERR_PTR(-ENODEV);
> +
> + match = of_match_node(qcom_ubwc_configs, root);
> + of_node_put(root);
> + if (!match) {
> + pr_err("Couldn't find UBWC config data for this platform!\n");
> + return ERR_PTR(-EINVAL);
> + }
> +
> + return match->data;
> +}
> diff --git a/include/linux/soc/qcom/ubwc.h b/include/linux/soc/qcom/ubwc.h
> new file mode 100644
> index 0000000000000000000000000000000000000000..450106e6aea06f9f752bb7312ec3074e375eee4d
> --- /dev/null
> +++ b/include/linux/soc/qcom/ubwc.h
> @@ -0,0 +1,31 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (c) 2018, The Linux Foundation
> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
> + */
> +
> +#ifndef __QCOM_UBWC_H__
> +#define __QCOM_UBWC_H__
> +
> +#include <linux/types.h>
> +
> +struct qcom_ubwc_cfg_data {
> + u32 ubwc_enc_version;
> + /* Can be read from MDSS_BASE + 0x58 */
> + u32 ubwc_dec_version;
> + u32 ubwc_swizzle;
> + int highest_bank_bit;
> + bool ubwc_bank_spread;
> + bool macrotile_mode;
> + u32 mdss_reg_bus_bw;
This doesn't really seem relevant to UBWC?
> +};
The comments should be copied over from the Adreno struct. That was
the main way the meaning of most of these was documented and you're
deleting it here.
> +
> +#define UBWC_1_0 0x10000000
> +#define UBWC_2_0 0x20000000
> +#define UBWC_3_0 0x30000000
> +#define UBWC_4_0 0x40000000
> +#define UBWC_4_3 0x40030000
> +
> +const struct qcom_ubwc_cfg_data *qcom_ubwc_config_get_data(void);
> +
> +#endif /* __QCOM_UBWC_H__ */
>
> --
> 2.49.0
>
^ permalink raw reply [flat|nested] 43+ messages in thread* Re: [PATCH RFT 01/14] soc: qcom: Add UBWC config provider
2025-05-08 20:12 ` Connor Abbott
@ 2025-05-09 12:28 ` Konrad Dybcio
2025-05-11 21:13 ` Dmitry Baryshkov
0 siblings, 1 reply; 43+ messages in thread
From: Konrad Dybcio @ 2025-05-09 12:28 UTC (permalink / raw)
To: Connor Abbott, Konrad Dybcio
Cc: Bjorn Andersson, Rob Clark, Abhinav Kumar, Dmitry Baryshkov,
Akhil P Oommen, Sean Paul, David Airlie, Simona Vetter,
Marijn Suijten, linux-kernel, linux-arm-msm, dri-devel, freedreno
On 5/8/25 10:12 PM, Connor Abbott wrote:
> On Thu, May 8, 2025 at 2:13 PM Konrad Dybcio <konradybcio@kernel.org> wrote:
>>
>> From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>>
>> Add a file that will serve as a single source of truth for UBWC
>> configuration data for various multimedia blocks.
>>
>> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>> ---
[...]
>> +struct qcom_ubwc_cfg_data {
>> + u32 ubwc_enc_version;
>> + /* Can be read from MDSS_BASE + 0x58 */
>> + u32 ubwc_dec_version;
>> + u32 ubwc_swizzle;
>> + int highest_bank_bit;
>> + bool ubwc_bank_spread;
>> + bool macrotile_mode;
>> + u32 mdss_reg_bus_bw;
>
> This doesn't really seem relevant to UBWC?
I'll admit I just took it with the rest of properties for a simpler transition.
Generally, we could ma-a-a-aybe just make up a common value and pray it doesn't
break anything, as we're taking numbers that translate to ANYTHING_ABOVE_OFF or
ANYTHING_ABOVE_OFF_PLUS_1 in most cases wrt a cpu-ipblock path.
>
>> +};
>
> The comments should be copied over from the Adreno struct. That was
> the main way the meaning of most of these was documented and you're
> deleting it here.
I'll do that.
Konrad
^ permalink raw reply [flat|nested] 43+ messages in thread* Re: [PATCH RFT 01/14] soc: qcom: Add UBWC config provider
2025-05-09 12:28 ` Konrad Dybcio
@ 2025-05-11 21:13 ` Dmitry Baryshkov
2025-05-12 8:57 ` Dmitry Baryshkov
0 siblings, 1 reply; 43+ messages in thread
From: Dmitry Baryshkov @ 2025-05-11 21:13 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Connor Abbott, Konrad Dybcio, Bjorn Andersson, Rob Clark,
Abhinav Kumar, Akhil P Oommen, Sean Paul, David Airlie,
Simona Vetter, Marijn Suijten, linux-kernel, linux-arm-msm,
dri-devel, freedreno
On Fri, May 09, 2025 at 02:28:55PM +0200, Konrad Dybcio wrote:
> On 5/8/25 10:12 PM, Connor Abbott wrote:
> > On Thu, May 8, 2025 at 2:13 PM Konrad Dybcio <konradybcio@kernel.org> wrote:
> >>
> >> From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> >>
> >> Add a file that will serve as a single source of truth for UBWC
> >> configuration data for various multimedia blocks.
> >>
> >> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> >> ---
>
> [...]
>
> >> +struct qcom_ubwc_cfg_data {
> >> + u32 ubwc_enc_version;
> >> + /* Can be read from MDSS_BASE + 0x58 */
> >> + u32 ubwc_dec_version;
> >> + u32 ubwc_swizzle;
> >> + int highest_bank_bit;
> >> + bool ubwc_bank_spread;
> >> + bool macrotile_mode;
> >> + u32 mdss_reg_bus_bw;
> >
> > This doesn't really seem relevant to UBWC?
>
> I'll admit I just took it with the rest of properties for a simpler transition.
>
> Generally, we could ma-a-a-aybe just make up a common value and pray it doesn't
> break anything, as we're taking numbers that translate to ANYTHING_ABOVE_OFF or
> ANYTHING_ABOVE_OFF_PLUS_1 in most cases wrt a cpu-ipblock path.
I'd rather not do that. Let me check if I can cook it on top of your
series.
>
> >
> >> +};
> >
> > The comments should be copied over from the Adreno struct. That was
> > the main way the meaning of most of these was documented and you're
> > deleting it here.
>
> I'll do that.
>
> Konrad
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 43+ messages in thread* Re: [PATCH RFT 01/14] soc: qcom: Add UBWC config provider
2025-05-11 21:13 ` Dmitry Baryshkov
@ 2025-05-12 8:57 ` Dmitry Baryshkov
0 siblings, 0 replies; 43+ messages in thread
From: Dmitry Baryshkov @ 2025-05-12 8:57 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Connor Abbott, Konrad Dybcio, Bjorn Andersson, Rob Clark,
Abhinav Kumar, Akhil P Oommen, Sean Paul, David Airlie,
Simona Vetter, Marijn Suijten, linux-kernel, linux-arm-msm,
dri-devel, freedreno
[-- Attachment #1: Type: text/plain, Size: 1440 bytes --]
On Mon, May 12, 2025 at 12:13:40AM +0300, Dmitry Baryshkov wrote:
> On Fri, May 09, 2025 at 02:28:55PM +0200, Konrad Dybcio wrote:
> > On 5/8/25 10:12 PM, Connor Abbott wrote:
> > > On Thu, May 8, 2025 at 2:13 PM Konrad Dybcio <konradybcio@kernel.org> wrote:
> > >>
> > >> From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> > >>
> > >> Add a file that will serve as a single source of truth for UBWC
> > >> configuration data for various multimedia blocks.
> > >>
> > >> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> > >> ---
> >
> > [...]
> >
> > >> +struct qcom_ubwc_cfg_data {
> > >> + u32 ubwc_enc_version;
> > >> + /* Can be read from MDSS_BASE + 0x58 */
> > >> + u32 ubwc_dec_version;
> > >> + u32 ubwc_swizzle;
> > >> + int highest_bank_bit;
> > >> + bool ubwc_bank_spread;
> > >> + bool macrotile_mode;
> > >> + u32 mdss_reg_bus_bw;
> > >
> > > This doesn't really seem relevant to UBWC?
> >
> > I'll admit I just took it with the rest of properties for a simpler transition.
> >
> > Generally, we could ma-a-a-aybe just make up a common value and pray it doesn't
> > break anything, as we're taking numbers that translate to ANYTHING_ABOVE_OFF or
> > ANYTHING_ABOVE_OFF_PLUS_1 in most cases wrt a cpu-ipblock path.
>
> I'd rather not do that. Let me check if I can cook it on top of your
> series.
See the attached patch.
--
With best wishes
Dmitry
[-- Attachment #2: 0001-drm-msm-bring-MDSS-bandwidth-data-back-to-msm_mdss.patch --]
[-- Type: text/x-diff, Size: 10635 bytes --]
From cf3fe1a79c035dbf1b62143fe4219b15096bb8b1 Mon Sep 17 00:00:00 2001
From: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Date: Mon, 12 May 2025 11:55:59 +0300
Subject: [PATCH] drm/msm: bring MDSS bandwidth data back to msm_mdss
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/gpu/drm/msm/msm_mdss.c | 85 +++++++++++++++++++++-------------
drivers/soc/qcom/ubwc_config.c | 20 --------
include/linux/soc/qcom/ubwc.h | 1 -
3 files changed, 54 insertions(+), 52 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
index 71f5440994cc..a71597dc1e4d 100644
--- a/drivers/gpu/drm/msm/msm_mdss.c
+++ b/drivers/gpu/drm/msm/msm_mdss.c
@@ -24,7 +24,9 @@
#define MIN_IB_BW 400000000UL /* Min ib vote 400MB */
-#define DEFAULT_REG_BW 153600 /* Used in mdss fbdev driver */
+struct msm_mdss_data {
+ u32 reg_bus_bw;
+};
struct msm_mdss {
struct device *dev;
@@ -38,6 +40,7 @@ struct msm_mdss {
struct irq_domain *domain;
} irq_controller;
const struct qcom_ubwc_cfg_data *mdss_data;
+ u32 reg_bus_bw;
struct icc_path *mdp_path[2];
u32 num_mdp_paths;
struct icc_path *reg_bus_path;
@@ -235,12 +238,8 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss)
for (i = 0; i < msm_mdss->num_mdp_paths; i++)
icc_set_bw(msm_mdss->mdp_path[i], 0, Bps_to_icc(MIN_IB_BW));
- if (msm_mdss->mdss_data && msm_mdss->mdss_data->mdss_reg_bus_bw)
- icc_set_bw(msm_mdss->reg_bus_path, 0,
- msm_mdss->mdss_data->mdss_reg_bus_bw);
- else
- icc_set_bw(msm_mdss->reg_bus_path, 0,
- DEFAULT_REG_BW);
+ icc_set_bw(msm_mdss->reg_bus_path, 0,
+ msm_mdss->reg_bus_bw);
ret = clk_bulk_prepare_enable(msm_mdss->num_clocks, msm_mdss->clocks);
if (ret) {
@@ -376,6 +375,7 @@ static int mdp5_mdss_parse_clock(struct platform_device *pdev, struct clk_bulk_d
static struct msm_mdss *msm_mdss_init(struct platform_device *pdev, bool is_mdp5)
{
+ const struct msm_mdss_data *mdss_data;
struct msm_mdss *msm_mdss;
int ret;
int irq;
@@ -392,6 +392,12 @@ static struct msm_mdss *msm_mdss_init(struct platform_device *pdev, bool is_mdp5
if (IS_ERR(msm_mdss->mdss_data))
return ERR_CAST(msm_mdss->mdss_data);
+ mdss_data = of_device_get_match_data(&pdev->dev);
+ if (!mdss_data)
+ return ERR_PTR(-EINVAL);
+
+ msm_mdss->reg_bus_bw = mdss_data->reg_bus_bw;
+
msm_mdss->mmio = devm_platform_ioremap_resource_byname(pdev, is_mdp5 ? "mdss_phys" : "mdss");
if (IS_ERR(msm_mdss->mmio))
return ERR_CAST(msm_mdss->mmio);
@@ -509,31 +515,48 @@ static void mdss_remove(struct platform_device *pdev)
msm_mdss_destroy(mdss);
}
+static const struct msm_mdss_data data_57k = {
+ .reg_bus_bw = 57000,
+};
+
+static const struct msm_mdss_data data_74k = {
+ .reg_bus_bw = 74000,
+};
+
+static const struct msm_mdss_data data_76k8 = {
+ .reg_bus_bw = 76800,
+};
+
+static const struct msm_mdss_data data_153k6 = {
+ .reg_bus_bw = 153600,
+};
+
static const struct of_device_id mdss_dt_match[] = {
- { .compatible = "qcom,mdss" },
- { .compatible = "qcom,msm8998-mdss" },
- { .compatible = "qcom,qcm2290-mdss" },
- { .compatible = "qcom,sa8775p-mdss" },
- { .compatible = "qcom,sar2130p-mdss" },
- { .compatible = "qcom,sdm670-mdss" },
- { .compatible = "qcom,sdm845-mdss" },
- { .compatible = "qcom,sc7180-mdss" },
- { .compatible = "qcom,sc7280-mdss" },
- { .compatible = "qcom,sc8180x-mdss" },
- { .compatible = "qcom,sc8280xp-mdss" },
- { .compatible = "qcom,sm6115-mdss" },
- { .compatible = "qcom,sm6125-mdss" },
- { .compatible = "qcom,sm6150-mdss" },
- { .compatible = "qcom,sm6350-mdss" },
- { .compatible = "qcom,sm6375-mdss" },
- { .compatible = "qcom,sm7150-mdss" },
- { .compatible = "qcom,sm8150-mdss" },
- { .compatible = "qcom,sm8250-mdss" },
- { .compatible = "qcom,sm8350-mdss" },
- { .compatible = "qcom,sm8450-mdss" },
- { .compatible = "qcom,sm8550-mdss" },
- { .compatible = "qcom,sm8650-mdss" },
- { .compatible = "qcom,x1e80100-mdss"},
+ { .compatible = "qcom,mdss", .data = &data_153k6 },
+ { .compatible = "qcom,msm8998-mdss", .data = &data_76k8 },
+ { .compatible = "qcom,qcm2290-mdss", .data = &data_76k8 },
+ { .compatible = "qcom,sa8775p-mdss", .data = &data_74k},
+ { .compatible = "qcom,sar2130p-mdss", .data = &data_74k},
+ { .compatible = "qcom,sdm670-mdss", .data = &data_76k8 },
+ { .compatible = "qcom,sdm845-mdss", .data = &data_76k8 },
+ { .compatible = "qcom,sc7180-mdss", .data = &data_76k8 },
+ { .compatible = "qcom,sc7280-mdss", .data = &data_74k },
+ { .compatible = "qcom,sc8180x-mdss", .data = &data_76k8 },
+ { .compatible = "qcom,sc8280xp-mdss", .data = &data_76k8 },
+ { .compatible = "qcom,sm6115-mdss", .data = &data_76k8 },
+ { .compatible = "qcom,sm6125-mdss", .data = &data_76k8 },
+ { .compatible = "qcom,sm6150-mdss", .data = &data_76k8 },
+ { .compatible = "qcom,sm6350-mdss", .data = &data_76k8 },
+ { .compatible = "qcom,sm6375-mdss", .data = &data_76k8 },
+ { .compatible = "qcom,sm7150-mdss", .data = &data_76k8 },
+ { .compatible = "qcom,sm8150-mdss", .data = &data_76k8 },
+ { .compatible = "qcom,sm8250-mdss", .data = &data_76k8 },
+ { .compatible = "qcom,sm8350-mdss", .data = &data_74k },
+ { .compatible = "qcom,sm8450-mdss", .data = &data_74k },
+ { .compatible = "qcom,sm8550-mdss", .data = &data_57k },
+ { .compatible = "qcom,sm8650-mdss", .data = &data_57k },
+ /* TODO: x1e8: Add reg_bus_bw with real value */
+ { .compatible = "qcom,x1e80100-mdss", .data = &data_153k6 },
{}
};
MODULE_DEVICE_TABLE(of, mdss_dt_match);
diff --git a/drivers/soc/qcom/ubwc_config.c b/drivers/soc/qcom/ubwc_config.c
index 3f81fb2aab28..43c9e6facb73 100644
--- a/drivers/soc/qcom/ubwc_config.c
+++ b/drivers/soc/qcom/ubwc_config.c
@@ -16,20 +16,17 @@ static const struct qcom_ubwc_cfg_data msm8937_data = {
.ubwc_enc_version = UBWC_1_0,
.ubwc_dec_version = UBWC_1_0,
.highest_bank_bit = 1,
- .mdss_reg_bus_bw = 76800,
};
static const struct qcom_ubwc_cfg_data msm8998_data = {
.ubwc_enc_version = UBWC_1_0,
.ubwc_dec_version = UBWC_1_0,
.highest_bank_bit = 2,
- .mdss_reg_bus_bw = 76800,
};
static const struct qcom_ubwc_cfg_data qcm2290_data = {
/* no UBWC */
.highest_bank_bit = 2,
- .mdss_reg_bus_bw = 76800,
};
static const struct qcom_ubwc_cfg_data sa8775p_data = {
@@ -39,7 +36,6 @@ static const struct qcom_ubwc_cfg_data sa8775p_data = {
.ubwc_bank_spread = true,
.highest_bank_bit = 0,
.macrotile_mode = true,
- .mdss_reg_bus_bw = 74000,
};
static const struct qcom_ubwc_cfg_data sar2130p_data = {
@@ -49,7 +45,6 @@ static const struct qcom_ubwc_cfg_data sar2130p_data = {
.ubwc_bank_spread = true,
.highest_bank_bit = 0,
.macrotile_mode = true,
- .mdss_reg_bus_bw = 74000,
};
static const struct qcom_ubwc_cfg_data sc7180_data = {
@@ -58,7 +53,6 @@ static const struct qcom_ubwc_cfg_data sc7180_data = {
.ubwc_swizzle = 6,
.ubwc_bank_spread = true,
.highest_bank_bit = 1,
- .mdss_reg_bus_bw = 76800,
};
static const struct qcom_ubwc_cfg_data sc7280_data = {
@@ -68,7 +62,6 @@ static const struct qcom_ubwc_cfg_data sc7280_data = {
.ubwc_bank_spread = true,
.highest_bank_bit = 1,
.macrotile_mode = true,
- .mdss_reg_bus_bw = 74000,
};
static const struct qcom_ubwc_cfg_data sc8180x_data = {
@@ -76,7 +69,6 @@ static const struct qcom_ubwc_cfg_data sc8180x_data = {
.ubwc_dec_version = UBWC_3_0,
.highest_bank_bit = 3,
.macrotile_mode = true,
- .mdss_reg_bus_bw = 76800,
};
static const struct qcom_ubwc_cfg_data sc8280xp_data = {
@@ -86,21 +78,18 @@ static const struct qcom_ubwc_cfg_data sc8280xp_data = {
.ubwc_bank_spread = true,
.highest_bank_bit = 3,
.macrotile_mode = true,
- .mdss_reg_bus_bw = 76800,
};
static const struct qcom_ubwc_cfg_data sdm670_data = {
.ubwc_enc_version = UBWC_2_0,
.ubwc_dec_version = UBWC_2_0,
.highest_bank_bit = 1,
- .mdss_reg_bus_bw = 76800,
};
static const struct qcom_ubwc_cfg_data sdm845_data = {
.ubwc_enc_version = UBWC_2_0,
.ubwc_dec_version = UBWC_2_0,
.highest_bank_bit = 2,
- .mdss_reg_bus_bw = 76800,
};
static const struct qcom_ubwc_cfg_data sm6115_data = {
@@ -109,7 +98,6 @@ static const struct qcom_ubwc_cfg_data sm6115_data = {
.ubwc_swizzle = 7,
.ubwc_bank_spread = true,
.highest_bank_bit = 1,
- .mdss_reg_bus_bw = 76800,
};
static const struct qcom_ubwc_cfg_data sm6125_data = {
@@ -123,7 +111,6 @@ static const struct qcom_ubwc_cfg_data sm6150_data = {
.ubwc_enc_version = UBWC_2_0,
.ubwc_dec_version = UBWC_2_0,
.highest_bank_bit = 1,
- .mdss_reg_bus_bw = 76800,
};
static const struct qcom_ubwc_cfg_data sm6350_data = {
@@ -132,21 +119,18 @@ static const struct qcom_ubwc_cfg_data sm6350_data = {
.ubwc_swizzle = 6,
.ubwc_bank_spread = true,
.highest_bank_bit = 1,
- .mdss_reg_bus_bw = 76800,
};
static const struct qcom_ubwc_cfg_data sm7150_data = {
.ubwc_enc_version = UBWC_2_0,
.ubwc_dec_version = UBWC_2_0,
.highest_bank_bit = 1,
- .mdss_reg_bus_bw = 76800,
};
static const struct qcom_ubwc_cfg_data sm8150_data = {
.ubwc_enc_version = UBWC_3_0,
.ubwc_dec_version = UBWC_3_0,
.highest_bank_bit = 2,
- .mdss_reg_bus_bw = 76800,
};
static const struct qcom_ubwc_cfg_data sm8250_data = {
@@ -157,7 +141,6 @@ static const struct qcom_ubwc_cfg_data sm8250_data = {
/* TODO: highest_bank_bit = 2 for LP_DDR4 */
.highest_bank_bit = 3,
.macrotile_mode = true,
- .mdss_reg_bus_bw = 76800,
};
static const struct qcom_ubwc_cfg_data sm8350_data = {
@@ -168,7 +151,6 @@ static const struct qcom_ubwc_cfg_data sm8350_data = {
/* TODO: highest_bank_bit = 2 for LP_DDR4 */
.highest_bank_bit = 3,
.macrotile_mode = true,
- .mdss_reg_bus_bw = 74000,
};
static const struct qcom_ubwc_cfg_data sm8550_data = {
@@ -179,7 +161,6 @@ static const struct qcom_ubwc_cfg_data sm8550_data = {
/* TODO: highest_bank_bit = 2 for LP_DDR4 */
.highest_bank_bit = 3,
.macrotile_mode = true,
- .mdss_reg_bus_bw = 57000,
};
static const struct qcom_ubwc_cfg_data x1e80100_data = {
@@ -190,7 +171,6 @@ static const struct qcom_ubwc_cfg_data x1e80100_data = {
/* TODO: highest_bank_bit = 2 for LP_DDR4 */
.highest_bank_bit = 3,
.macrotile_mode = true,
- /* TODO: Add mdss_reg_bus_bw with real value */
};
static const struct of_device_id qcom_ubwc_configs[] __maybe_unused = {
diff --git a/include/linux/soc/qcom/ubwc.h b/include/linux/soc/qcom/ubwc.h
index 450106e6aea0..e78645fc090f 100644
--- a/include/linux/soc/qcom/ubwc.h
+++ b/include/linux/soc/qcom/ubwc.h
@@ -17,7 +17,6 @@ struct qcom_ubwc_cfg_data {
int highest_bank_bit;
bool ubwc_bank_spread;
bool macrotile_mode;
- u32 mdss_reg_bus_bw;
};
#define UBWC_1_0 0x10000000
--
2.39.5
^ permalink raw reply related [flat|nested] 43+ messages in thread
* Re: [PATCH RFT 01/14] soc: qcom: Add UBWC config provider
2025-05-08 18:12 ` [PATCH RFT 01/14] soc: qcom: Add UBWC config provider Konrad Dybcio
2025-05-08 20:12 ` Connor Abbott
@ 2025-05-11 22:21 ` Bjorn Andersson
1 sibling, 0 replies; 43+ messages in thread
From: Bjorn Andersson @ 2025-05-11 22:21 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Akhil P Oommen,
Sean Paul, David Airlie, Simona Vetter, Marijn Suijten,
linux-kernel, linux-arm-msm, dri-devel, freedreno, Konrad Dybcio
On Thu, May 08, 2025 at 08:12:33PM +0200, Konrad Dybcio wrote:
> From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>
I'd prefer this to contain some of the problem description from the
cover letter.
Regards,
Bjorn
> Add a file that will serve as a single source of truth for UBWC
> configuration data for various multimedia blocks.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> ---
> drivers/soc/qcom/Kconfig | 8 ++
> drivers/soc/qcom/Makefile | 1 +
> drivers/soc/qcom/ubwc_config.c | 255 +++++++++++++++++++++++++++++++++++++++++
> include/linux/soc/qcom/ubwc.h | 31 +++++
> 4 files changed, 295 insertions(+)
>
> diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig
> index 58e63cf0036ba8554e4082da5184a620ca807a9e..2caadbbcf8307ff94f5afbdd1481e5e5e291749f 100644
> --- a/drivers/soc/qcom/Kconfig
> +++ b/drivers/soc/qcom/Kconfig
> @@ -296,3 +296,11 @@ config QCOM_PBS
> PBS trigger event to the PBS RAM.
>
> endmenu
> +
> +config QCOM_UBWC_CONFIG
> + tristate
> + help
> + Most Qualcomm SoCs feature a number of Universal Bandwidth Compression
> + (UBWC) engines across various IP blocks, which need to be initialized
> + with coherent configuration data. This module functions as a single
> + source of truth for that information.
> diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile
> index acbca2ab5cc2a9ab3dce1ff38efd048ba2fab31e..b7f1d2a5736748b8772c090fd24462fa91f321c6 100644
> --- a/drivers/soc/qcom/Makefile
> +++ b/drivers/soc/qcom/Makefile
> @@ -39,3 +39,4 @@ obj-$(CONFIG_QCOM_ICC_BWMON) += icc-bwmon.o
> qcom_ice-objs += ice.o
> obj-$(CONFIG_QCOM_INLINE_CRYPTO_ENGINE) += qcom_ice.o
> obj-$(CONFIG_QCOM_PBS) += qcom-pbs.o
> +obj-$(CONFIG_QCOM_UBWC_CONFIG) += ubwc_config.o
> diff --git a/drivers/soc/qcom/ubwc_config.c b/drivers/soc/qcom/ubwc_config.c
> new file mode 100644
> index 0000000000000000000000000000000000000000..3f81fb2aab284dc9a5bcf53e5d638aaba44b6f2d
> --- /dev/null
> +++ b/drivers/soc/qcom/ubwc_config.c
> @@ -0,0 +1,255 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
> + */
> +
> +#include <linux/debugfs.h>
> +#include <linux/io.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/platform_device.h>
> +
> +#include <linux/soc/qcom/ubwc.h>
> +
> +static const struct qcom_ubwc_cfg_data msm8937_data = {
> + .ubwc_enc_version = UBWC_1_0,
> + .ubwc_dec_version = UBWC_1_0,
> + .highest_bank_bit = 1,
> + .mdss_reg_bus_bw = 76800,
> +};
> +
> +static const struct qcom_ubwc_cfg_data msm8998_data = {
> + .ubwc_enc_version = UBWC_1_0,
> + .ubwc_dec_version = UBWC_1_0,
> + .highest_bank_bit = 2,
> + .mdss_reg_bus_bw = 76800,
> +};
> +
> +static const struct qcom_ubwc_cfg_data qcm2290_data = {
> + /* no UBWC */
> + .highest_bank_bit = 2,
> + .mdss_reg_bus_bw = 76800,
> +};
> +
> +static const struct qcom_ubwc_cfg_data sa8775p_data = {
> + .ubwc_enc_version = UBWC_4_0,
> + .ubwc_dec_version = UBWC_4_0,
> + .ubwc_swizzle = 4,
> + .ubwc_bank_spread = true,
> + .highest_bank_bit = 0,
> + .macrotile_mode = true,
> + .mdss_reg_bus_bw = 74000,
> +};
> +
> +static const struct qcom_ubwc_cfg_data sar2130p_data = {
> + .ubwc_enc_version = UBWC_3_0, /* 4.0.2 in hw */
> + .ubwc_dec_version = UBWC_4_3,
> + .ubwc_swizzle = 6,
> + .ubwc_bank_spread = true,
> + .highest_bank_bit = 0,
> + .macrotile_mode = true,
> + .mdss_reg_bus_bw = 74000,
> +};
> +
> +static const struct qcom_ubwc_cfg_data sc7180_data = {
> + .ubwc_enc_version = UBWC_2_0,
> + .ubwc_dec_version = UBWC_2_0,
> + .ubwc_swizzle = 6,
> + .ubwc_bank_spread = true,
> + .highest_bank_bit = 1,
> + .mdss_reg_bus_bw = 76800,
> +};
> +
> +static const struct qcom_ubwc_cfg_data sc7280_data = {
> + .ubwc_enc_version = UBWC_3_0,
> + .ubwc_dec_version = UBWC_4_0,
> + .ubwc_swizzle = 6,
> + .ubwc_bank_spread = true,
> + .highest_bank_bit = 1,
> + .macrotile_mode = true,
> + .mdss_reg_bus_bw = 74000,
> +};
> +
> +static const struct qcom_ubwc_cfg_data sc8180x_data = {
> + .ubwc_enc_version = UBWC_3_0,
> + .ubwc_dec_version = UBWC_3_0,
> + .highest_bank_bit = 3,
> + .macrotile_mode = true,
> + .mdss_reg_bus_bw = 76800,
> +};
> +
> +static const struct qcom_ubwc_cfg_data sc8280xp_data = {
> + .ubwc_enc_version = UBWC_4_0,
> + .ubwc_dec_version = UBWC_4_0,
> + .ubwc_swizzle = 6,
> + .ubwc_bank_spread = true,
> + .highest_bank_bit = 3,
> + .macrotile_mode = true,
> + .mdss_reg_bus_bw = 76800,
> +};
> +
> +static const struct qcom_ubwc_cfg_data sdm670_data = {
> + .ubwc_enc_version = UBWC_2_0,
> + .ubwc_dec_version = UBWC_2_0,
> + .highest_bank_bit = 1,
> + .mdss_reg_bus_bw = 76800,
> +};
> +
> +static const struct qcom_ubwc_cfg_data sdm845_data = {
> + .ubwc_enc_version = UBWC_2_0,
> + .ubwc_dec_version = UBWC_2_0,
> + .highest_bank_bit = 2,
> + .mdss_reg_bus_bw = 76800,
> +};
> +
> +static const struct qcom_ubwc_cfg_data sm6115_data = {
> + .ubwc_enc_version = UBWC_1_0,
> + .ubwc_dec_version = UBWC_2_0,
> + .ubwc_swizzle = 7,
> + .ubwc_bank_spread = true,
> + .highest_bank_bit = 1,
> + .mdss_reg_bus_bw = 76800,
> +};
> +
> +static const struct qcom_ubwc_cfg_data sm6125_data = {
> + .ubwc_enc_version = UBWC_1_0,
> + .ubwc_dec_version = UBWC_3_0,
> + .ubwc_swizzle = 1,
> + .highest_bank_bit = 1,
> +};
> +
> +static const struct qcom_ubwc_cfg_data sm6150_data = {
> + .ubwc_enc_version = UBWC_2_0,
> + .ubwc_dec_version = UBWC_2_0,
> + .highest_bank_bit = 1,
> + .mdss_reg_bus_bw = 76800,
> +};
> +
> +static const struct qcom_ubwc_cfg_data sm6350_data = {
> + .ubwc_enc_version = UBWC_2_0,
> + .ubwc_dec_version = UBWC_2_0,
> + .ubwc_swizzle = 6,
> + .ubwc_bank_spread = true,
> + .highest_bank_bit = 1,
> + .mdss_reg_bus_bw = 76800,
> +};
> +
> +static const struct qcom_ubwc_cfg_data sm7150_data = {
> + .ubwc_enc_version = UBWC_2_0,
> + .ubwc_dec_version = UBWC_2_0,
> + .highest_bank_bit = 1,
> + .mdss_reg_bus_bw = 76800,
> +};
> +
> +static const struct qcom_ubwc_cfg_data sm8150_data = {
> + .ubwc_enc_version = UBWC_3_0,
> + .ubwc_dec_version = UBWC_3_0,
> + .highest_bank_bit = 2,
> + .mdss_reg_bus_bw = 76800,
> +};
> +
> +static const struct qcom_ubwc_cfg_data sm8250_data = {
> + .ubwc_enc_version = UBWC_4_0,
> + .ubwc_dec_version = UBWC_4_0,
> + .ubwc_swizzle = 6,
> + .ubwc_bank_spread = true,
> + /* TODO: highest_bank_bit = 2 for LP_DDR4 */
> + .highest_bank_bit = 3,
> + .macrotile_mode = true,
> + .mdss_reg_bus_bw = 76800,
> +};
> +
> +static const struct qcom_ubwc_cfg_data sm8350_data = {
> + .ubwc_enc_version = UBWC_4_0,
> + .ubwc_dec_version = UBWC_4_0,
> + .ubwc_swizzle = 6,
> + .ubwc_bank_spread = true,
> + /* TODO: highest_bank_bit = 2 for LP_DDR4 */
> + .highest_bank_bit = 3,
> + .macrotile_mode = true,
> + .mdss_reg_bus_bw = 74000,
> +};
> +
> +static const struct qcom_ubwc_cfg_data sm8550_data = {
> + .ubwc_enc_version = UBWC_4_0,
> + .ubwc_dec_version = UBWC_4_3,
> + .ubwc_swizzle = 6,
> + .ubwc_bank_spread = true,
> + /* TODO: highest_bank_bit = 2 for LP_DDR4 */
> + .highest_bank_bit = 3,
> + .macrotile_mode = true,
> + .mdss_reg_bus_bw = 57000,
> +};
> +
> +static const struct qcom_ubwc_cfg_data x1e80100_data = {
> + .ubwc_enc_version = UBWC_4_0,
> + .ubwc_dec_version = UBWC_4_3,
> + .ubwc_swizzle = 6,
> + .ubwc_bank_spread = true,
> + /* TODO: highest_bank_bit = 2 for LP_DDR4 */
> + .highest_bank_bit = 3,
> + .macrotile_mode = true,
> + /* TODO: Add mdss_reg_bus_bw with real value */
> +};
> +
> +static const struct of_device_id qcom_ubwc_configs[] __maybe_unused = {
> + { .compatible = "qcom,apq8096", .data = &msm8998_data },
> + { .compatible = "qcom,msm8917", .data = &msm8937_data },
> + { .compatible = "qcom,msm8937", .data = &msm8937_data },
> + { .compatible = "qcom,msm8953", .data = &msm8937_data },
> + { .compatible = "qcom,msm8956", .data = &msm8937_data },
> + { .compatible = "qcom,msm8976", .data = &msm8937_data },
> + { .compatible = "qcom,msm8996", .data = &msm8998_data },
> + { .compatible = "qcom,msm8998", .data = &msm8998_data },
> + { .compatible = "qcom,qcm2290", .data = &qcm2290_data, },
> + { .compatible = "qcom,qcm6490", .data = &sc7280_data, },
> + { .compatible = "qcom,sa8155p", .data = &sm8150_data, },
> + { .compatible = "qcom,sa8540p", .data = &sc8280xp_data, },
> + { .compatible = "qcom,sa8775p", .data = &sa8775p_data, },
> + { .compatible = "qcom,sc7180", .data = &sc7180_data },
> + { .compatible = "qcom,sc7280", .data = &sc7280_data, },
> + { .compatible = "qcom,sc8180x", .data = &sc8180x_data, },
> + { .compatible = "qcom,sc8280xp", .data = &sc8280xp_data, },
> + { .compatible = "qcom,sdm630", .data = &msm8937_data },
> + { .compatible = "qcom,sdm636", .data = &msm8937_data },
> + { .compatible = "qcom,sdm660", .data = &msm8937_data },
> + { .compatible = "qcom,sdm670", .data = &sdm670_data, },
> + { .compatible = "qcom,sdm845", .data = &sdm845_data, },
> + { .compatible = "qcom,sm4250", .data = &sm6115_data, },
> + { .compatible = "qcom,sm6115", .data = &sm6115_data, },
> + { .compatible = "qcom,sm6125", .data = &sm6125_data, },
> + { .compatible = "qcom,sm6150", .data = &sm6150_data, },
> + { .compatible = "qcom,sm6350", .data = &sm6350_data, },
> + { .compatible = "qcom,sm6375", .data = &sm6350_data, },
> + { .compatible = "qcom,sm7125", .data = &sc7180_data },
> + { .compatible = "qcom,sm7150", .data = &sm7150_data, },
> + { .compatible = "qcom,sm8150", .data = &sm8150_data, },
> + { .compatible = "qcom,sm8250", .data = &sm8250_data, },
> + { .compatible = "qcom,sm8350", .data = &sm8350_data, },
> + { .compatible = "qcom,sm8450", .data = &sm8350_data, },
> + { .compatible = "qcom,sm8550", .data = &sm8550_data, },
> + { .compatible = "qcom,sm8650", .data = &sm8550_data, },
> + { .compatible = "qcom,x1e80100", .data = &x1e80100_data, },
> + { .compatible = "qcom,x1p42100", .data = &x1e80100_data, },
> + { }
> +};
> +
> +const struct qcom_ubwc_cfg_data *qcom_ubwc_config_get_data(void)
> +{
> + const struct of_device_id *match;
> + struct device_node *root;
> +
> + root = of_find_node_by_path("/");
> + if (!root)
> + return ERR_PTR(-ENODEV);
> +
> + match = of_match_node(qcom_ubwc_configs, root);
> + of_node_put(root);
> + if (!match) {
> + pr_err("Couldn't find UBWC config data for this platform!\n");
> + return ERR_PTR(-EINVAL);
> + }
> +
> + return match->data;
> +}
> diff --git a/include/linux/soc/qcom/ubwc.h b/include/linux/soc/qcom/ubwc.h
> new file mode 100644
> index 0000000000000000000000000000000000000000..450106e6aea06f9f752bb7312ec3074e375eee4d
> --- /dev/null
> +++ b/include/linux/soc/qcom/ubwc.h
> @@ -0,0 +1,31 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (c) 2018, The Linux Foundation
> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
> + */
> +
> +#ifndef __QCOM_UBWC_H__
> +#define __QCOM_UBWC_H__
> +
> +#include <linux/types.h>
> +
> +struct qcom_ubwc_cfg_data {
> + u32 ubwc_enc_version;
> + /* Can be read from MDSS_BASE + 0x58 */
> + u32 ubwc_dec_version;
> + u32 ubwc_swizzle;
> + int highest_bank_bit;
> + bool ubwc_bank_spread;
> + bool macrotile_mode;
> + u32 mdss_reg_bus_bw;
> +};
> +
> +#define UBWC_1_0 0x10000000
> +#define UBWC_2_0 0x20000000
> +#define UBWC_3_0 0x30000000
> +#define UBWC_4_0 0x40000000
> +#define UBWC_4_3 0x40030000
> +
> +const struct qcom_ubwc_cfg_data *qcom_ubwc_config_get_data(void);
> +
> +#endif /* __QCOM_UBWC_H__ */
>
> --
> 2.49.0
>
^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH RFT 02/14] drm/msm: Use the central UBWC config database
2025-05-08 18:12 [RFT PATCH 00/14] Add a single source of truth for UBWC configuration data Konrad Dybcio
2025-05-08 18:12 ` [PATCH RFT 01/14] soc: qcom: Add UBWC config provider Konrad Dybcio
@ 2025-05-08 18:12 ` Konrad Dybcio
2025-05-08 18:12 ` [PATCH RFT 03/14] drm/msm/adreno: Offset the HBB value by 13 Konrad Dybcio
` (11 subsequent siblings)
13 siblings, 0 replies; 43+ messages in thread
From: Konrad Dybcio @ 2025-05-08 18:12 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Clark, Abhinav Kumar,
Dmitry Baryshkov, Akhil P Oommen, Sean Paul, David Airlie,
Simona Vetter
Cc: Marijn Suijten, linux-kernel, linux-arm-msm, dri-devel, freedreno,
Konrad Dybcio
From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
To reduce room for error, move to fetching the config from a central
source, so that the data programmed into the hardware is consistent
across all multimedia blocks that request it.
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
---
drivers/gpu/drm/msm/Kconfig | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 6 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 4 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 7 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 3 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 2 +-
drivers/gpu/drm/msm/msm_mdss.c | 302 ++++------------------------
drivers/gpu/drm/msm/msm_mdss.h | 28 ---
10 files changed, 49 insertions(+), 308 deletions(-)
diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig
index 7f127e2ae44292f8f5c7ff6a9251c3d7ec8c9f58..6579ac907b83bc8042388e4efbaa250ebe771ac5 100644
--- a/drivers/gpu/drm/msm/Kconfig
+++ b/drivers/gpu/drm/msm/Kconfig
@@ -95,6 +95,7 @@ config DRM_MSM_DPU
depends on DRM_MSM
select DRM_MSM_MDSS
select DRM_DISPLAY_DSC_HELPER
+ select QCOM_UBWC_CONFIG
default y
help
Compile in support for the Display Processing Unit in
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
index 32c7c80845533d720683dbcde3978d98f4972cce..54ccb1e5a89c75452ac6d53d201999d1124be8cd 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
@@ -10,11 +10,11 @@
#include "dpu_hw_sspp.h"
#include "dpu_kms.h"
-#include "msm_mdss.h"
-
#include <drm/drm_file.h>
#include <drm/drm_managed.h>
+#include <linux/soc/qcom/ubwc.h>
+
#define DPU_FETCH_CONFIG_RESET_VALUE 0x00000087
/* SSPP registers */
@@ -684,7 +684,7 @@ int _dpu_hw_sspp_init_debugfs(struct dpu_hw_sspp *hw_pipe, struct dpu_kms *kms,
struct dpu_hw_sspp *dpu_hw_sspp_init(struct drm_device *dev,
const struct dpu_sspp_cfg *cfg,
void __iomem *addr,
- const struct msm_mdss_data *mdss_data,
+ const struct qcom_ubwc_cfg_data *mdss_data,
const struct dpu_mdss_version *mdss_rev)
{
struct dpu_hw_sspp *hw_pipe;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
index 56a0edf2a57c6dcef7cddf4a1bcd6f6df5ad60f6..7957a3ab6b68cbbd2fd9e1f48673b42d1c8a225a 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
@@ -308,7 +308,7 @@ struct dpu_hw_sspp_ops {
struct dpu_hw_sspp {
struct dpu_hw_blk base;
struct dpu_hw_blk_reg_map hw;
- const struct msm_mdss_data *ubwc;
+ const struct qcom_ubwc_cfg_data *ubwc;
/* Pipe */
enum dpu_sspp idx;
@@ -323,7 +323,7 @@ struct dpu_kms;
struct dpu_hw_sspp *dpu_hw_sspp_init(struct drm_device *dev,
const struct dpu_sspp_cfg *cfg,
void __iomem *addr,
- const struct msm_mdss_data *mdss_data,
+ const struct qcom_ubwc_cfg_data *mdss_data,
const struct dpu_mdss_version *mdss_rev);
int _dpu_hw_sspp_init_debugfs(struct dpu_hw_sspp *hw_pipe, struct dpu_kms *kms,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 1fd82b6747e9058ce11dc2620729921492d5ebdd..6667de3154e078b74f797ce1b92d4625c1503f9e 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -20,9 +20,10 @@
#include <drm/drm_vblank.h>
#include <drm/drm_writeback.h>
+#include <linux/soc/qcom/ubwc.h>
+
#include "msm_drv.h"
#include "msm_mmu.h"
-#include "msm_mdss.h"
#include "msm_gem.h"
#include "disp/msm_disp_snapshot.h"
@@ -1189,10 +1190,10 @@ static int dpu_kms_hw_init(struct msm_kms *kms)
goto err_pm_put;
}
- dpu_kms->mdss = msm_mdss_get_mdss_data(dpu_kms->pdev->dev.parent);
+ dpu_kms->mdss = qcom_ubwc_config_get_data();
if (IS_ERR(dpu_kms->mdss)) {
rc = PTR_ERR(dpu_kms->mdss);
- DPU_ERROR("failed to get MDSS data: %d\n", rc);
+ DPU_ERROR("failed to get UBWC config data: %d\n", rc);
goto err_pm_put;
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
index a57ec2ec106083e8f93578e4307e8b13ae549c08..993cf512f8c509ac4e28a60a1a31b262f4a54f98 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
@@ -60,7 +60,7 @@ struct dpu_kms {
struct msm_kms base;
struct drm_device *dev;
const struct dpu_mdss_cfg *catalog;
- const struct msm_mdss_data *mdss;
+ const struct qcom_ubwc_cfg_data *mdss;
/* io/register spaces: */
void __iomem *mmio, *vbif[VBIF_MAX];
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index 421138bc3cb779c45fcfd5319056f0d31c862452..ba5a46c5c1b501d22c6b28dd82ac761c26d08541 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -17,8 +17,9 @@
#include <drm/drm_framebuffer.h>
#include <drm/drm_gem_atomic_helper.h>
+#include <linux/soc/qcom/ubwc.h>
+
#include "msm_drv.h"
-#include "msm_mdss.h"
#include "dpu_kms.h"
#include "dpu_hw_sspp.h"
#include "dpu_hw_util.h"
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index 2e296f79cba1437470eeb30900a650f6f4e334b6..cae85812fe273ba12ef9215e1881f59986bbf969 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -40,7 +40,7 @@ static inline bool reserved_by_other(uint32_t *res_map, int idx,
int dpu_rm_init(struct drm_device *dev,
struct dpu_rm *rm,
const struct dpu_mdss_cfg *cat,
- const struct msm_mdss_data *mdss_data,
+ const struct qcom_ubwc_cfg_data *mdss_data,
void __iomem *mmio)
{
int rc, i;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
index aa62966056d489d9c94c61f24051a2f3e7b7ed89..ccd64404f12d3ca3956c8e6df7d1ffddd4f20642 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
@@ -69,7 +69,7 @@ struct msm_display_topology {
int dpu_rm_init(struct drm_device *dev,
struct dpu_rm *rm,
const struct dpu_mdss_cfg *cat,
- const struct msm_mdss_data *mdss_data,
+ const struct qcom_ubwc_cfg_data *mdss_data,
void __iomem *mmio);
int dpu_rm_reserve(struct dpu_rm *rm,
diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
index 709979fcfab6062c0f316f7655823e888638bfea..a0c4b47470deca4b469868c7fdcc2f962723efcb 100644
--- a/drivers/gpu/drm/msm/msm_mdss.c
+++ b/drivers/gpu/drm/msm/msm_mdss.c
@@ -16,7 +16,8 @@
#include <linux/pm_runtime.h>
#include <linux/reset.h>
-#include "msm_mdss.h"
+#include <linux/soc/qcom/ubwc.h>
+
#include "msm_kms.h"
#include <generated/mdss.xml.h>
@@ -36,7 +37,7 @@ struct msm_mdss {
unsigned long enabled_mask;
struct irq_domain *domain;
} irq_controller;
- const struct msm_mdss_data *mdss_data;
+ const struct qcom_ubwc_cfg_data *mdss_data;
struct icc_path *mdp_path[2];
u32 num_mdp_paths;
struct icc_path *reg_bus_path;
@@ -165,7 +166,7 @@ static int _msm_mdss_irq_domain_add(struct msm_mdss *msm_mdss)
static void msm_mdss_setup_ubwc_dec_20(struct msm_mdss *msm_mdss)
{
- const struct msm_mdss_data *data = msm_mdss->mdss_data;
+ const struct qcom_ubwc_cfg_data *data = msm_mdss->mdss_data;
u32 value = MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle) |
MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit);
@@ -180,7 +181,7 @@ static void msm_mdss_setup_ubwc_dec_20(struct msm_mdss *msm_mdss)
static void msm_mdss_setup_ubwc_dec_30(struct msm_mdss *msm_mdss)
{
- const struct msm_mdss_data *data = msm_mdss->mdss_data;
+ const struct qcom_ubwc_cfg_data *data = msm_mdss->mdss_data;
u32 value = MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle & 0x1) |
MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit);
@@ -198,7 +199,7 @@ static void msm_mdss_setup_ubwc_dec_30(struct msm_mdss *msm_mdss)
static void msm_mdss_setup_ubwc_dec_40(struct msm_mdss *msm_mdss)
{
- const struct msm_mdss_data *data = msm_mdss->mdss_data;
+ const struct qcom_ubwc_cfg_data *data = msm_mdss->mdss_data;
u32 value = MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle) |
MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit);
@@ -222,69 +223,6 @@ static void msm_mdss_setup_ubwc_dec_40(struct msm_mdss *msm_mdss)
}
}
-#define MDSS_HW_MAJ_MIN \
- (MDSS_HW_VERSION_MAJOR__MASK | MDSS_HW_VERSION_MINOR__MASK)
-
-#define MDSS_HW_MSM8996 0x1007
-#define MDSS_HW_MSM8937 0x100e
-#define MDSS_HW_MSM8953 0x1010
-#define MDSS_HW_MSM8998 0x3000
-#define MDSS_HW_SDM660 0x3002
-#define MDSS_HW_SDM630 0x3003
-
-/*
- * MDP5 platforms use generic qcom,mdp5 compat string, so we have to generate this data
- */
-static const struct msm_mdss_data *msm_mdss_generate_mdp5_mdss_data(struct msm_mdss *mdss)
-{
- struct msm_mdss_data *data;
- u32 hw_rev;
-
- data = devm_kzalloc(mdss->dev, sizeof(*data), GFP_KERNEL);
- if (!data)
- return NULL;
-
- hw_rev = readl_relaxed(mdss->mmio + REG_MDSS_HW_VERSION);
- hw_rev = FIELD_GET(MDSS_HW_MAJ_MIN, hw_rev);
-
- if (hw_rev == MDSS_HW_MSM8996 ||
- hw_rev == MDSS_HW_MSM8937 ||
- hw_rev == MDSS_HW_MSM8953 ||
- hw_rev == MDSS_HW_MSM8998 ||
- hw_rev == MDSS_HW_SDM660 ||
- hw_rev == MDSS_HW_SDM630) {
- data->ubwc_dec_version = UBWC_1_0;
- data->ubwc_enc_version = UBWC_1_0;
- }
-
- if (hw_rev == MDSS_HW_MSM8996 ||
- hw_rev == MDSS_HW_MSM8998)
- data->highest_bank_bit = 2;
- else
- data->highest_bank_bit = 1;
-
- return data;
-}
-
-const struct msm_mdss_data *msm_mdss_get_mdss_data(struct device *dev)
-{
- struct msm_mdss *mdss;
-
- if (!dev)
- return ERR_PTR(-EINVAL);
-
- mdss = dev_get_drvdata(dev);
-
- /*
- * We could not do it at the probe time, since hw revision register was
- * not readable. Fill data structure now for the MDP5 platforms.
- */
- if (!mdss->mdss_data && mdss->is_mdp5)
- mdss->mdss_data = msm_mdss_generate_mdp5_mdss_data(mdss);
-
- return mdss->mdss_data;
-}
-
static int msm_mdss_enable(struct msm_mdss *msm_mdss)
{
int ret, i;
@@ -297,9 +235,9 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss)
for (i = 0; i < msm_mdss->num_mdp_paths; i++)
icc_set_bw(msm_mdss->mdp_path[i], 0, Bps_to_icc(MIN_IB_BW));
- if (msm_mdss->mdss_data && msm_mdss->mdss_data->reg_bus_bw)
+ if (msm_mdss->mdss_data && msm_mdss->mdss_data->mdss_reg_bus_bw)
icc_set_bw(msm_mdss->reg_bus_path, 0,
- msm_mdss->mdss_data->reg_bus_bw);
+ msm_mdss->mdss_data->mdss_reg_bus_bw);
else
icc_set_bw(msm_mdss->reg_bus_path, 0,
DEFAULT_REG_BW);
@@ -450,7 +388,9 @@ static struct msm_mdss *msm_mdss_init(struct platform_device *pdev, bool is_mdp5
if (!msm_mdss)
return ERR_PTR(-ENOMEM);
- msm_mdss->mdss_data = of_device_get_match_data(&pdev->dev);
+ msm_mdss->mdss_data = qcom_ubwc_config_get_data();
+ if (IS_ERR(msm_mdss->mdss_data))
+ return ERR_CAST(msm_mdss->mdss_data);
msm_mdss->mmio = devm_platform_ioremap_resource_byname(pdev, is_mdp5 ? "mdss_phys" : "mdss");
if (IS_ERR(msm_mdss->mmio))
@@ -569,205 +509,31 @@ static void mdss_remove(struct platform_device *pdev)
msm_mdss_destroy(mdss);
}
-static const struct msm_mdss_data msm8998_data = {
- .ubwc_enc_version = UBWC_1_0,
- .ubwc_dec_version = UBWC_1_0,
- .highest_bank_bit = 2,
- .reg_bus_bw = 76800,
-};
-
-static const struct msm_mdss_data qcm2290_data = {
- /* no UBWC */
- .highest_bank_bit = 0x2,
- .reg_bus_bw = 76800,
-};
-
-static const struct msm_mdss_data sa8775p_data = {
- .ubwc_enc_version = UBWC_4_0,
- .ubwc_dec_version = UBWC_4_0,
- .ubwc_swizzle = 4,
- .ubwc_bank_spread = true,
- .highest_bank_bit = 0,
- .macrotile_mode = true,
- .reg_bus_bw = 74000,
-};
-
-static const struct msm_mdss_data sar2130p_data = {
- .ubwc_enc_version = UBWC_3_0, /* 4.0.2 in hw */
- .ubwc_dec_version = UBWC_4_3,
- .ubwc_swizzle = 6,
- .ubwc_bank_spread = true,
- .highest_bank_bit = 0,
- .macrotile_mode = 1,
- .reg_bus_bw = 74000,
-};
-
-static const struct msm_mdss_data sc7180_data = {
- .ubwc_enc_version = UBWC_2_0,
- .ubwc_dec_version = UBWC_2_0,
- .ubwc_swizzle = 6,
- .ubwc_bank_spread = true,
- .highest_bank_bit = 0x1,
- .reg_bus_bw = 76800,
-};
-
-static const struct msm_mdss_data sc7280_data = {
- .ubwc_enc_version = UBWC_3_0,
- .ubwc_dec_version = UBWC_4_0,
- .ubwc_swizzle = 6,
- .ubwc_bank_spread = true,
- .highest_bank_bit = 1,
- .macrotile_mode = true,
- .reg_bus_bw = 74000,
-};
-
-static const struct msm_mdss_data sc8180x_data = {
- .ubwc_enc_version = UBWC_3_0,
- .ubwc_dec_version = UBWC_3_0,
- .highest_bank_bit = 3,
- .macrotile_mode = true,
- .reg_bus_bw = 76800,
-};
-
-static const struct msm_mdss_data sc8280xp_data = {
- .ubwc_enc_version = UBWC_4_0,
- .ubwc_dec_version = UBWC_4_0,
- .ubwc_swizzle = 6,
- .ubwc_bank_spread = true,
- .highest_bank_bit = 3,
- .macrotile_mode = true,
- .reg_bus_bw = 76800,
-};
-
-static const struct msm_mdss_data sdm670_data = {
- .ubwc_enc_version = UBWC_2_0,
- .ubwc_dec_version = UBWC_2_0,
- .highest_bank_bit = 1,
- .reg_bus_bw = 76800,
-};
-
-static const struct msm_mdss_data sdm845_data = {
- .ubwc_enc_version = UBWC_2_0,
- .ubwc_dec_version = UBWC_2_0,
- .highest_bank_bit = 2,
- .reg_bus_bw = 76800,
-};
-
-static const struct msm_mdss_data sm6350_data = {
- .ubwc_enc_version = UBWC_2_0,
- .ubwc_dec_version = UBWC_2_0,
- .ubwc_swizzle = 6,
- .ubwc_bank_spread = true,
- .highest_bank_bit = 1,
- .reg_bus_bw = 76800,
-};
-
-static const struct msm_mdss_data sm7150_data = {
- .ubwc_enc_version = UBWC_2_0,
- .ubwc_dec_version = UBWC_2_0,
- .highest_bank_bit = 1,
- .reg_bus_bw = 76800,
-};
-
-static const struct msm_mdss_data sm8150_data = {
- .ubwc_enc_version = UBWC_3_0,
- .ubwc_dec_version = UBWC_3_0,
- .highest_bank_bit = 2,
- .reg_bus_bw = 76800,
-};
-
-static const struct msm_mdss_data sm6115_data = {
- .ubwc_enc_version = UBWC_1_0,
- .ubwc_dec_version = UBWC_2_0,
- .ubwc_swizzle = 7,
- .ubwc_bank_spread = true,
- .highest_bank_bit = 0x1,
- .reg_bus_bw = 76800,
-};
-
-static const struct msm_mdss_data sm6125_data = {
- .ubwc_enc_version = UBWC_1_0,
- .ubwc_dec_version = UBWC_3_0,
- .ubwc_swizzle = 1,
- .highest_bank_bit = 1,
-};
-
-static const struct msm_mdss_data sm6150_data = {
- .ubwc_enc_version = UBWC_2_0,
- .ubwc_dec_version = UBWC_2_0,
- .highest_bank_bit = 1,
- .reg_bus_bw = 76800,
-};
-
-static const struct msm_mdss_data sm8250_data = {
- .ubwc_enc_version = UBWC_4_0,
- .ubwc_dec_version = UBWC_4_0,
- .ubwc_swizzle = 6,
- .ubwc_bank_spread = true,
- /* TODO: highest_bank_bit = 2 for LP_DDR4 */
- .highest_bank_bit = 3,
- .macrotile_mode = true,
- .reg_bus_bw = 76800,
-};
-
-static const struct msm_mdss_data sm8350_data = {
- .ubwc_enc_version = UBWC_4_0,
- .ubwc_dec_version = UBWC_4_0,
- .ubwc_swizzle = 6,
- .ubwc_bank_spread = true,
- /* TODO: highest_bank_bit = 2 for LP_DDR4 */
- .highest_bank_bit = 3,
- .macrotile_mode = true,
- .reg_bus_bw = 74000,
-};
-
-static const struct msm_mdss_data sm8550_data = {
- .ubwc_enc_version = UBWC_4_0,
- .ubwc_dec_version = UBWC_4_3,
- .ubwc_swizzle = 6,
- .ubwc_bank_spread = true,
- /* TODO: highest_bank_bit = 2 for LP_DDR4 */
- .highest_bank_bit = 3,
- .macrotile_mode = true,
- .reg_bus_bw = 57000,
-};
-
-static const struct msm_mdss_data x1e80100_data = {
- .ubwc_enc_version = UBWC_4_0,
- .ubwc_dec_version = UBWC_4_3,
- .ubwc_swizzle = 6,
- .ubwc_bank_spread = true,
- /* TODO: highest_bank_bit = 2 for LP_DDR4 */
- .highest_bank_bit = 3,
- .macrotile_mode = true,
- /* TODO: Add reg_bus_bw with real value */
-};
-
static const struct of_device_id mdss_dt_match[] = {
{ .compatible = "qcom,mdss" },
- { .compatible = "qcom,msm8998-mdss", .data = &msm8998_data },
- { .compatible = "qcom,qcm2290-mdss", .data = &qcm2290_data },
- { .compatible = "qcom,sa8775p-mdss", .data = &sa8775p_data },
- { .compatible = "qcom,sar2130p-mdss", .data = &sar2130p_data },
- { .compatible = "qcom,sdm670-mdss", .data = &sdm670_data },
- { .compatible = "qcom,sdm845-mdss", .data = &sdm845_data },
- { .compatible = "qcom,sc7180-mdss", .data = &sc7180_data },
- { .compatible = "qcom,sc7280-mdss", .data = &sc7280_data },
- { .compatible = "qcom,sc8180x-mdss", .data = &sc8180x_data },
- { .compatible = "qcom,sc8280xp-mdss", .data = &sc8280xp_data },
- { .compatible = "qcom,sm6115-mdss", .data = &sm6115_data },
- { .compatible = "qcom,sm6125-mdss", .data = &sm6125_data },
- { .compatible = "qcom,sm6150-mdss", .data = &sm6150_data },
- { .compatible = "qcom,sm6350-mdss", .data = &sm6350_data },
- { .compatible = "qcom,sm6375-mdss", .data = &sm6350_data },
- { .compatible = "qcom,sm7150-mdss", .data = &sm7150_data },
- { .compatible = "qcom,sm8150-mdss", .data = &sm8150_data },
- { .compatible = "qcom,sm8250-mdss", .data = &sm8250_data },
- { .compatible = "qcom,sm8350-mdss", .data = &sm8350_data },
- { .compatible = "qcom,sm8450-mdss", .data = &sm8350_data },
- { .compatible = "qcom,sm8550-mdss", .data = &sm8550_data },
- { .compatible = "qcom,sm8650-mdss", .data = &sm8550_data},
- { .compatible = "qcom,x1e80100-mdss", .data = &x1e80100_data},
+ { .compatible = "qcom,msm8998-mdss" },
+ { .compatible = "qcom,qcm2290-mdss" },
+ { .compatible = "qcom,sa8775p-mdss" },
+ { .compatible = "qcom,sar2130p-mdss" },
+ { .compatible = "qcom,sdm670-mdss" },
+ { .compatible = "qcom,sdm845-mdss" },
+ { .compatible = "qcom,sc7180-mdss" },
+ { .compatible = "qcom,sc7280-mdss" },
+ { .compatible = "qcom,sc8180x-mdss" },
+ { .compatible = "qcom,sc8280xp-mdss" },
+ { .compatible = "qcom,sm6115-mdss" },
+ { .compatible = "qcom,sm6125-mdss" },
+ { .compatible = "qcom,sm6150-mdss" },
+ { .compatible = "qcom,sm6350-mdss" },
+ { .compatible = "qcom,sm6375-mdss" },
+ { .compatible = "qcom,sm7150-mdss" },
+ { .compatible = "qcom,sm8150-mdss" },
+ { .compatible = "qcom,sm8250-mdss" },
+ { .compatible = "qcom,sm8350-mdss" },
+ { .compatible = "qcom,sm8450-mdss" },
+ { .compatible = "qcom,sm8550-mdss" },
+ { .compatible = "qcom,sm8650-mdss" },
+ { .compatible = "qcom,x1e80100-mdss"},
{}
};
MODULE_DEVICE_TABLE(of, mdss_dt_match);
diff --git a/drivers/gpu/drm/msm/msm_mdss.h b/drivers/gpu/drm/msm/msm_mdss.h
deleted file mode 100644
index 14dc53704314558841ee1fe08d93309fd2233812..0000000000000000000000000000000000000000
--- a/drivers/gpu/drm/msm/msm_mdss.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (c) 2018, The Linux Foundation
- */
-
-#ifndef __MSM_MDSS_H__
-#define __MSM_MDSS_H__
-
-struct msm_mdss_data {
- u32 ubwc_enc_version;
- /* can be read from register 0x58 */
- u32 ubwc_dec_version;
- u32 ubwc_swizzle;
- u32 highest_bank_bit;
- bool ubwc_bank_spread;
- bool macrotile_mode;
- u32 reg_bus_bw;
-};
-
-#define UBWC_1_0 0x10000000
-#define UBWC_2_0 0x20000000
-#define UBWC_3_0 0x30000000
-#define UBWC_4_0 0x40000000
-#define UBWC_4_3 0x40030000
-
-const struct msm_mdss_data *msm_mdss_get_mdss_data(struct device *dev);
-
-#endif /* __MSM_MDSS_H__ */
--
2.49.0
^ permalink raw reply related [flat|nested] 43+ messages in thread* [PATCH RFT 03/14] drm/msm/adreno: Offset the HBB value by 13
2025-05-08 18:12 [RFT PATCH 00/14] Add a single source of truth for UBWC configuration data Konrad Dybcio
2025-05-08 18:12 ` [PATCH RFT 01/14] soc: qcom: Add UBWC config provider Konrad Dybcio
2025-05-08 18:12 ` [PATCH RFT 02/14] drm/msm: Use the central UBWC config database Konrad Dybcio
@ 2025-05-08 18:12 ` Konrad Dybcio
2025-05-08 19:03 ` Connor Abbott
2025-05-08 18:12 ` [PATCH RFT 04/14] drm/msm/a6xx: Get a handle to the common UBWC config Konrad Dybcio
` (10 subsequent siblings)
13 siblings, 1 reply; 43+ messages in thread
From: Konrad Dybcio @ 2025-05-08 18:12 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Clark, Abhinav Kumar,
Dmitry Baryshkov, Akhil P Oommen, Sean Paul, David Airlie,
Simona Vetter
Cc: Marijn Suijten, linux-kernel, linux-arm-msm, dri-devel, freedreno,
Konrad Dybcio
From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
The value the UBWC hardware expects is 13 less than the actual value.
To make it easier to migrate to a common UBWC configuration table,
defer that logic to the data source (which is currently a number of
if-else statements with assignments in case of this driver).
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 7 +++----
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 30 ++++++++++++------------------
2 files changed, 15 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
index 650e5bac225f372e819130b891f1d020b464f17f..67331a7ee750c0d9eeeead9440e5d08b1a09c878 100644
--- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
@@ -833,8 +833,7 @@ static int a5xx_hw_init(struct msm_gpu *gpu)
gpu_write(gpu, REG_A5XX_RBBM_AHB_CNTL2, 0x0000003F);
- BUG_ON(adreno_gpu->ubwc_config.highest_bank_bit < 13);
- hbb = adreno_gpu->ubwc_config.highest_bank_bit - 13;
+ hbb = adreno_gpu->ubwc_config.highest_bank_bit;
gpu_write(gpu, REG_A5XX_TPL1_MODE_CNTL, hbb << 7);
gpu_write(gpu, REG_A5XX_RB_MODE_CNTL, hbb << 1);
@@ -1792,9 +1791,9 @@ struct msm_gpu *a5xx_gpu_init(struct drm_device *dev)
/* Set the highest bank bit */
if (adreno_is_a540(adreno_gpu) || adreno_is_a530(adreno_gpu))
- adreno_gpu->ubwc_config.highest_bank_bit = 15;
+ adreno_gpu->ubwc_config.highest_bank_bit = 2;
else
- adreno_gpu->ubwc_config.highest_bank_bit = 14;
+ adreno_gpu->ubwc_config.highest_bank_bit = 1;
/* a5xx only supports UBWC 1.0, these are not configurable */
adreno_gpu->ubwc_config.macrotile_mode = 0;
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index bf3758f010f4079aa86f9c658b52a70acf10b488..b161b5cd991fc645dfcd69754b82be9691775ffe 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -592,32 +592,32 @@ static void a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
gpu->ubwc_config.min_acc_len = 0;
gpu->ubwc_config.ubwc_swizzle = 0x6;
gpu->ubwc_config.macrotile_mode = 0;
- gpu->ubwc_config.highest_bank_bit = 15;
+ gpu->ubwc_config.highest_bank_bit = 2;
if (adreno_is_a610(gpu)) {
- gpu->ubwc_config.highest_bank_bit = 13;
+ gpu->ubwc_config.highest_bank_bit = 0;
gpu->ubwc_config.min_acc_len = 1;
gpu->ubwc_config.ubwc_swizzle = 0x7;
}
if (adreno_is_a618(gpu))
- gpu->ubwc_config.highest_bank_bit = 14;
+ gpu->ubwc_config.highest_bank_bit = 1;
if (adreno_is_a619(gpu))
/* TODO: Should be 14 but causes corruption at e.g. 1920x1200 on DP */
- gpu->ubwc_config.highest_bank_bit = 13;
+ gpu->ubwc_config.highest_bank_bit = 0;
if (adreno_is_a619_holi(gpu))
- gpu->ubwc_config.highest_bank_bit = 13;
+ gpu->ubwc_config.highest_bank_bit = 0;
if (adreno_is_a621(gpu)) {
- gpu->ubwc_config.highest_bank_bit = 13;
+ gpu->ubwc_config.highest_bank_bit = 0;
gpu->ubwc_config.amsbc = 1;
gpu->ubwc_config.uavflagprd_inv = 2;
}
if (adreno_is_a623(gpu)) {
- gpu->ubwc_config.highest_bank_bit = 16;
+ gpu->ubwc_config.highest_bank_bit = 3;
gpu->ubwc_config.amsbc = 1;
gpu->ubwc_config.rgb565_predicator = 1;
gpu->ubwc_config.uavflagprd_inv = 2;
@@ -636,7 +636,7 @@ static void a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
adreno_is_a730(gpu) ||
adreno_is_a740_family(gpu)) {
/* TODO: get ddr type from bootloader and use 2 for LPDDR4 */
- gpu->ubwc_config.highest_bank_bit = 16;
+ gpu->ubwc_config.highest_bank_bit = 3;
gpu->ubwc_config.amsbc = 1;
gpu->ubwc_config.rgb565_predicator = 1;
gpu->ubwc_config.uavflagprd_inv = 2;
@@ -644,7 +644,7 @@ static void a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
}
if (adreno_is_a663(gpu)) {
- gpu->ubwc_config.highest_bank_bit = 13;
+ gpu->ubwc_config.highest_bank_bit = 0;
gpu->ubwc_config.amsbc = 1;
gpu->ubwc_config.rgb565_predicator = 1;
gpu->ubwc_config.uavflagprd_inv = 2;
@@ -653,14 +653,14 @@ static void a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
}
if (adreno_is_7c3(gpu)) {
- gpu->ubwc_config.highest_bank_bit = 14;
+ gpu->ubwc_config.highest_bank_bit = 1;
gpu->ubwc_config.amsbc = 1;
gpu->ubwc_config.uavflagprd_inv = 2;
gpu->ubwc_config.macrotile_mode = 1;
}
if (adreno_is_a702(gpu)) {
- gpu->ubwc_config.highest_bank_bit = 14;
+ gpu->ubwc_config.highest_bank_bit = 1;
gpu->ubwc_config.min_acc_len = 1;
}
}
@@ -668,13 +668,7 @@ static void a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
{
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
- /*
- * We subtract 13 from the highest bank bit (13 is the minimum value
- * allowed by hw) and write the lowest two bits of the remaining value
- * as hbb_lo and the one above it as hbb_hi to the hardware.
- */
- BUG_ON(adreno_gpu->ubwc_config.highest_bank_bit < 13);
- u32 hbb = adreno_gpu->ubwc_config.highest_bank_bit - 13;
+ u32 hbb = adreno_gpu->ubwc_config.highest_bank_bit;
u32 hbb_hi = hbb >> 2;
u32 hbb_lo = hbb & 3;
u32 ubwc_mode = adreno_gpu->ubwc_config.ubwc_swizzle & 1;
--
2.49.0
^ permalink raw reply related [flat|nested] 43+ messages in thread* Re: [PATCH RFT 03/14] drm/msm/adreno: Offset the HBB value by 13
2025-05-08 18:12 ` [PATCH RFT 03/14] drm/msm/adreno: Offset the HBB value by 13 Konrad Dybcio
@ 2025-05-08 19:03 ` Connor Abbott
2025-05-09 12:30 ` Konrad Dybcio
0 siblings, 1 reply; 43+ messages in thread
From: Connor Abbott @ 2025-05-08 19:03 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Bjorn Andersson, Rob Clark, Abhinav Kumar, Dmitry Baryshkov,
Akhil P Oommen, Sean Paul, David Airlie, Simona Vetter,
Marijn Suijten, linux-kernel, linux-arm-msm, dri-devel, freedreno,
Konrad Dybcio
On Thu, May 8, 2025 at 2:13 PM Konrad Dybcio <konradybcio@kernel.org> wrote:
>
> From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>
> The value the UBWC hardware expects is 13 less than the actual value.
> To make it easier to migrate to a common UBWC configuration table,
> defer that logic to the data source (which is currently a number of
> if-else statements with assignments in case of this driver).
Don't break the value exposed to userspace!
Connor
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> ---
> drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 7 +++----
> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 30 ++++++++++++------------------
> 2 files changed, 15 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
> index 650e5bac225f372e819130b891f1d020b464f17f..67331a7ee750c0d9eeeead9440e5d08b1a09c878 100644
> --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
> @@ -833,8 +833,7 @@ static int a5xx_hw_init(struct msm_gpu *gpu)
>
> gpu_write(gpu, REG_A5XX_RBBM_AHB_CNTL2, 0x0000003F);
>
> - BUG_ON(adreno_gpu->ubwc_config.highest_bank_bit < 13);
> - hbb = adreno_gpu->ubwc_config.highest_bank_bit - 13;
> + hbb = adreno_gpu->ubwc_config.highest_bank_bit;
>
> gpu_write(gpu, REG_A5XX_TPL1_MODE_CNTL, hbb << 7);
> gpu_write(gpu, REG_A5XX_RB_MODE_CNTL, hbb << 1);
> @@ -1792,9 +1791,9 @@ struct msm_gpu *a5xx_gpu_init(struct drm_device *dev)
>
> /* Set the highest bank bit */
> if (adreno_is_a540(adreno_gpu) || adreno_is_a530(adreno_gpu))
> - adreno_gpu->ubwc_config.highest_bank_bit = 15;
> + adreno_gpu->ubwc_config.highest_bank_bit = 2;
> else
> - adreno_gpu->ubwc_config.highest_bank_bit = 14;
> + adreno_gpu->ubwc_config.highest_bank_bit = 1;
>
> /* a5xx only supports UBWC 1.0, these are not configurable */
> adreno_gpu->ubwc_config.macrotile_mode = 0;
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> index bf3758f010f4079aa86f9c658b52a70acf10b488..b161b5cd991fc645dfcd69754b82be9691775ffe 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> @@ -592,32 +592,32 @@ static void a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
> gpu->ubwc_config.min_acc_len = 0;
> gpu->ubwc_config.ubwc_swizzle = 0x6;
> gpu->ubwc_config.macrotile_mode = 0;
> - gpu->ubwc_config.highest_bank_bit = 15;
> + gpu->ubwc_config.highest_bank_bit = 2;
>
> if (adreno_is_a610(gpu)) {
> - gpu->ubwc_config.highest_bank_bit = 13;
> + gpu->ubwc_config.highest_bank_bit = 0;
> gpu->ubwc_config.min_acc_len = 1;
> gpu->ubwc_config.ubwc_swizzle = 0x7;
> }
>
> if (adreno_is_a618(gpu))
> - gpu->ubwc_config.highest_bank_bit = 14;
> + gpu->ubwc_config.highest_bank_bit = 1;
>
> if (adreno_is_a619(gpu))
> /* TODO: Should be 14 but causes corruption at e.g. 1920x1200 on DP */
> - gpu->ubwc_config.highest_bank_bit = 13;
> + gpu->ubwc_config.highest_bank_bit = 0;
>
> if (adreno_is_a619_holi(gpu))
> - gpu->ubwc_config.highest_bank_bit = 13;
> + gpu->ubwc_config.highest_bank_bit = 0;
>
> if (adreno_is_a621(gpu)) {
> - gpu->ubwc_config.highest_bank_bit = 13;
> + gpu->ubwc_config.highest_bank_bit = 0;
> gpu->ubwc_config.amsbc = 1;
> gpu->ubwc_config.uavflagprd_inv = 2;
> }
>
> if (adreno_is_a623(gpu)) {
> - gpu->ubwc_config.highest_bank_bit = 16;
> + gpu->ubwc_config.highest_bank_bit = 3;
> gpu->ubwc_config.amsbc = 1;
> gpu->ubwc_config.rgb565_predicator = 1;
> gpu->ubwc_config.uavflagprd_inv = 2;
> @@ -636,7 +636,7 @@ static void a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
> adreno_is_a730(gpu) ||
> adreno_is_a740_family(gpu)) {
> /* TODO: get ddr type from bootloader and use 2 for LPDDR4 */
> - gpu->ubwc_config.highest_bank_bit = 16;
> + gpu->ubwc_config.highest_bank_bit = 3;
> gpu->ubwc_config.amsbc = 1;
> gpu->ubwc_config.rgb565_predicator = 1;
> gpu->ubwc_config.uavflagprd_inv = 2;
> @@ -644,7 +644,7 @@ static void a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
> }
>
> if (adreno_is_a663(gpu)) {
> - gpu->ubwc_config.highest_bank_bit = 13;
> + gpu->ubwc_config.highest_bank_bit = 0;
> gpu->ubwc_config.amsbc = 1;
> gpu->ubwc_config.rgb565_predicator = 1;
> gpu->ubwc_config.uavflagprd_inv = 2;
> @@ -653,14 +653,14 @@ static void a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
> }
>
> if (adreno_is_7c3(gpu)) {
> - gpu->ubwc_config.highest_bank_bit = 14;
> + gpu->ubwc_config.highest_bank_bit = 1;
> gpu->ubwc_config.amsbc = 1;
> gpu->ubwc_config.uavflagprd_inv = 2;
> gpu->ubwc_config.macrotile_mode = 1;
> }
>
> if (adreno_is_a702(gpu)) {
> - gpu->ubwc_config.highest_bank_bit = 14;
> + gpu->ubwc_config.highest_bank_bit = 1;
> gpu->ubwc_config.min_acc_len = 1;
> }
> }
> @@ -668,13 +668,7 @@ static void a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
> static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
> {
> struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
> - /*
> - * We subtract 13 from the highest bank bit (13 is the minimum value
> - * allowed by hw) and write the lowest two bits of the remaining value
> - * as hbb_lo and the one above it as hbb_hi to the hardware.
> - */
> - BUG_ON(adreno_gpu->ubwc_config.highest_bank_bit < 13);
> - u32 hbb = adreno_gpu->ubwc_config.highest_bank_bit - 13;
> + u32 hbb = adreno_gpu->ubwc_config.highest_bank_bit;
> u32 hbb_hi = hbb >> 2;
> u32 hbb_lo = hbb & 3;
> u32 ubwc_mode = adreno_gpu->ubwc_config.ubwc_swizzle & 1;
>
> --
> 2.49.0
>
^ permalink raw reply [flat|nested] 43+ messages in thread* Re: [PATCH RFT 03/14] drm/msm/adreno: Offset the HBB value by 13
2025-05-08 19:03 ` Connor Abbott
@ 2025-05-09 12:30 ` Konrad Dybcio
0 siblings, 0 replies; 43+ messages in thread
From: Konrad Dybcio @ 2025-05-09 12:30 UTC (permalink / raw)
To: Connor Abbott, Konrad Dybcio
Cc: Bjorn Andersson, Rob Clark, Abhinav Kumar, Dmitry Baryshkov,
Akhil P Oommen, Sean Paul, David Airlie, Simona Vetter,
Marijn Suijten, linux-kernel, linux-arm-msm, dri-devel, freedreno
On 5/8/25 9:03 PM, Connor Abbott wrote:
> On Thu, May 8, 2025 at 2:13 PM Konrad Dybcio <konradybcio@kernel.org> wrote:
>>
>> From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>>
>> The value the UBWC hardware expects is 13 less than the actual value.
>> To make it easier to migrate to a common UBWC configuration table,
>> defer that logic to the data source (which is currently a number of
>> if-else statements with assignments in case of this driver).
>
> Don't break the value exposed to userspace!
Bah, I keep forgetting it's there.. I think I'll alter the mdss code to
do a -13 in there instead to make it a little saner with the future
getters that return the x+13 value too.
Konrad
^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH RFT 04/14] drm/msm/a6xx: Get a handle to the common UBWC config
2025-05-08 18:12 [RFT PATCH 00/14] Add a single source of truth for UBWC configuration data Konrad Dybcio
` (2 preceding siblings ...)
2025-05-08 18:12 ` [PATCH RFT 03/14] drm/msm/adreno: Offset the HBB value by 13 Konrad Dybcio
@ 2025-05-08 18:12 ` Konrad Dybcio
2025-05-08 18:41 ` Rob Clark
2025-05-08 18:12 ` [PATCH RFT 05/14] drm/msm/a6xx: Resolve the meaning of AMSBC Konrad Dybcio
` (9 subsequent siblings)
13 siblings, 1 reply; 43+ messages in thread
From: Konrad Dybcio @ 2025-05-08 18:12 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Clark, Abhinav Kumar,
Dmitry Baryshkov, Akhil P Oommen, Sean Paul, David Airlie,
Simona Vetter
Cc: Marijn Suijten, linux-kernel, linux-arm-msm, dri-devel, freedreno,
Konrad Dybcio
From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Start the great despaghettification by getting a pointer to the common
UBWC configuration, which houses e.g. UBWC versions that we need to
make decisions.
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 16 ++++++++++++++--
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 6 ++++++
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 3 +++
3 files changed, 23 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index b161b5cd991fc645dfcd69754b82be9691775ffe..89eb725f0950f3679d6214366cfbd22d5bcf4bc7 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -585,8 +585,13 @@ static void a6xx_set_cp_protect(struct msm_gpu *gpu)
gpu_write(gpu, REG_A6XX_CP_PROTECT(protect->count_max - 1), protect->regs[i]);
}
-static void a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
+static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
{
+ /* Inherit the common config and make some necessary fixups */
+ gpu->common_ubwc_cfg = qcom_ubwc_config_get_data();
+ if (IS_ERR(gpu->common_ubwc_cfg))
+ return -EINVAL;
+
gpu->ubwc_config.rgb565_predicator = 0;
gpu->ubwc_config.uavflagprd_inv = 0;
gpu->ubwc_config.min_acc_len = 0;
@@ -663,6 +668,8 @@ static void a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
gpu->ubwc_config.highest_bank_bit = 1;
gpu->ubwc_config.min_acc_len = 1;
}
+
+ return 0;
}
static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
@@ -2540,7 +2547,12 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)
msm_mmu_set_fault_handler(gpu->aspace->mmu, gpu,
a6xx_fault_handler);
- a6xx_calc_ubwc_config(adreno_gpu);
+ ret = a6xx_calc_ubwc_config(adreno_gpu);
+ if (ret) {
+ a6xx_destroy(&(a6xx_gpu->base.base));
+ return ERR_PTR(ret);
+ }
+
/* Set up the preemption specific bits and pieces for each ringbuffer */
a6xx_preempt_init(gpu);
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
index 2348ffb35f7eb73a26da47881901d9111dca1ad9..b7f7eb8dcb272394dce8ed1e68310a394c1734a9 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
@@ -1149,6 +1149,12 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
speedbin = 0xffff;
adreno_gpu->speedbin = (uint16_t) (0xffff & speedbin);
+ adreno_gpu->common_ubwc_cfg = devm_kzalloc(dev,
+ sizeof(*adreno_gpu->common_ubwc_cfg),
+ GFP_KERNEL);
+ if (!adreno_gpu->common_ubwc_cfg)
+ return -ENOMEM;
+
gpu_name = devm_kasprintf(dev, GFP_KERNEL, "%"ADRENO_CHIPID_FMT,
ADRENO_CHIPID_ARGS(config->chip_id));
if (!gpu_name)
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
index a8f4bf416e64fadbd1c61c991db13d539581e324..06be95d3efaee94e4107a484ad3132e0a6a9ea46 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
@@ -12,6 +12,8 @@
#include <linux/firmware.h>
#include <linux/iopoll.h>
+#include <linux/soc/qcom/ubwc.h>
+
#include "msm_gpu.h"
#include "adreno_common.xml.h"
@@ -243,6 +245,7 @@ struct adreno_gpu {
*/
u32 macrotile_mode;
} ubwc_config;
+ const struct qcom_ubwc_cfg_data *common_ubwc_cfg;
/*
* Register offsets are different between some GPUs.
--
2.49.0
^ permalink raw reply related [flat|nested] 43+ messages in thread* Re: [PATCH RFT 04/14] drm/msm/a6xx: Get a handle to the common UBWC config
2025-05-08 18:12 ` [PATCH RFT 04/14] drm/msm/a6xx: Get a handle to the common UBWC config Konrad Dybcio
@ 2025-05-08 18:41 ` Rob Clark
2025-05-09 12:31 ` Konrad Dybcio
0 siblings, 1 reply; 43+ messages in thread
From: Rob Clark @ 2025-05-08 18:41 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Bjorn Andersson, Abhinav Kumar, Dmitry Baryshkov, Akhil P Oommen,
Sean Paul, David Airlie, Simona Vetter, Marijn Suijten,
linux-kernel, linux-arm-msm, dri-devel, freedreno, Konrad Dybcio
On Thu, May 8, 2025 at 11:13 AM Konrad Dybcio <konradybcio@kernel.org> wrote:
>
> From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>
> Start the great despaghettification by getting a pointer to the common
> UBWC configuration, which houses e.g. UBWC versions that we need to
> make decisions.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 16 ++++++++++++++--
> drivers/gpu/drm/msm/adreno/adreno_gpu.c | 6 ++++++
> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 3 +++
> 3 files changed, 23 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> index b161b5cd991fc645dfcd69754b82be9691775ffe..89eb725f0950f3679d6214366cfbd22d5bcf4bc7 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> @@ -585,8 +585,13 @@ static void a6xx_set_cp_protect(struct msm_gpu *gpu)
> gpu_write(gpu, REG_A6XX_CP_PROTECT(protect->count_max - 1), protect->regs[i]);
> }
>
> -static void a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
> +static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
> {
> + /* Inherit the common config and make some necessary fixups */
> + gpu->common_ubwc_cfg = qcom_ubwc_config_get_data();
This does look a bit funny given the devm_kzalloc() below.. I guess
just so that the ptr is never NULL?
BR,
-R
> + if (IS_ERR(gpu->common_ubwc_cfg))
> + return -EINVAL;
> +
> gpu->ubwc_config.rgb565_predicator = 0;
> gpu->ubwc_config.uavflagprd_inv = 0;
> gpu->ubwc_config.min_acc_len = 0;
> @@ -663,6 +668,8 @@ static void a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
> gpu->ubwc_config.highest_bank_bit = 1;
> gpu->ubwc_config.min_acc_len = 1;
> }
> +
> + return 0;
> }
>
> static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
> @@ -2540,7 +2547,12 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)
> msm_mmu_set_fault_handler(gpu->aspace->mmu, gpu,
> a6xx_fault_handler);
>
> - a6xx_calc_ubwc_config(adreno_gpu);
> + ret = a6xx_calc_ubwc_config(adreno_gpu);
> + if (ret) {
> + a6xx_destroy(&(a6xx_gpu->base.base));
> + return ERR_PTR(ret);
> + }
> +
> /* Set up the preemption specific bits and pieces for each ringbuffer */
> a6xx_preempt_init(gpu);
>
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> index 2348ffb35f7eb73a26da47881901d9111dca1ad9..b7f7eb8dcb272394dce8ed1e68310a394c1734a9 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> @@ -1149,6 +1149,12 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
> speedbin = 0xffff;
> adreno_gpu->speedbin = (uint16_t) (0xffff & speedbin);
>
> + adreno_gpu->common_ubwc_cfg = devm_kzalloc(dev,
> + sizeof(*adreno_gpu->common_ubwc_cfg),
> + GFP_KERNEL);
> + if (!adreno_gpu->common_ubwc_cfg)
> + return -ENOMEM;
> +
> gpu_name = devm_kasprintf(dev, GFP_KERNEL, "%"ADRENO_CHIPID_FMT,
> ADRENO_CHIPID_ARGS(config->chip_id));
> if (!gpu_name)
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> index a8f4bf416e64fadbd1c61c991db13d539581e324..06be95d3efaee94e4107a484ad3132e0a6a9ea46 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> @@ -12,6 +12,8 @@
> #include <linux/firmware.h>
> #include <linux/iopoll.h>
>
> +#include <linux/soc/qcom/ubwc.h>
> +
> #include "msm_gpu.h"
>
> #include "adreno_common.xml.h"
> @@ -243,6 +245,7 @@ struct adreno_gpu {
> */
> u32 macrotile_mode;
> } ubwc_config;
> + const struct qcom_ubwc_cfg_data *common_ubwc_cfg;
>
> /*
> * Register offsets are different between some GPUs.
>
> --
> 2.49.0
>
^ permalink raw reply [flat|nested] 43+ messages in thread* Re: [PATCH RFT 04/14] drm/msm/a6xx: Get a handle to the common UBWC config
2025-05-08 18:41 ` Rob Clark
@ 2025-05-09 12:31 ` Konrad Dybcio
2025-05-09 13:52 ` Rob Clark
0 siblings, 1 reply; 43+ messages in thread
From: Konrad Dybcio @ 2025-05-09 12:31 UTC (permalink / raw)
To: Rob Clark, Konrad Dybcio
Cc: Bjorn Andersson, Abhinav Kumar, Dmitry Baryshkov, Akhil P Oommen,
Sean Paul, David Airlie, Simona Vetter, Marijn Suijten,
linux-kernel, linux-arm-msm, dri-devel, freedreno
On 5/8/25 8:41 PM, Rob Clark wrote:
> On Thu, May 8, 2025 at 11:13 AM Konrad Dybcio <konradybcio@kernel.org> wrote:
>>
>> From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>>
>> Start the great despaghettification by getting a pointer to the common
>> UBWC configuration, which houses e.g. UBWC versions that we need to
>> make decisions.
>>
>> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>> ---
>> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 16 ++++++++++++++--
>> drivers/gpu/drm/msm/adreno/adreno_gpu.c | 6 ++++++
>> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 3 +++
>> 3 files changed, 23 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
>> index b161b5cd991fc645dfcd69754b82be9691775ffe..89eb725f0950f3679d6214366cfbd22d5bcf4bc7 100644
>> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
>> @@ -585,8 +585,13 @@ static void a6xx_set_cp_protect(struct msm_gpu *gpu)
>> gpu_write(gpu, REG_A6XX_CP_PROTECT(protect->count_max - 1), protect->regs[i]);
>> }
>>
>> -static void a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
>> +static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
>> {
>> + /* Inherit the common config and make some necessary fixups */
>> + gpu->common_ubwc_cfg = qcom_ubwc_config_get_data();
>
> This does look a bit funny given the devm_kzalloc() below.. I guess
> just so that the ptr is never NULL?
Yeah, would you prefer this is changed?
Konrad
^ permalink raw reply [flat|nested] 43+ messages in thread* Re: [PATCH RFT 04/14] drm/msm/a6xx: Get a handle to the common UBWC config
2025-05-09 12:31 ` Konrad Dybcio
@ 2025-05-09 13:52 ` Rob Clark
2025-05-09 17:00 ` Konrad Dybcio
0 siblings, 1 reply; 43+ messages in thread
From: Rob Clark @ 2025-05-09 13:52 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Konrad Dybcio, Bjorn Andersson, Abhinav Kumar, Dmitry Baryshkov,
Akhil P Oommen, Sean Paul, David Airlie, Simona Vetter,
Marijn Suijten, linux-kernel, linux-arm-msm, dri-devel, freedreno
On Fri, May 9, 2025 at 5:31 AM Konrad Dybcio
<konrad.dybcio@oss.qualcomm.com> wrote:
>
> On 5/8/25 8:41 PM, Rob Clark wrote:
> > On Thu, May 8, 2025 at 11:13 AM Konrad Dybcio <konradybcio@kernel.org> wrote:
> >>
> >> From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> >>
> >> Start the great despaghettification by getting a pointer to the common
> >> UBWC configuration, which houses e.g. UBWC versions that we need to
> >> make decisions.
> >>
> >> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> >> ---
> >> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 16 ++++++++++++++--
> >> drivers/gpu/drm/msm/adreno/adreno_gpu.c | 6 ++++++
> >> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 3 +++
> >> 3 files changed, 23 insertions(+), 2 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> >> index b161b5cd991fc645dfcd69754b82be9691775ffe..89eb725f0950f3679d6214366cfbd22d5bcf4bc7 100644
> >> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> >> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> >> @@ -585,8 +585,13 @@ static void a6xx_set_cp_protect(struct msm_gpu *gpu)
> >> gpu_write(gpu, REG_A6XX_CP_PROTECT(protect->count_max - 1), protect->regs[i]);
> >> }
> >>
> >> -static void a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
> >> +static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
> >> {
> >> + /* Inherit the common config and make some necessary fixups */
> >> + gpu->common_ubwc_cfg = qcom_ubwc_config_get_data();
> >
> > This does look a bit funny given the devm_kzalloc() below.. I guess
> > just so that the ptr is never NULL?
>
> Yeah, would you prefer this is changed?
I think having an all zeros ubwc cfg isn't really going to work
anyways, so probably drop the kzalloc(). Or if there is a case that
I'm not thinking of offhand where it makes sense to have an all 0's
cfg, then add a comment to avoid future head scratching, since
otherwise it looks like a bug to be fixed.
BR,
-R
^ permalink raw reply [flat|nested] 43+ messages in thread* Re: [PATCH RFT 04/14] drm/msm/a6xx: Get a handle to the common UBWC config
2025-05-09 13:52 ` Rob Clark
@ 2025-05-09 17:00 ` Konrad Dybcio
2025-05-13 22:06 ` Rob Clark
0 siblings, 1 reply; 43+ messages in thread
From: Konrad Dybcio @ 2025-05-09 17:00 UTC (permalink / raw)
To: Rob Clark, Konrad Dybcio
Cc: Konrad Dybcio, Bjorn Andersson, Abhinav Kumar, Dmitry Baryshkov,
Akhil P Oommen, Sean Paul, David Airlie, Simona Vetter,
Marijn Suijten, linux-kernel, linux-arm-msm, dri-devel, freedreno
On 5/9/25 3:52 PM, Rob Clark wrote:
> On Fri, May 9, 2025 at 5:31 AM Konrad Dybcio
> <konrad.dybcio@oss.qualcomm.com> wrote:
>>
>> On 5/8/25 8:41 PM, Rob Clark wrote:
>>> On Thu, May 8, 2025 at 11:13 AM Konrad Dybcio <konradybcio@kernel.org> wrote:
>>>>
>>>> From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>>>>
>>>> Start the great despaghettification by getting a pointer to the common
>>>> UBWC configuration, which houses e.g. UBWC versions that we need to
>>>> make decisions.
>>>>
>>>> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>>>> ---
>>>> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 16 ++++++++++++++--
>>>> drivers/gpu/drm/msm/adreno/adreno_gpu.c | 6 ++++++
>>>> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 3 +++
>>>> 3 files changed, 23 insertions(+), 2 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
>>>> index b161b5cd991fc645dfcd69754b82be9691775ffe..89eb725f0950f3679d6214366cfbd22d5bcf4bc7 100644
>>>> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
>>>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
>>>> @@ -585,8 +585,13 @@ static void a6xx_set_cp_protect(struct msm_gpu *gpu)
>>>> gpu_write(gpu, REG_A6XX_CP_PROTECT(protect->count_max - 1), protect->regs[i]);
>>>> }
>>>>
>>>> -static void a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
>>>> +static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
>>>> {
>>>> + /* Inherit the common config and make some necessary fixups */
>>>> + gpu->common_ubwc_cfg = qcom_ubwc_config_get_data();
>>>
>>> This does look a bit funny given the devm_kzalloc() below.. I guess
>>> just so that the ptr is never NULL?
>>
>> Yeah, would you prefer this is changed?
>
> I think having an all zeros ubwc cfg isn't really going to work
> anyways, so probably drop the kzalloc(). Or if there is a case that
> I'm not thinking of offhand where it makes sense to have an all 0's
> cfg, then add a comment to avoid future head scratching, since
> otherwise it looks like a bug to be fixed.
So my own lack of comments bit me.
Without the allocation this will fall apart badly..
I added this hunk:
---------------------
/* Inherit the common config and make some necessary fixups */
common_cfg = if (IS_ERR(common_cfg))
return ERR_PTR(-EINVAL);
*adreno_gpu->ubwc_config = *common_cfg;
---------------------
to get the common data but take away the const qualifier.. because
we still override some HBB values and we can't yet fully trust the
common config, as the smem getter is not yet plumbed up.
I can add a commit discarding all the HBB overrides (matching or not)
or we can keep the zeroalloc around for some time (i'd rather keep
the function returning const so that when things are ready nobody gets
to poke at the source of *truth*)
Konrad
^ permalink raw reply [flat|nested] 43+ messages in thread* Re: [PATCH RFT 04/14] drm/msm/a6xx: Get a handle to the common UBWC config
2025-05-09 17:00 ` Konrad Dybcio
@ 2025-05-13 22:06 ` Rob Clark
2025-05-13 22:11 ` Konrad Dybcio
0 siblings, 1 reply; 43+ messages in thread
From: Rob Clark @ 2025-05-13 22:06 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Konrad Dybcio, Bjorn Andersson, Abhinav Kumar, Dmitry Baryshkov,
Akhil P Oommen, Sean Paul, David Airlie, Simona Vetter,
Marijn Suijten, linux-kernel, linux-arm-msm, dri-devel, freedreno
On Fri, May 9, 2025 at 10:00 AM Konrad Dybcio
<konrad.dybcio@oss.qualcomm.com> wrote:
>
> On 5/9/25 3:52 PM, Rob Clark wrote:
> > On Fri, May 9, 2025 at 5:31 AM Konrad Dybcio
> > <konrad.dybcio@oss.qualcomm.com> wrote:
> >>
> >> On 5/8/25 8:41 PM, Rob Clark wrote:
> >>> On Thu, May 8, 2025 at 11:13 AM Konrad Dybcio <konradybcio@kernel.org> wrote:
> >>>>
> >>>> From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> >>>>
> >>>> Start the great despaghettification by getting a pointer to the common
> >>>> UBWC configuration, which houses e.g. UBWC versions that we need to
> >>>> make decisions.
> >>>>
> >>>> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> >>>> ---
> >>>> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 16 ++++++++++++++--
> >>>> drivers/gpu/drm/msm/adreno/adreno_gpu.c | 6 ++++++
> >>>> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 3 +++
> >>>> 3 files changed, 23 insertions(+), 2 deletions(-)
> >>>>
> >>>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> >>>> index b161b5cd991fc645dfcd69754b82be9691775ffe..89eb725f0950f3679d6214366cfbd22d5bcf4bc7 100644
> >>>> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> >>>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> >>>> @@ -585,8 +585,13 @@ static void a6xx_set_cp_protect(struct msm_gpu *gpu)
> >>>> gpu_write(gpu, REG_A6XX_CP_PROTECT(protect->count_max - 1), protect->regs[i]);
> >>>> }
> >>>>
> >>>> -static void a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
> >>>> +static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
> >>>> {
> >>>> + /* Inherit the common config and make some necessary fixups */
> >>>> + gpu->common_ubwc_cfg = qcom_ubwc_config_get_data();
> >>>
> >>> This does look a bit funny given the devm_kzalloc() below.. I guess
> >>> just so that the ptr is never NULL?
> >>
> >> Yeah, would you prefer this is changed?
> >
> > I think having an all zeros ubwc cfg isn't really going to work
> > anyways, so probably drop the kzalloc(). Or if there is a case that
> > I'm not thinking of offhand where it makes sense to have an all 0's
> > cfg, then add a comment to avoid future head scratching, since
> > otherwise it looks like a bug to be fixed.
>
> So my own lack of comments bit me.
>
> Without the allocation this will fall apart badly..
> I added this hunk:
>
> ---------------------
> /* Inherit the common config and make some necessary fixups */
> common_cfg = if (IS_ERR(common_cfg))
> return ERR_PTR(-EINVAL);
>
> *adreno_gpu->ubwc_config = *common_cfg;
> ---------------------
>
> to get the common data but take away the const qualifier.. because
> we still override some HBB values and we can't yet fully trust the
> common config, as the smem getter is not yet plumbed up.
So I get that common_ubwc_cfg is the const thing without fixups (and
agree that it should say const), and ubwc_config is the fixed up
thing. But don't see how that necessitates the zeroalloc. Couldn't
you just:
if (!IS_ERR_OR_NULL(adreno_gpu->common_ubwc_cfg)
adreno_gpu->ubwc_config = *adreno_gpu->common_ubwc_cfg;
> I can add a commit discarding all the HBB overrides (matching or not)
> or we can keep the zeroalloc around for some time (i'd rather keep
> the function returning const so that when things are ready nobody gets
> to poke at the source of *truth*)
We can keep the overrides to start (although the goal should be to
remove them).. but qcom_ubwc_config_get_data() not finding anything
seems like more or less a fatal condition.
BR,
-R
^ permalink raw reply [flat|nested] 43+ messages in thread* Re: [PATCH RFT 04/14] drm/msm/a6xx: Get a handle to the common UBWC config
2025-05-13 22:06 ` Rob Clark
@ 2025-05-13 22:11 ` Konrad Dybcio
0 siblings, 0 replies; 43+ messages in thread
From: Konrad Dybcio @ 2025-05-13 22:11 UTC (permalink / raw)
To: Rob Clark, Konrad Dybcio
Cc: Konrad Dybcio, Bjorn Andersson, Abhinav Kumar, Dmitry Baryshkov,
Akhil P Oommen, Sean Paul, David Airlie, Simona Vetter,
Marijn Suijten, linux-kernel, linux-arm-msm, dri-devel, freedreno
On 5/14/25 12:06 AM, Rob Clark wrote:
> On Fri, May 9, 2025 at 10:00 AM Konrad Dybcio
> <konrad.dybcio@oss.qualcomm.com> wrote:
>>
>> On 5/9/25 3:52 PM, Rob Clark wrote:
>>> On Fri, May 9, 2025 at 5:31 AM Konrad Dybcio
>>> <konrad.dybcio@oss.qualcomm.com> wrote:
>>>>
>>>> On 5/8/25 8:41 PM, Rob Clark wrote:
>>>>> On Thu, May 8, 2025 at 11:13 AM Konrad Dybcio <konradybcio@kernel.org> wrote:
>>>>>>
>>>>>> From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>>>>>>
>>>>>> Start the great despaghettification by getting a pointer to the common
>>>>>> UBWC configuration, which houses e.g. UBWC versions that we need to
>>>>>> make decisions.
>>>>>>
>>>>>> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>>>>>> ---
>>>>>> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 16 ++++++++++++++--
>>>>>> drivers/gpu/drm/msm/adreno/adreno_gpu.c | 6 ++++++
>>>>>> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 3 +++
>>>>>> 3 files changed, 23 insertions(+), 2 deletions(-)
>>>>>>
>>>>>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
>>>>>> index b161b5cd991fc645dfcd69754b82be9691775ffe..89eb725f0950f3679d6214366cfbd22d5bcf4bc7 100644
>>>>>> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
>>>>>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
>>>>>> @@ -585,8 +585,13 @@ static void a6xx_set_cp_protect(struct msm_gpu *gpu)
>>>>>> gpu_write(gpu, REG_A6XX_CP_PROTECT(protect->count_max - 1), protect->regs[i]);
>>>>>> }
>>>>>>
>>>>>> -static void a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
>>>>>> +static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
>>>>>> {
>>>>>> + /* Inherit the common config and make some necessary fixups */
>>>>>> + gpu->common_ubwc_cfg = qcom_ubwc_config_get_data();
>>>>>
>>>>> This does look a bit funny given the devm_kzalloc() below.. I guess
>>>>> just so that the ptr is never NULL?
>>>>
>>>> Yeah, would you prefer this is changed?
>>>
>>> I think having an all zeros ubwc cfg isn't really going to work
>>> anyways, so probably drop the kzalloc(). Or if there is a case that
>>> I'm not thinking of offhand where it makes sense to have an all 0's
>>> cfg, then add a comment to avoid future head scratching, since
>>> otherwise it looks like a bug to be fixed.
>>
>> So my own lack of comments bit me.
>>
>> Without the allocation this will fall apart badly..
>> I added this hunk:
>>
>> ---------------------
>> /* Inherit the common config and make some necessary fixups */
>> common_cfg = if (IS_ERR(common_cfg))
>> return ERR_PTR(-EINVAL);
>>
>> *adreno_gpu->ubwc_config = *common_cfg;
>> ---------------------
>>
>> to get the common data but take away the const qualifier.. because
>> we still override some HBB values and we can't yet fully trust the
>> common config, as the smem getter is not yet plumbed up.
>
> So I get that common_ubwc_cfg is the const thing without fixups (and
> agree that it should say const), and ubwc_config is the fixed up
> thing. But don't see how that necessitates the zeroalloc. Couldn't
> you just:
>
>
> if (!IS_ERR_OR_NULL(adreno_gpu->common_ubwc_cfg)
> adreno_gpu->ubwc_config = *adreno_gpu->common_ubwc_cfg;
Aaaah I read into what me-a-week-ago thought and realized I did that so
that I can still make overrides in a5xx_gpu.c (where this data is
*always* hardcoded up until now) - I can simply squash the last patch
with this one and we should be gtg without the zeroalloc
>> I can add a commit discarding all the HBB overrides (matching or not)
>> or we can keep the zeroalloc around for some time (i'd rather keep
>> the function returning const so that when things are ready nobody gets
>> to poke at the source of *truth*)
>
> We can keep the overrides to start (although the goal should be to
> remove them).. but qcom_ubwc_config_get_data() not finding anything
> seems like more or less a fatal condition.
Indeed
Konrad
^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH RFT 05/14] drm/msm/a6xx: Resolve the meaning of AMSBC
2025-05-08 18:12 [RFT PATCH 00/14] Add a single source of truth for UBWC configuration data Konrad Dybcio
` (3 preceding siblings ...)
2025-05-08 18:12 ` [PATCH RFT 04/14] drm/msm/a6xx: Get a handle to the common UBWC config Konrad Dybcio
@ 2025-05-08 18:12 ` Konrad Dybcio
2025-05-08 19:16 ` Connor Abbott
2025-05-08 18:12 ` [PATCH RFT 06/14] drm/msm/a6xx: Simplify uavflagprd_inv detection Konrad Dybcio
` (8 subsequent siblings)
13 siblings, 1 reply; 43+ messages in thread
From: Konrad Dybcio @ 2025-05-08 18:12 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Clark, Abhinav Kumar,
Dmitry Baryshkov, Akhil P Oommen, Sean Paul, David Airlie,
Simona Vetter
Cc: Marijn Suijten, linux-kernel, linux-arm-msm, dri-devel, freedreno,
Konrad Dybcio
From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
The bit must be set to 1 if the UBWC encoder version is >= 3.0, drop it
as a separate field.
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 12 +++---------
1 file changed, 3 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 89eb725f0950f3679d6214366cfbd22d5bcf4bc7..5fe0e8e72930320282a856e1ff77994865360854 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -617,21 +617,16 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
if (adreno_is_a621(gpu)) {
gpu->ubwc_config.highest_bank_bit = 0;
- gpu->ubwc_config.amsbc = 1;
gpu->ubwc_config.uavflagprd_inv = 2;
}
if (adreno_is_a623(gpu)) {
gpu->ubwc_config.highest_bank_bit = 3;
- gpu->ubwc_config.amsbc = 1;
gpu->ubwc_config.rgb565_predicator = 1;
gpu->ubwc_config.uavflagprd_inv = 2;
gpu->ubwc_config.macrotile_mode = 1;
}
- if (adreno_is_a640_family(gpu))
- gpu->ubwc_config.amsbc = 1;
-
if (adreno_is_a680(gpu))
gpu->ubwc_config.macrotile_mode = 1;
@@ -642,7 +637,6 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
adreno_is_a740_family(gpu)) {
/* TODO: get ddr type from bootloader and use 2 for LPDDR4 */
gpu->ubwc_config.highest_bank_bit = 3;
- gpu->ubwc_config.amsbc = 1;
gpu->ubwc_config.rgb565_predicator = 1;
gpu->ubwc_config.uavflagprd_inv = 2;
gpu->ubwc_config.macrotile_mode = 1;
@@ -650,7 +644,6 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
if (adreno_is_a663(gpu)) {
gpu->ubwc_config.highest_bank_bit = 0;
- gpu->ubwc_config.amsbc = 1;
gpu->ubwc_config.rgb565_predicator = 1;
gpu->ubwc_config.uavflagprd_inv = 2;
gpu->ubwc_config.macrotile_mode = 1;
@@ -659,7 +652,6 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
if (adreno_is_7c3(gpu)) {
gpu->ubwc_config.highest_bank_bit = 1;
- gpu->ubwc_config.amsbc = 1;
gpu->ubwc_config.uavflagprd_inv = 2;
gpu->ubwc_config.macrotile_mode = 1;
}
@@ -675,7 +667,9 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
{
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
+ const struct qcom_ubwc_cfg_data *cfg = adreno_gpu->common_ubwc_cfg;
u32 hbb = adreno_gpu->ubwc_config.highest_bank_bit;
+ bool amsbc = cfg->ubwc_enc_version >= UBWC_3_0;
u32 hbb_hi = hbb >> 2;
u32 hbb_lo = hbb & 3;
u32 ubwc_mode = adreno_gpu->ubwc_config.ubwc_swizzle & 1;
@@ -684,7 +678,7 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL,
level2_swizzling_dis << 12 |
adreno_gpu->ubwc_config.rgb565_predicator << 11 |
- hbb_hi << 10 | adreno_gpu->ubwc_config.amsbc << 4 |
+ hbb_hi << 10 | amsbc << 4 |
adreno_gpu->ubwc_config.min_acc_len << 3 |
hbb_lo << 1 | ubwc_mode);
--
2.49.0
^ permalink raw reply related [flat|nested] 43+ messages in thread* Re: [PATCH RFT 05/14] drm/msm/a6xx: Resolve the meaning of AMSBC
2025-05-08 18:12 ` [PATCH RFT 05/14] drm/msm/a6xx: Resolve the meaning of AMSBC Konrad Dybcio
@ 2025-05-08 19:16 ` Connor Abbott
2025-05-09 12:31 ` Konrad Dybcio
0 siblings, 1 reply; 43+ messages in thread
From: Connor Abbott @ 2025-05-08 19:16 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Bjorn Andersson, Rob Clark, Abhinav Kumar, Dmitry Baryshkov,
Akhil P Oommen, Sean Paul, David Airlie, Simona Vetter,
Marijn Suijten, linux-kernel, linux-arm-msm, dri-devel, freedreno,
Konrad Dybcio
On Thu, May 8, 2025 at 2:13 PM Konrad Dybcio <konradybcio@kernel.org> wrote:
>
> From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>
> The bit must be set to 1 if the UBWC encoder version is >= 3.0, drop it
> as a separate field.
For these sorts of things, it's probably best to add a helper to the
common ubwc config header. Other blocks also have bits for enabling
AMSBC and similar things that also need to be set based on the UBWC
version.
Connor
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 12 +++---------
> 1 file changed, 3 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> index 89eb725f0950f3679d6214366cfbd22d5bcf4bc7..5fe0e8e72930320282a856e1ff77994865360854 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> @@ -617,21 +617,16 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
>
> if (adreno_is_a621(gpu)) {
> gpu->ubwc_config.highest_bank_bit = 0;
> - gpu->ubwc_config.amsbc = 1;
> gpu->ubwc_config.uavflagprd_inv = 2;
> }
>
> if (adreno_is_a623(gpu)) {
> gpu->ubwc_config.highest_bank_bit = 3;
> - gpu->ubwc_config.amsbc = 1;
> gpu->ubwc_config.rgb565_predicator = 1;
> gpu->ubwc_config.uavflagprd_inv = 2;
> gpu->ubwc_config.macrotile_mode = 1;
> }
>
> - if (adreno_is_a640_family(gpu))
> - gpu->ubwc_config.amsbc = 1;
> -
> if (adreno_is_a680(gpu))
> gpu->ubwc_config.macrotile_mode = 1;
>
> @@ -642,7 +637,6 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
> adreno_is_a740_family(gpu)) {
> /* TODO: get ddr type from bootloader and use 2 for LPDDR4 */
> gpu->ubwc_config.highest_bank_bit = 3;
> - gpu->ubwc_config.amsbc = 1;
> gpu->ubwc_config.rgb565_predicator = 1;
> gpu->ubwc_config.uavflagprd_inv = 2;
> gpu->ubwc_config.macrotile_mode = 1;
> @@ -650,7 +644,6 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
>
> if (adreno_is_a663(gpu)) {
> gpu->ubwc_config.highest_bank_bit = 0;
> - gpu->ubwc_config.amsbc = 1;
> gpu->ubwc_config.rgb565_predicator = 1;
> gpu->ubwc_config.uavflagprd_inv = 2;
> gpu->ubwc_config.macrotile_mode = 1;
> @@ -659,7 +652,6 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
>
> if (adreno_is_7c3(gpu)) {
> gpu->ubwc_config.highest_bank_bit = 1;
> - gpu->ubwc_config.amsbc = 1;
> gpu->ubwc_config.uavflagprd_inv = 2;
> gpu->ubwc_config.macrotile_mode = 1;
> }
> @@ -675,7 +667,9 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
> static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
> {
> struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
> + const struct qcom_ubwc_cfg_data *cfg = adreno_gpu->common_ubwc_cfg;
> u32 hbb = adreno_gpu->ubwc_config.highest_bank_bit;
> + bool amsbc = cfg->ubwc_enc_version >= UBWC_3_0;
> u32 hbb_hi = hbb >> 2;
> u32 hbb_lo = hbb & 3;
> u32 ubwc_mode = adreno_gpu->ubwc_config.ubwc_swizzle & 1;
> @@ -684,7 +678,7 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
> gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL,
> level2_swizzling_dis << 12 |
> adreno_gpu->ubwc_config.rgb565_predicator << 11 |
> - hbb_hi << 10 | adreno_gpu->ubwc_config.amsbc << 4 |
> + hbb_hi << 10 | amsbc << 4 |
> adreno_gpu->ubwc_config.min_acc_len << 3 |
> hbb_lo << 1 | ubwc_mode);
>
>
> --
> 2.49.0
>
^ permalink raw reply [flat|nested] 43+ messages in thread* Re: [PATCH RFT 05/14] drm/msm/a6xx: Resolve the meaning of AMSBC
2025-05-08 19:16 ` Connor Abbott
@ 2025-05-09 12:31 ` Konrad Dybcio
0 siblings, 0 replies; 43+ messages in thread
From: Konrad Dybcio @ 2025-05-09 12:31 UTC (permalink / raw)
To: Connor Abbott, Konrad Dybcio
Cc: Bjorn Andersson, Rob Clark, Abhinav Kumar, Dmitry Baryshkov,
Akhil P Oommen, Sean Paul, David Airlie, Simona Vetter,
Marijn Suijten, linux-kernel, linux-arm-msm, dri-devel, freedreno
On 5/8/25 9:16 PM, Connor Abbott wrote:
> On Thu, May 8, 2025 at 2:13 PM Konrad Dybcio <konradybcio@kernel.org> wrote:
>>
>> From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>>
>> The bit must be set to 1 if the UBWC encoder version is >= 3.0, drop it
>> as a separate field.
>
> For these sorts of things, it's probably best to add a helper to the
> common ubwc config header. Other blocks also have bits for enabling
> AMSBC and similar things that also need to be set based on the UBWC
> version.
Good idea
Konrad
^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH RFT 06/14] drm/msm/a6xx: Simplify uavflagprd_inv detection
2025-05-08 18:12 [RFT PATCH 00/14] Add a single source of truth for UBWC configuration data Konrad Dybcio
` (4 preceding siblings ...)
2025-05-08 18:12 ` [PATCH RFT 05/14] drm/msm/a6xx: Resolve the meaning of AMSBC Konrad Dybcio
@ 2025-05-08 18:12 ` Konrad Dybcio
2025-05-08 19:05 ` Connor Abbott
2025-05-08 18:12 ` [PATCH RFT 07/14] drm/msm/a6xx: Resolve the meaning of UBWC_MODE Konrad Dybcio
` (7 subsequent siblings)
13 siblings, 1 reply; 43+ messages in thread
From: Konrad Dybcio @ 2025-05-08 18:12 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Clark, Abhinav Kumar,
Dmitry Baryshkov, Akhil P Oommen, Sean Paul, David Airlie,
Simona Vetter
Cc: Marijn Suijten, linux-kernel, linux-arm-msm, dri-devel, freedreno,
Konrad Dybcio
From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Instead of setting it on a gpu-per-gpu basis, converge it to the
intended "is A650 family or A7xx".
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 12 +++---------
1 file changed, 3 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 5fe0e8e72930320282a856e1ff77994865360854..e1eab0906b6c460528da82a94a285ef181e0b479 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -593,7 +593,6 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
return -EINVAL;
gpu->ubwc_config.rgb565_predicator = 0;
- gpu->ubwc_config.uavflagprd_inv = 0;
gpu->ubwc_config.min_acc_len = 0;
gpu->ubwc_config.ubwc_swizzle = 0x6;
gpu->ubwc_config.macrotile_mode = 0;
@@ -615,15 +614,12 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
if (adreno_is_a619_holi(gpu))
gpu->ubwc_config.highest_bank_bit = 0;
- if (adreno_is_a621(gpu)) {
+ if (adreno_is_a621(gpu))
gpu->ubwc_config.highest_bank_bit = 0;
- gpu->ubwc_config.uavflagprd_inv = 2;
- }
if (adreno_is_a623(gpu)) {
gpu->ubwc_config.highest_bank_bit = 3;
gpu->ubwc_config.rgb565_predicator = 1;
- gpu->ubwc_config.uavflagprd_inv = 2;
gpu->ubwc_config.macrotile_mode = 1;
}
@@ -638,21 +634,18 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
/* TODO: get ddr type from bootloader and use 2 for LPDDR4 */
gpu->ubwc_config.highest_bank_bit = 3;
gpu->ubwc_config.rgb565_predicator = 1;
- gpu->ubwc_config.uavflagprd_inv = 2;
gpu->ubwc_config.macrotile_mode = 1;
}
if (adreno_is_a663(gpu)) {
gpu->ubwc_config.highest_bank_bit = 0;
gpu->ubwc_config.rgb565_predicator = 1;
- gpu->ubwc_config.uavflagprd_inv = 2;
gpu->ubwc_config.macrotile_mode = 1;
gpu->ubwc_config.ubwc_swizzle = 0x4;
}
if (adreno_is_7c3(gpu)) {
gpu->ubwc_config.highest_bank_bit = 1;
- gpu->ubwc_config.uavflagprd_inv = 2;
gpu->ubwc_config.macrotile_mode = 1;
}
@@ -667,6 +660,7 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
{
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
+ u8 uavflagprd_inv = adreno_is_a650_family(adreno_gpu) || adreno_is_a7xx(adreno_gpu) ? 2 : 0;
const struct qcom_ubwc_cfg_data *cfg = adreno_gpu->common_ubwc_cfg;
u32 hbb = adreno_gpu->ubwc_config.highest_bank_bit;
bool amsbc = cfg->ubwc_enc_version >= UBWC_3_0;
@@ -689,7 +683,7 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL,
level2_swizzling_dis << 12 | hbb_hi << 10 |
- adreno_gpu->ubwc_config.uavflagprd_inv << 4 |
+ uavflagprd_inv << 4 |
adreno_gpu->ubwc_config.min_acc_len << 3 |
hbb_lo << 1 | ubwc_mode);
--
2.49.0
^ permalink raw reply related [flat|nested] 43+ messages in thread* Re: [PATCH RFT 06/14] drm/msm/a6xx: Simplify uavflagprd_inv detection
2025-05-08 18:12 ` [PATCH RFT 06/14] drm/msm/a6xx: Simplify uavflagprd_inv detection Konrad Dybcio
@ 2025-05-08 19:05 ` Connor Abbott
2025-05-09 12:36 ` Konrad Dybcio
0 siblings, 1 reply; 43+ messages in thread
From: Connor Abbott @ 2025-05-08 19:05 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Bjorn Andersson, Rob Clark, Abhinav Kumar, Dmitry Baryshkov,
Akhil P Oommen, Sean Paul, David Airlie, Simona Vetter,
Marijn Suijten, linux-kernel, linux-arm-msm, dri-devel, freedreno,
Konrad Dybcio
On Thu, May 8, 2025 at 2:13 PM Konrad Dybcio <konradybcio@kernel.org> wrote:
>
> From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>
> Instead of setting it on a gpu-per-gpu basis, converge it to the
> intended "is A650 family or A7xx".
Can we also set this based on the UBWC version?
Connor
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 12 +++---------
> 1 file changed, 3 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> index 5fe0e8e72930320282a856e1ff77994865360854..e1eab0906b6c460528da82a94a285ef181e0b479 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> @@ -593,7 +593,6 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
> return -EINVAL;
>
> gpu->ubwc_config.rgb565_predicator = 0;
> - gpu->ubwc_config.uavflagprd_inv = 0;
> gpu->ubwc_config.min_acc_len = 0;
> gpu->ubwc_config.ubwc_swizzle = 0x6;
> gpu->ubwc_config.macrotile_mode = 0;
> @@ -615,15 +614,12 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
> if (adreno_is_a619_holi(gpu))
> gpu->ubwc_config.highest_bank_bit = 0;
>
> - if (adreno_is_a621(gpu)) {
> + if (adreno_is_a621(gpu))
> gpu->ubwc_config.highest_bank_bit = 0;
> - gpu->ubwc_config.uavflagprd_inv = 2;
> - }
>
> if (adreno_is_a623(gpu)) {
> gpu->ubwc_config.highest_bank_bit = 3;
> gpu->ubwc_config.rgb565_predicator = 1;
> - gpu->ubwc_config.uavflagprd_inv = 2;
> gpu->ubwc_config.macrotile_mode = 1;
> }
>
> @@ -638,21 +634,18 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
> /* TODO: get ddr type from bootloader and use 2 for LPDDR4 */
> gpu->ubwc_config.highest_bank_bit = 3;
> gpu->ubwc_config.rgb565_predicator = 1;
> - gpu->ubwc_config.uavflagprd_inv = 2;
> gpu->ubwc_config.macrotile_mode = 1;
> }
>
> if (adreno_is_a663(gpu)) {
> gpu->ubwc_config.highest_bank_bit = 0;
> gpu->ubwc_config.rgb565_predicator = 1;
> - gpu->ubwc_config.uavflagprd_inv = 2;
> gpu->ubwc_config.macrotile_mode = 1;
> gpu->ubwc_config.ubwc_swizzle = 0x4;
> }
>
> if (adreno_is_7c3(gpu)) {
> gpu->ubwc_config.highest_bank_bit = 1;
> - gpu->ubwc_config.uavflagprd_inv = 2;
> gpu->ubwc_config.macrotile_mode = 1;
> }
>
> @@ -667,6 +660,7 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
> static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
> {
> struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
> + u8 uavflagprd_inv = adreno_is_a650_family(adreno_gpu) || adreno_is_a7xx(adreno_gpu) ? 2 : 0;
> const struct qcom_ubwc_cfg_data *cfg = adreno_gpu->common_ubwc_cfg;
> u32 hbb = adreno_gpu->ubwc_config.highest_bank_bit;
> bool amsbc = cfg->ubwc_enc_version >= UBWC_3_0;
> @@ -689,7 +683,7 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
>
> gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL,
> level2_swizzling_dis << 12 | hbb_hi << 10 |
> - adreno_gpu->ubwc_config.uavflagprd_inv << 4 |
> + uavflagprd_inv << 4 |
> adreno_gpu->ubwc_config.min_acc_len << 3 |
> hbb_lo << 1 | ubwc_mode);
>
>
> --
> 2.49.0
>
^ permalink raw reply [flat|nested] 43+ messages in thread* Re: [PATCH RFT 06/14] drm/msm/a6xx: Simplify uavflagprd_inv detection
2025-05-08 19:05 ` Connor Abbott
@ 2025-05-09 12:36 ` Konrad Dybcio
0 siblings, 0 replies; 43+ messages in thread
From: Konrad Dybcio @ 2025-05-09 12:36 UTC (permalink / raw)
To: Connor Abbott, Konrad Dybcio
Cc: Bjorn Andersson, Rob Clark, Abhinav Kumar, Dmitry Baryshkov,
Akhil P Oommen, Sean Paul, David Airlie, Simona Vetter,
Marijn Suijten, linux-kernel, linux-arm-msm, dri-devel, freedreno
On 5/8/25 9:05 PM, Connor Abbott wrote:
> On Thu, May 8, 2025 at 2:13 PM Konrad Dybcio <konradybcio@kernel.org> wrote:
>>
>> From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>>
>> Instead of setting it on a gpu-per-gpu basis, converge it to the
>> intended "is A650 family or A7xx".
>
> Can we also set this based on the UBWC version?
Unfortunately that doesn't give us a 100% match
Konrad
^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH RFT 07/14] drm/msm/a6xx: Resolve the meaning of UBWC_MODE
2025-05-08 18:12 [RFT PATCH 00/14] Add a single source of truth for UBWC configuration data Konrad Dybcio
` (5 preceding siblings ...)
2025-05-08 18:12 ` [PATCH RFT 06/14] drm/msm/a6xx: Simplify uavflagprd_inv detection Konrad Dybcio
@ 2025-05-08 18:12 ` Konrad Dybcio
2025-05-08 18:25 ` Connor Abbott
2025-05-08 18:12 ` [PATCH RFT 08/14] drm/msm/a6xx: Replace '2' with BIT(1) in level2_swizzling_dis calc Konrad Dybcio
` (6 subsequent siblings)
13 siblings, 1 reply; 43+ messages in thread
From: Konrad Dybcio @ 2025-05-08 18:12 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Clark, Abhinav Kumar,
Dmitry Baryshkov, Akhil P Oommen, Sean Paul, David Airlie,
Simona Vetter
Cc: Marijn Suijten, linux-kernel, linux-arm-msm, dri-devel, freedreno,
Konrad Dybcio
From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
This bit is set iff the UBWC version is 1.0. That notably does not
include QCM2290's "no UBWC".
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index e1eab0906b6c460528da82a94a285ef181e0b479..d47726ea8818a9660eadd52d97dde1489a884684 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -663,10 +663,10 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
u8 uavflagprd_inv = adreno_is_a650_family(adreno_gpu) || adreno_is_a7xx(adreno_gpu) ? 2 : 0;
const struct qcom_ubwc_cfg_data *cfg = adreno_gpu->common_ubwc_cfg;
u32 hbb = adreno_gpu->ubwc_config.highest_bank_bit;
+ bool ubwc_mode = cfg->ubwc_enc_version == UBWC_1_0;
bool amsbc = cfg->ubwc_enc_version >= UBWC_3_0;
u32 hbb_hi = hbb >> 2;
u32 hbb_lo = hbb & 3;
- u32 ubwc_mode = adreno_gpu->ubwc_config.ubwc_swizzle & 1;
u32 level2_swizzling_dis = !(adreno_gpu->ubwc_config.ubwc_swizzle & 2);
gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL,
--
2.49.0
^ permalink raw reply related [flat|nested] 43+ messages in thread* Re: [PATCH RFT 07/14] drm/msm/a6xx: Resolve the meaning of UBWC_MODE
2025-05-08 18:12 ` [PATCH RFT 07/14] drm/msm/a6xx: Resolve the meaning of UBWC_MODE Konrad Dybcio
@ 2025-05-08 18:25 ` Connor Abbott
2025-05-09 12:37 ` Konrad Dybcio
0 siblings, 1 reply; 43+ messages in thread
From: Connor Abbott @ 2025-05-08 18:25 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Bjorn Andersson, Rob Clark, Abhinav Kumar, Dmitry Baryshkov,
Akhil P Oommen, Sean Paul, David Airlie, Simona Vetter,
Marijn Suijten, linux-kernel, linux-arm-msm, dri-devel, freedreno,
Konrad Dybcio
On Thu, May 8, 2025 at 2:14 PM Konrad Dybcio <konradybcio@kernel.org> wrote:
>
> From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>
> This bit is set iff the UBWC version is 1.0. That notably does not
> include QCM2290's "no UBWC".
While this is technically true, AFAIK the only difference between UBWC
1.0 and 2.0 is that newer UBWC disables level 1 bank swizzling, which
is why I originally wrote it this way. There's a bit of redundancy
between the UBWC version and ubwc_swizzle bit 0.
Connor
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> index e1eab0906b6c460528da82a94a285ef181e0b479..d47726ea8818a9660eadd52d97dde1489a884684 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> @@ -663,10 +663,10 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
> u8 uavflagprd_inv = adreno_is_a650_family(adreno_gpu) || adreno_is_a7xx(adreno_gpu) ? 2 : 0;
> const struct qcom_ubwc_cfg_data *cfg = adreno_gpu->common_ubwc_cfg;
> u32 hbb = adreno_gpu->ubwc_config.highest_bank_bit;
> + bool ubwc_mode = cfg->ubwc_enc_version == UBWC_1_0;
> bool amsbc = cfg->ubwc_enc_version >= UBWC_3_0;
> u32 hbb_hi = hbb >> 2;
> u32 hbb_lo = hbb & 3;
> - u32 ubwc_mode = adreno_gpu->ubwc_config.ubwc_swizzle & 1;
> u32 level2_swizzling_dis = !(adreno_gpu->ubwc_config.ubwc_swizzle & 2);
>
> gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL,
>
> --
> 2.49.0
>
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH RFT 07/14] drm/msm/a6xx: Resolve the meaning of UBWC_MODE
2025-05-08 18:25 ` Connor Abbott
@ 2025-05-09 12:37 ` Konrad Dybcio
2025-05-09 12:39 ` Konrad Dybcio
0 siblings, 1 reply; 43+ messages in thread
From: Konrad Dybcio @ 2025-05-09 12:37 UTC (permalink / raw)
To: Connor Abbott, Konrad Dybcio
Cc: Bjorn Andersson, Rob Clark, Abhinav Kumar, Dmitry Baryshkov,
Akhil P Oommen, Sean Paul, David Airlie, Simona Vetter,
Marijn Suijten, linux-kernel, linux-arm-msm, dri-devel, freedreno
On 5/8/25 8:25 PM, Connor Abbott wrote:
> On Thu, May 8, 2025 at 2:14 PM Konrad Dybcio <konradybcio@kernel.org> wrote:
>>
>> From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>>
>> This bit is set iff the UBWC version is 1.0. That notably does not
>> include QCM2290's "no UBWC".
>
> While this is technically true, AFAIK the only difference between UBWC
> 1.0 and 2.0 is that newer UBWC disables level 1 bank swizzling, which
> is why I originally wrote it this way. There's a bit of redundancy
> between the UBWC version and ubwc_swizzle bit 0.
It turns out to be a hardware matter
Konrad
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH RFT 07/14] drm/msm/a6xx: Resolve the meaning of UBWC_MODE
2025-05-09 12:37 ` Konrad Dybcio
@ 2025-05-09 12:39 ` Konrad Dybcio
0 siblings, 0 replies; 43+ messages in thread
From: Konrad Dybcio @ 2025-05-09 12:39 UTC (permalink / raw)
To: Konrad Dybcio, Connor Abbott, Konrad Dybcio
Cc: Bjorn Andersson, Rob Clark, Abhinav Kumar, Dmitry Baryshkov,
Akhil P Oommen, Sean Paul, David Airlie, Simona Vetter,
Marijn Suijten, linux-kernel, linux-arm-msm, dri-devel, freedreno
On 5/9/25 2:37 PM, Konrad Dybcio wrote:
> On 5/8/25 8:25 PM, Connor Abbott wrote:
>> On Thu, May 8, 2025 at 2:14 PM Konrad Dybcio <konradybcio@kernel.org> wrote:
>>>
>>> From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>>>
>>> This bit is set iff the UBWC version is 1.0. That notably does not
>>> include QCM2290's "no UBWC".
>>
>> While this is technically true, AFAIK the only difference between UBWC
>> 1.0 and 2.0 is that newer UBWC disables level 1 bank swizzling, which
>> is why I originally wrote it this way. There's a bit of redundancy
>> between the UBWC version and ubwc_swizzle bit 0.
>
> It turns out to be a hardware matter
Well you just said that.. in any case, i can do either (or both with a
sanity check)
Konrad
^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH RFT 08/14] drm/msm/a6xx: Replace '2' with BIT(1) in level2_swizzling_dis calc
2025-05-08 18:12 [RFT PATCH 00/14] Add a single source of truth for UBWC configuration data Konrad Dybcio
` (6 preceding siblings ...)
2025-05-08 18:12 ` [PATCH RFT 07/14] drm/msm/a6xx: Resolve the meaning of UBWC_MODE Konrad Dybcio
@ 2025-05-08 18:12 ` Konrad Dybcio
2025-05-08 18:12 ` [PATCH RFT 09/14] drm/msm/a6xx: Resolve the meaning of rgb565_predicator Konrad Dybcio
` (5 subsequent siblings)
13 siblings, 0 replies; 43+ messages in thread
From: Konrad Dybcio @ 2025-05-08 18:12 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Clark, Abhinav Kumar,
Dmitry Baryshkov, Akhil P Oommen, Sean Paul, David Airlie,
Simona Vetter
Cc: Marijn Suijten, linux-kernel, linux-arm-msm, dri-devel, freedreno,
Konrad Dybcio
From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
ubwc_swizzle is a bitmask. Check for a bit to make it more obvious.
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index d47726ea8818a9660eadd52d97dde1489a884684..afe4fa8e9325988af37ff12adb61faae66d746ba 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -662,12 +662,12 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
u8 uavflagprd_inv = adreno_is_a650_family(adreno_gpu) || adreno_is_a7xx(adreno_gpu) ? 2 : 0;
const struct qcom_ubwc_cfg_data *cfg = adreno_gpu->common_ubwc_cfg;
+ u32 level2_swizzling_dis = !(cfg->ubwc_swizzle & BIT(1));
u32 hbb = adreno_gpu->ubwc_config.highest_bank_bit;
bool ubwc_mode = cfg->ubwc_enc_version == UBWC_1_0;
bool amsbc = cfg->ubwc_enc_version >= UBWC_3_0;
u32 hbb_hi = hbb >> 2;
u32 hbb_lo = hbb & 3;
- u32 level2_swizzling_dis = !(adreno_gpu->ubwc_config.ubwc_swizzle & 2);
gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL,
level2_swizzling_dis << 12 |
--
2.49.0
^ permalink raw reply related [flat|nested] 43+ messages in thread* [PATCH RFT 09/14] drm/msm/a6xx: Resolve the meaning of rgb565_predicator
2025-05-08 18:12 [RFT PATCH 00/14] Add a single source of truth for UBWC configuration data Konrad Dybcio
` (7 preceding siblings ...)
2025-05-08 18:12 ` [PATCH RFT 08/14] drm/msm/a6xx: Replace '2' with BIT(1) in level2_swizzling_dis calc Konrad Dybcio
@ 2025-05-08 18:12 ` Konrad Dybcio
2025-05-08 18:12 ` [PATCH RFT 10/14] drm/msm/a6xx: Stop tracking macrotile_mode (again) Konrad Dybcio
` (4 subsequent siblings)
13 siblings, 0 replies; 43+ messages in thread
From: Konrad Dybcio @ 2025-05-08 18:12 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Clark, Abhinav Kumar,
Dmitry Baryshkov, Akhil P Oommen, Sean Paul, David Airlie,
Simona Vetter
Cc: Marijn Suijten, linux-kernel, linux-arm-msm, dri-devel, freedreno,
Konrad Dybcio
From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
It's supposed to be on when the UBWC encoder version is >= 4.0.
Drop the per-GPU assignments.
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 7 ++-----
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index afe4fa8e9325988af37ff12adb61faae66d746ba..60f89a2d851a5c383fc14cce4c483f630132a9a6 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -592,7 +592,6 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
if (IS_ERR(gpu->common_ubwc_cfg))
return -EINVAL;
- gpu->ubwc_config.rgb565_predicator = 0;
gpu->ubwc_config.min_acc_len = 0;
gpu->ubwc_config.ubwc_swizzle = 0x6;
gpu->ubwc_config.macrotile_mode = 0;
@@ -619,7 +618,6 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
if (adreno_is_a623(gpu)) {
gpu->ubwc_config.highest_bank_bit = 3;
- gpu->ubwc_config.rgb565_predicator = 1;
gpu->ubwc_config.macrotile_mode = 1;
}
@@ -633,13 +631,11 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
adreno_is_a740_family(gpu)) {
/* TODO: get ddr type from bootloader and use 2 for LPDDR4 */
gpu->ubwc_config.highest_bank_bit = 3;
- gpu->ubwc_config.rgb565_predicator = 1;
gpu->ubwc_config.macrotile_mode = 1;
}
if (adreno_is_a663(gpu)) {
gpu->ubwc_config.highest_bank_bit = 0;
- gpu->ubwc_config.rgb565_predicator = 1;
gpu->ubwc_config.macrotile_mode = 1;
gpu->ubwc_config.ubwc_swizzle = 0x4;
}
@@ -662,6 +658,7 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
u8 uavflagprd_inv = adreno_is_a650_family(adreno_gpu) || adreno_is_a7xx(adreno_gpu) ? 2 : 0;
const struct qcom_ubwc_cfg_data *cfg = adreno_gpu->common_ubwc_cfg;
+ bool rgb565_predicator = cfg->ubwc_enc_version >= UBWC_4_0;
u32 level2_swizzling_dis = !(cfg->ubwc_swizzle & BIT(1));
u32 hbb = adreno_gpu->ubwc_config.highest_bank_bit;
bool ubwc_mode = cfg->ubwc_enc_version == UBWC_1_0;
@@ -671,7 +668,7 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL,
level2_swizzling_dis << 12 |
- adreno_gpu->ubwc_config.rgb565_predicator << 11 |
+ rgb565_predicator << 11 |
hbb_hi << 10 | amsbc << 4 |
adreno_gpu->ubwc_config.min_acc_len << 3 |
hbb_lo << 1 | ubwc_mode);
--
2.49.0
^ permalink raw reply related [flat|nested] 43+ messages in thread* [PATCH RFT 10/14] drm/msm/a6xx: Stop tracking macrotile_mode (again)
2025-05-08 18:12 [RFT PATCH 00/14] Add a single source of truth for UBWC configuration data Konrad Dybcio
` (8 preceding siblings ...)
2025-05-08 18:12 ` [PATCH RFT 09/14] drm/msm/a6xx: Resolve the meaning of rgb565_predicator Konrad Dybcio
@ 2025-05-08 18:12 ` Konrad Dybcio
2025-05-08 18:33 ` Connor Abbott
2025-05-08 18:12 ` [PATCH RFT 11/14] drm/msm/a6xx: Simplify min_acc_len calculation Konrad Dybcio
` (3 subsequent siblings)
13 siblings, 1 reply; 43+ messages in thread
From: Konrad Dybcio @ 2025-05-08 18:12 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Clark, Abhinav Kumar,
Dmitry Baryshkov, Akhil P Oommen, Sean Paul, David Airlie,
Simona Vetter
Cc: Marijn Suijten, linux-kernel, linux-arm-msm, dri-devel, freedreno,
Konrad Dybcio
From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
SC8180X (A680) and SA8775P (A663) require a write to that register,
while other SKUs are fine with the default value. Don't overwrite it
needlessly, requiring the developer to read the value back from
hardware just to put it in the driver again, introducing much more room
for error.
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 19 +++++--------------
1 file changed, 5 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 60f89a2d851a5c383fc14cce4c483f630132a9a6..bee7e9685aa3ea282fb20ef479e4d243d28418f7 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -594,7 +594,6 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
gpu->ubwc_config.min_acc_len = 0;
gpu->ubwc_config.ubwc_swizzle = 0x6;
- gpu->ubwc_config.macrotile_mode = 0;
gpu->ubwc_config.highest_bank_bit = 2;
if (adreno_is_a610(gpu)) {
@@ -616,13 +615,8 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
if (adreno_is_a621(gpu))
gpu->ubwc_config.highest_bank_bit = 0;
- if (adreno_is_a623(gpu)) {
+ if (adreno_is_a623(gpu))
gpu->ubwc_config.highest_bank_bit = 3;
- gpu->ubwc_config.macrotile_mode = 1;
- }
-
- if (adreno_is_a680(gpu))
- gpu->ubwc_config.macrotile_mode = 1;
if (adreno_is_a650(gpu) ||
adreno_is_a660(gpu) ||
@@ -631,19 +625,15 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
adreno_is_a740_family(gpu)) {
/* TODO: get ddr type from bootloader and use 2 for LPDDR4 */
gpu->ubwc_config.highest_bank_bit = 3;
- gpu->ubwc_config.macrotile_mode = 1;
}
if (adreno_is_a663(gpu)) {
gpu->ubwc_config.highest_bank_bit = 0;
- gpu->ubwc_config.macrotile_mode = 1;
gpu->ubwc_config.ubwc_swizzle = 0x4;
}
- if (adreno_is_7c3(gpu)) {
+ if (adreno_is_7c3(gpu))
gpu->ubwc_config.highest_bank_bit = 1;
- gpu->ubwc_config.macrotile_mode = 1;
- }
if (adreno_is_a702(gpu)) {
gpu->ubwc_config.highest_bank_bit = 1;
@@ -691,8 +681,9 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL,
adreno_gpu->ubwc_config.min_acc_len << 23 | hbb_lo << 21);
- gpu_write(gpu, REG_A6XX_RBBM_NC_MODE_CNTL,
- adreno_gpu->ubwc_config.macrotile_mode);
+ /* The reset value only needs altering in some cases */
+ if (adreno_is_a680(adreno_gpu) || adreno_is_a663(adreno_gpu))
+ gpu_write(gpu, REG_A6XX_RBBM_NC_MODE_CNTL, BIT(0));
}
static void a7xx_patch_pwrup_reglist(struct msm_gpu *gpu)
--
2.49.0
^ permalink raw reply related [flat|nested] 43+ messages in thread* Re: [PATCH RFT 10/14] drm/msm/a6xx: Stop tracking macrotile_mode (again)
2025-05-08 18:12 ` [PATCH RFT 10/14] drm/msm/a6xx: Stop tracking macrotile_mode (again) Konrad Dybcio
@ 2025-05-08 18:33 ` Connor Abbott
2025-05-09 12:45 ` Konrad Dybcio
0 siblings, 1 reply; 43+ messages in thread
From: Connor Abbott @ 2025-05-08 18:33 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Bjorn Andersson, Rob Clark, Abhinav Kumar, Dmitry Baryshkov,
Akhil P Oommen, Sean Paul, David Airlie, Simona Vetter,
Marijn Suijten, linux-kernel, linux-arm-msm, dri-devel, freedreno,
Konrad Dybcio
On Thu, May 8, 2025 at 2:14 PM Konrad Dybcio <konradybcio@kernel.org> wrote:
>
> From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>
> SC8180X (A680) and SA8775P (A663) require a write to that register,
> while other SKUs are fine with the default value. Don't overwrite it
> needlessly, requiring the developer to read the value back from
> hardware just to put it in the driver again, introducing much more room
> for error.
I'm not sure I understand that last sentence. The original reason I
always wrote it was that for host image copy we need to know the value
of macrotile_mode, so again the value exposed to userspace must match
what's set in the HW. We can't read the value from the HW and send it
to userspace, because userspace queries this when creating the
physical device during device enumeration and we really don't want to
spuriously turn on the device then. That means the safest thing is to
always program it, guaranteeing that it always matches. Otherwise we
just have to hope that the default value matches what we expect it to
be.
I know you're copying this from kgsl, but kgsl doesn't expose the
macrotile_mode to userspace. I expect that HIC was added afterwards
and only works via hacks there (if it's even supported at all on the
relevant SoCs).
Connor
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 19 +++++--------------
> 1 file changed, 5 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> index 60f89a2d851a5c383fc14cce4c483f630132a9a6..bee7e9685aa3ea282fb20ef479e4d243d28418f7 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> @@ -594,7 +594,6 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
>
> gpu->ubwc_config.min_acc_len = 0;
> gpu->ubwc_config.ubwc_swizzle = 0x6;
> - gpu->ubwc_config.macrotile_mode = 0;
> gpu->ubwc_config.highest_bank_bit = 2;
>
> if (adreno_is_a610(gpu)) {
> @@ -616,13 +615,8 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
> if (adreno_is_a621(gpu))
> gpu->ubwc_config.highest_bank_bit = 0;
>
> - if (adreno_is_a623(gpu)) {
> + if (adreno_is_a623(gpu))
> gpu->ubwc_config.highest_bank_bit = 3;
> - gpu->ubwc_config.macrotile_mode = 1;
> - }
> -
> - if (adreno_is_a680(gpu))
> - gpu->ubwc_config.macrotile_mode = 1;
>
> if (adreno_is_a650(gpu) ||
> adreno_is_a660(gpu) ||
> @@ -631,19 +625,15 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
> adreno_is_a740_family(gpu)) {
> /* TODO: get ddr type from bootloader and use 2 for LPDDR4 */
> gpu->ubwc_config.highest_bank_bit = 3;
> - gpu->ubwc_config.macrotile_mode = 1;
> }
>
> if (adreno_is_a663(gpu)) {
> gpu->ubwc_config.highest_bank_bit = 0;
> - gpu->ubwc_config.macrotile_mode = 1;
> gpu->ubwc_config.ubwc_swizzle = 0x4;
> }
>
> - if (adreno_is_7c3(gpu)) {
> + if (adreno_is_7c3(gpu))
> gpu->ubwc_config.highest_bank_bit = 1;
> - gpu->ubwc_config.macrotile_mode = 1;
> - }
>
> if (adreno_is_a702(gpu)) {
> gpu->ubwc_config.highest_bank_bit = 1;
> @@ -691,8 +681,9 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
> gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL,
> adreno_gpu->ubwc_config.min_acc_len << 23 | hbb_lo << 21);
>
> - gpu_write(gpu, REG_A6XX_RBBM_NC_MODE_CNTL,
> - adreno_gpu->ubwc_config.macrotile_mode);
> + /* The reset value only needs altering in some cases */
> + if (adreno_is_a680(adreno_gpu) || adreno_is_a663(adreno_gpu))
> + gpu_write(gpu, REG_A6XX_RBBM_NC_MODE_CNTL, BIT(0));
> }
>
> static void a7xx_patch_pwrup_reglist(struct msm_gpu *gpu)
>
> --
> 2.49.0
>
^ permalink raw reply [flat|nested] 43+ messages in thread* Re: [PATCH RFT 10/14] drm/msm/a6xx: Stop tracking macrotile_mode (again)
2025-05-08 18:33 ` Connor Abbott
@ 2025-05-09 12:45 ` Konrad Dybcio
2025-05-09 14:52 ` Connor Abbott
0 siblings, 1 reply; 43+ messages in thread
From: Konrad Dybcio @ 2025-05-09 12:45 UTC (permalink / raw)
To: Connor Abbott, Konrad Dybcio
Cc: Bjorn Andersson, Rob Clark, Abhinav Kumar, Dmitry Baryshkov,
Akhil P Oommen, Sean Paul, David Airlie, Simona Vetter,
Marijn Suijten, linux-kernel, linux-arm-msm, dri-devel, freedreno,
Konrad Dybcio
On 5/8/25 8:33 PM, Connor Abbott wrote:
> On Thu, May 8, 2025 at 2:14 PM Konrad Dybcio <konradybcio@kernel.org> wrote:
>>
>> From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>>
>> SC8180X (A680) and SA8775P (A663) require a write to that register,
>> while other SKUs are fine with the default value. Don't overwrite it
>> needlessly, requiring the developer to read the value back from
>> hardware just to put it in the driver again, introducing much more room
>> for error.
>
> I'm not sure I understand that last sentence. The original reason I
> always wrote it was that for host image copy we need to know the value
> of macrotile_mode, so again the value exposed to userspace must match
> what's set in the HW. We can't read the value from the HW and send it
> to userspace, because userspace queries this when creating the
> physical device during device enumeration and we really don't want to
> spuriously turn on the device then. That means the safest thing is to
> always program it, guaranteeing that it always matches. Otherwise we
> just have to hope that the default value matches what we expect it to
> be.
>
> I know you're copying this from kgsl, but kgsl doesn't expose the
> macrotile_mode to userspace. I expect that HIC was added afterwards
> and only works via hacks there (if it's even supported at all on the
> relevant SoCs).
Alright, I think I'll include it in the common UBWC config (even though
it only concerns the GPU), as IIUC it may differ between platforms
implementing the same GPU SKU
Konrad
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH RFT 10/14] drm/msm/a6xx: Stop tracking macrotile_mode (again)
2025-05-09 12:45 ` Konrad Dybcio
@ 2025-05-09 14:52 ` Connor Abbott
0 siblings, 0 replies; 43+ messages in thread
From: Connor Abbott @ 2025-05-09 14:52 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Konrad Dybcio, Bjorn Andersson, Rob Clark, Abhinav Kumar,
Dmitry Baryshkov, Akhil P Oommen, Sean Paul, David Airlie,
Simona Vetter, Marijn Suijten, linux-kernel, linux-arm-msm,
dri-devel, freedreno
On Fri, May 9, 2025 at 8:45 AM Konrad Dybcio
<konrad.dybcio@oss.qualcomm.com> wrote:
>
> On 5/8/25 8:33 PM, Connor Abbott wrote:
> > On Thu, May 8, 2025 at 2:14 PM Konrad Dybcio <konradybcio@kernel.org> wrote:
> >>
> >> From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> >>
> >> SC8180X (A680) and SA8775P (A663) require a write to that register,
> >> while other SKUs are fine with the default value. Don't overwrite it
> >> needlessly, requiring the developer to read the value back from
> >> hardware just to put it in the driver again, introducing much more room
> >> for error.
> >
> > I'm not sure I understand that last sentence. The original reason I
> > always wrote it was that for host image copy we need to know the value
> > of macrotile_mode, so again the value exposed to userspace must match
> > what's set in the HW. We can't read the value from the HW and send it
> > to userspace, because userspace queries this when creating the
> > physical device during device enumeration and we really don't want to
> > spuriously turn on the device then. That means the safest thing is to
> > always program it, guaranteeing that it always matches. Otherwise we
> > just have to hope that the default value matches what we expect it to
> > be.
> >
> > I know you're copying this from kgsl, but kgsl doesn't expose the
> > macrotile_mode to userspace. I expect that HIC was added afterwards
> > and only works via hacks there (if it's even supported at all on the
> > relevant SoCs).
>
> Alright, I think I'll include it in the common UBWC config (even though
> it only concerns the GPU), as IIUC it may differ between platforms
> implementing the same GPU SKU
>
> Konrad
It most definitely does not concern just the GPU. It determines the
way tiles are swizzled within a macrotile so it also has to be in sync
between blocks.
Also, as said in the comments it's introduced with UBWC 3.1, so you
could turn this into another getter based on the version if you
introduce UBWC_3_1. In a future where we have proper modifiers derived
from this config struct instead of the current lie that everything is
the same, it would save us a bit.
Connor
^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH RFT 11/14] drm/msm/a6xx: Simplify min_acc_len calculation
2025-05-08 18:12 [RFT PATCH 00/14] Add a single source of truth for UBWC configuration data Konrad Dybcio
` (9 preceding siblings ...)
2025-05-08 18:12 ` [PATCH RFT 10/14] drm/msm/a6xx: Stop tracking macrotile_mode (again) Konrad Dybcio
@ 2025-05-08 18:12 ` Konrad Dybcio
2025-05-08 18:12 ` [PATCH RFT 12/14] drm/msm/adreno: Switch to the common UBWC config struct Konrad Dybcio
` (2 subsequent siblings)
13 siblings, 0 replies; 43+ messages in thread
From: Konrad Dybcio @ 2025-05-08 18:12 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Clark, Abhinav Kumar,
Dmitry Baryshkov, Akhil P Oommen, Sean Paul, David Airlie,
Simona Vetter
Cc: Marijn Suijten, linux-kernel, linux-arm-msm, dri-devel, freedreno,
Konrad Dybcio
From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
It's only necessary for some lower end parts.
Also rename it to min_acc_len_64b to denote that if set, the minimum
access length is 64 bits, 32b otherwise.
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 15 ++++++---------
1 file changed, 6 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index bee7e9685aa3ea282fb20ef479e4d243d28418f7..d297890dfba60c6110fb8571e1f46729390302ed 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -592,13 +592,11 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
if (IS_ERR(gpu->common_ubwc_cfg))
return -EINVAL;
- gpu->ubwc_config.min_acc_len = 0;
gpu->ubwc_config.ubwc_swizzle = 0x6;
gpu->ubwc_config.highest_bank_bit = 2;
if (adreno_is_a610(gpu)) {
gpu->ubwc_config.highest_bank_bit = 0;
- gpu->ubwc_config.min_acc_len = 1;
gpu->ubwc_config.ubwc_swizzle = 0x7;
}
@@ -635,10 +633,8 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
if (adreno_is_7c3(gpu))
gpu->ubwc_config.highest_bank_bit = 1;
- if (adreno_is_a702(gpu)) {
+ if (adreno_is_a702(gpu))
gpu->ubwc_config.highest_bank_bit = 1;
- gpu->ubwc_config.min_acc_len = 1;
- }
return 0;
}
@@ -647,6 +643,7 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
{
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
u8 uavflagprd_inv = adreno_is_a650_family(adreno_gpu) || adreno_is_a7xx(adreno_gpu) ? 2 : 0;
+ bool min_acc_len_64b = adreno_is_a610(adreno_gpu) || adreno_is_a702(adreno_gpu);
const struct qcom_ubwc_cfg_data *cfg = adreno_gpu->common_ubwc_cfg;
bool rgb565_predicator = cfg->ubwc_enc_version >= UBWC_4_0;
u32 level2_swizzling_dis = !(cfg->ubwc_swizzle & BIT(1));
@@ -660,18 +657,18 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
level2_swizzling_dis << 12 |
rgb565_predicator << 11 |
hbb_hi << 10 | amsbc << 4 |
- adreno_gpu->ubwc_config.min_acc_len << 3 |
+ min_acc_len_64b << 3 |
hbb_lo << 1 | ubwc_mode);
gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL,
level2_swizzling_dis << 6 | hbb_hi << 4 |
- adreno_gpu->ubwc_config.min_acc_len << 3 |
+ min_acc_len_64b << 3 |
hbb_lo << 1 | ubwc_mode);
gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL,
level2_swizzling_dis << 12 | hbb_hi << 10 |
uavflagprd_inv << 4 |
- adreno_gpu->ubwc_config.min_acc_len << 3 |
+ min_acc_len_64b << 3 |
hbb_lo << 1 | ubwc_mode);
if (adreno_is_a7xx(adreno_gpu))
@@ -679,7 +676,7 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
FIELD_PREP(GENMASK(8, 5), hbb_lo));
gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL,
- adreno_gpu->ubwc_config.min_acc_len << 23 | hbb_lo << 21);
+ min_acc_len_64b << 23 | hbb_lo << 21);
/* The reset value only needs altering in some cases */
if (adreno_is_a680(adreno_gpu) || adreno_is_a663(adreno_gpu))
--
2.49.0
^ permalink raw reply related [flat|nested] 43+ messages in thread* [PATCH RFT 12/14] drm/msm/adreno: Switch to the common UBWC config struct
2025-05-08 18:12 [RFT PATCH 00/14] Add a single source of truth for UBWC configuration data Konrad Dybcio
` (10 preceding siblings ...)
2025-05-08 18:12 ` [PATCH RFT 11/14] drm/msm/a6xx: Simplify min_acc_len calculation Konrad Dybcio
@ 2025-05-08 18:12 ` Konrad Dybcio
2025-05-08 18:12 ` [PATCH RFT 13/14] drm/msm/a6xx: Drop cfg->ubwc_swizzle override Konrad Dybcio
2025-05-08 18:12 ` [PATCH RFT 14/14] drm/msm/a5xx: Use UBWC data from the common UBWC config struct Konrad Dybcio
13 siblings, 0 replies; 43+ messages in thread
From: Konrad Dybcio @ 2025-05-08 18:12 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Clark, Abhinav Kumar,
Dmitry Baryshkov, Akhil P Oommen, Sean Paul, David Airlie,
Simona Vetter
Cc: Marijn Suijten, linux-kernel, linux-arm-msm, dri-devel, freedreno,
Konrad Dybcio
From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Now that Adreno specifics are out of the way, use the common config
(but leave the HBB hardcoding in place until that is wired up on the
other side).
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 10 ++++----
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 41 ++++++++++++++++++---------------
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 12 ++++------
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 40 +-------------------------------
4 files changed, 34 insertions(+), 69 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
index 67331a7ee750c0d9eeeead9440e5d08b1a09c878..1344d461c16dfa942b0b65d747eadca507116806 100644
--- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
@@ -833,7 +833,7 @@ static int a5xx_hw_init(struct msm_gpu *gpu)
gpu_write(gpu, REG_A5XX_RBBM_AHB_CNTL2, 0x0000003F);
- hbb = adreno_gpu->ubwc_config.highest_bank_bit;
+ hbb = adreno_gpu->ubwc_config->highest_bank_bit;
gpu_write(gpu, REG_A5XX_TPL1_MODE_CNTL, hbb << 7);
gpu_write(gpu, REG_A5XX_RB_MODE_CNTL, hbb << 1);
@@ -1791,13 +1791,13 @@ struct msm_gpu *a5xx_gpu_init(struct drm_device *dev)
/* Set the highest bank bit */
if (adreno_is_a540(adreno_gpu) || adreno_is_a530(adreno_gpu))
- adreno_gpu->ubwc_config.highest_bank_bit = 2;
+ adreno_gpu->ubwc_config->highest_bank_bit = 2;
else
- adreno_gpu->ubwc_config.highest_bank_bit = 1;
+ adreno_gpu->ubwc_config->highest_bank_bit = 1;
/* a5xx only supports UBWC 1.0, these are not configurable */
- adreno_gpu->ubwc_config.macrotile_mode = 0;
- adreno_gpu->ubwc_config.ubwc_swizzle = 0x7;
+ adreno_gpu->ubwc_config->macrotile_mode = 0;
+ adreno_gpu->ubwc_config->ubwc_swizzle = 0x7;
adreno_gpu->uche_trap_base = 0x0001ffffffff0000ull;
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index d297890dfba60c6110fb8571e1f46729390302ed..28ba0cddd7d222b0a287c7c3a111e123a73b1d39 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -587,34 +587,39 @@ static void a6xx_set_cp_protect(struct msm_gpu *gpu)
static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
{
+ const struct qcom_ubwc_cfg_data *common_cfg;
+ struct qcom_ubwc_cfg_data *cfg = gpu->ubwc_config;
+
/* Inherit the common config and make some necessary fixups */
- gpu->common_ubwc_cfg = qcom_ubwc_config_get_data();
- if (IS_ERR(gpu->common_ubwc_cfg))
+ common_cfg = qcom_ubwc_config_get_data();
+ if (IS_ERR(common_cfg))
return -EINVAL;
- gpu->ubwc_config.ubwc_swizzle = 0x6;
- gpu->ubwc_config.highest_bank_bit = 2;
+ *cfg = *common_cfg;
+
+ cfg->ubwc_swizzle = 0x6;
+ cfg->highest_bank_bit = 2;
if (adreno_is_a610(gpu)) {
- gpu->ubwc_config.highest_bank_bit = 0;
- gpu->ubwc_config.ubwc_swizzle = 0x7;
+ cfg->highest_bank_bit = 0;
+ cfg->ubwc_swizzle = 0x7;
}
if (adreno_is_a618(gpu))
- gpu->ubwc_config.highest_bank_bit = 1;
+ cfg->highest_bank_bit = 1;
if (adreno_is_a619(gpu))
/* TODO: Should be 14 but causes corruption at e.g. 1920x1200 on DP */
- gpu->ubwc_config.highest_bank_bit = 0;
+ cfg->highest_bank_bit = 0;
if (adreno_is_a619_holi(gpu))
- gpu->ubwc_config.highest_bank_bit = 0;
+ cfg->highest_bank_bit = 0;
if (adreno_is_a621(gpu))
- gpu->ubwc_config.highest_bank_bit = 0;
+ cfg->highest_bank_bit = 0;
if (adreno_is_a623(gpu))
- gpu->ubwc_config.highest_bank_bit = 3;
+ cfg->highest_bank_bit = 3;
if (adreno_is_a650(gpu) ||
adreno_is_a660(gpu) ||
@@ -622,19 +627,19 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
adreno_is_a730(gpu) ||
adreno_is_a740_family(gpu)) {
/* TODO: get ddr type from bootloader and use 2 for LPDDR4 */
- gpu->ubwc_config.highest_bank_bit = 3;
+ cfg->highest_bank_bit = 3;
}
if (adreno_is_a663(gpu)) {
- gpu->ubwc_config.highest_bank_bit = 0;
- gpu->ubwc_config.ubwc_swizzle = 0x4;
+ cfg->highest_bank_bit = 0;
+ cfg->ubwc_swizzle = 0x4;
}
if (adreno_is_7c3(gpu))
- gpu->ubwc_config.highest_bank_bit = 1;
+ cfg->highest_bank_bit = 1;
if (adreno_is_a702(gpu))
- gpu->ubwc_config.highest_bank_bit = 1;
+ cfg->highest_bank_bit = 1;
return 0;
}
@@ -644,12 +649,12 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
u8 uavflagprd_inv = adreno_is_a650_family(adreno_gpu) || adreno_is_a7xx(adreno_gpu) ? 2 : 0;
bool min_acc_len_64b = adreno_is_a610(adreno_gpu) || adreno_is_a702(adreno_gpu);
- const struct qcom_ubwc_cfg_data *cfg = adreno_gpu->common_ubwc_cfg;
+ const struct qcom_ubwc_cfg_data *cfg = adreno_gpu->ubwc_config;
bool rgb565_predicator = cfg->ubwc_enc_version >= UBWC_4_0;
u32 level2_swizzling_dis = !(cfg->ubwc_swizzle & BIT(1));
- u32 hbb = adreno_gpu->ubwc_config.highest_bank_bit;
bool ubwc_mode = cfg->ubwc_enc_version == UBWC_1_0;
bool amsbc = cfg->ubwc_enc_version >= UBWC_3_0;
+ u32 hbb = cfg->highest_bank_bit;
u32 hbb_hi = hbb >> 2;
u32 hbb_lo = hbb & 3;
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
index b7f7eb8dcb272394dce8ed1e68310a394c1734a9..77f1e29df47e1413e35c688f24503cb4d457e304 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
@@ -388,16 +388,16 @@ int adreno_get_param(struct msm_gpu *gpu, struct msm_file_private *ctx,
*value = ctx->aspace->va_size;
return 0;
case MSM_PARAM_HIGHEST_BANK_BIT:
- *value = adreno_gpu->ubwc_config.highest_bank_bit;
+ *value = adreno_gpu->ubwc_config->highest_bank_bit;
return 0;
case MSM_PARAM_RAYTRACING:
*value = adreno_gpu->has_ray_tracing;
return 0;
case MSM_PARAM_UBWC_SWIZZLE:
- *value = adreno_gpu->ubwc_config.ubwc_swizzle;
+ *value = adreno_gpu->ubwc_config->ubwc_swizzle;
return 0;
case MSM_PARAM_MACROTILE_MODE:
- *value = adreno_gpu->ubwc_config.macrotile_mode;
+ *value = adreno_gpu->ubwc_config->macrotile_mode;
return 0;
case MSM_PARAM_UCHE_TRAP_BASE:
*value = adreno_gpu->uche_trap_base;
@@ -1149,10 +1149,8 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
speedbin = 0xffff;
adreno_gpu->speedbin = (uint16_t) (0xffff & speedbin);
- adreno_gpu->common_ubwc_cfg = devm_kzalloc(dev,
- sizeof(*adreno_gpu->common_ubwc_cfg),
- GFP_KERNEL);
- if (!adreno_gpu->common_ubwc_cfg)
+ adreno_gpu->ubwc_config = devm_kzalloc(dev, sizeof(*adreno_gpu->ubwc_config), GFP_KERNEL);
+ if (!adreno_gpu->ubwc_config)
return -ENOMEM;
gpu_name = devm_kasprintf(dev, GFP_KERNEL, "%"ADRENO_CHIPID_FMT,
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
index 06be95d3efaee94e4107a484ad3132e0a6a9ea46..5d27666c46e29da5177d6fc900effc209c2a5507 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
@@ -207,45 +207,7 @@ struct adreno_gpu {
/* firmware: */
const struct firmware *fw[ADRENO_FW_MAX];
- struct {
- /**
- * @rgb565_predicator: Unknown, introduced with A650 family,
- * related to UBWC mode/ver 4
- */
- u32 rgb565_predicator;
- /** @uavflagprd_inv: Unknown, introduced with A650 family */
- u32 uavflagprd_inv;
- /** @min_acc_len: Whether the minimum access length is 64 bits */
- u32 min_acc_len;
- /**
- * @ubwc_swizzle: Whether to enable level 1, 2 & 3 bank swizzling.
- *
- * UBWC 1.0 always enables all three levels.
- * UBWC 2.0 removes level 1 bank swizzling, leaving levels 2 & 3.
- * UBWC 4.0 adds the optional ability to disable levels 2 & 3.
- *
- * This is a bitmask where BIT(0) enables level 1, BIT(1)
- * controls level 2, and BIT(2) enables level 3.
- */
- u32 ubwc_swizzle;
- /**
- * @highest_bank_bit: Highest Bank Bit
- *
- * The Highest Bank Bit value represents the bit of the highest
- * DDR bank. This should ideally use DRAM type detection.
- */
- u32 highest_bank_bit;
- u32 amsbc;
- /**
- * @macrotile_mode: Macrotile Mode
- *
- * Whether to use 4-channel macrotiling mode or the newer
- * 8-channel macrotiling mode introduced in UBWC 3.1. 0 is
- * 4-channel and 1 is 8-channel.
- */
- u32 macrotile_mode;
- } ubwc_config;
- const struct qcom_ubwc_cfg_data *common_ubwc_cfg;
+ struct qcom_ubwc_cfg_data *ubwc_config;
/*
* Register offsets are different between some GPUs.
--
2.49.0
^ permalink raw reply related [flat|nested] 43+ messages in thread* [PATCH RFT 13/14] drm/msm/a6xx: Drop cfg->ubwc_swizzle override
2025-05-08 18:12 [RFT PATCH 00/14] Add a single source of truth for UBWC configuration data Konrad Dybcio
` (11 preceding siblings ...)
2025-05-08 18:12 ` [PATCH RFT 12/14] drm/msm/adreno: Switch to the common UBWC config struct Konrad Dybcio
@ 2025-05-08 18:12 ` Konrad Dybcio
2025-05-08 19:26 ` Connor Abbott
2025-05-08 18:12 ` [PATCH RFT 14/14] drm/msm/a5xx: Use UBWC data from the common UBWC config struct Konrad Dybcio
13 siblings, 1 reply; 43+ messages in thread
From: Konrad Dybcio @ 2025-05-08 18:12 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Clark, Abhinav Kumar,
Dmitry Baryshkov, Akhil P Oommen, Sean Paul, David Airlie,
Simona Vetter
Cc: Marijn Suijten, linux-kernel, linux-arm-msm, dri-devel, freedreno,
Konrad Dybcio
From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
On A663 (SA8775P) the value matches exactly.
On A610, the value matches on SM6115, but is different on SM6125. That
turns out not to be a problem, as the bits that differ aren't even
interpreted.
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 9 ++-------
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 28ba0cddd7d222b0a287c7c3a111e123a73b1d39..d96f8cec854a36a77896d39b88c320c29c787edd 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -597,13 +597,10 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
*cfg = *common_cfg;
- cfg->ubwc_swizzle = 0x6;
cfg->highest_bank_bit = 2;
- if (adreno_is_a610(gpu)) {
+ if (adreno_is_a610(gpu))
cfg->highest_bank_bit = 0;
- cfg->ubwc_swizzle = 0x7;
- }
if (adreno_is_a618(gpu))
cfg->highest_bank_bit = 1;
@@ -630,10 +627,8 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
cfg->highest_bank_bit = 3;
}
- if (adreno_is_a663(gpu)) {
+ if (adreno_is_a663(gpu))
cfg->highest_bank_bit = 0;
- cfg->ubwc_swizzle = 0x4;
- }
if (adreno_is_7c3(gpu))
cfg->highest_bank_bit = 1;
--
2.49.0
^ permalink raw reply related [flat|nested] 43+ messages in thread* Re: [PATCH RFT 13/14] drm/msm/a6xx: Drop cfg->ubwc_swizzle override
2025-05-08 18:12 ` [PATCH RFT 13/14] drm/msm/a6xx: Drop cfg->ubwc_swizzle override Konrad Dybcio
@ 2025-05-08 19:26 ` Connor Abbott
2025-05-09 13:17 ` Konrad Dybcio
0 siblings, 1 reply; 43+ messages in thread
From: Connor Abbott @ 2025-05-08 19:26 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Bjorn Andersson, Rob Clark, Abhinav Kumar, Dmitry Baryshkov,
Akhil P Oommen, Sean Paul, David Airlie, Simona Vetter,
Marijn Suijten, linux-kernel, linux-arm-msm, dri-devel, freedreno,
Konrad Dybcio
On Thu, May 8, 2025 at 2:14 PM Konrad Dybcio <konradybcio@kernel.org> wrote:
>
> From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>
> On A663 (SA8775P) the value matches exactly.
>
> On A610, the value matches on SM6115, but is different on SM6125. That
> turns out not to be a problem, as the bits that differ aren't even
> interpreted.
This is definitely going to break userspace, because the kernel
doesn't expose the UBWC version, instead exposing just the swizzle and
userspace expects that it sets the right value for older UBWC versions
before it became configurable (0x7 for UBWC 1.0 and 0x6 for 2.0-3.0).
It looks like the data for SM6125 is just wrong.
Connor
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 9 ++-------
> 1 file changed, 2 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> index 28ba0cddd7d222b0a287c7c3a111e123a73b1d39..d96f8cec854a36a77896d39b88c320c29c787edd 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> @@ -597,13 +597,10 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
>
> *cfg = *common_cfg;
>
> - cfg->ubwc_swizzle = 0x6;
> cfg->highest_bank_bit = 2;
>
> - if (adreno_is_a610(gpu)) {
> + if (adreno_is_a610(gpu))
> cfg->highest_bank_bit = 0;
> - cfg->ubwc_swizzle = 0x7;
> - }
>
> if (adreno_is_a618(gpu))
> cfg->highest_bank_bit = 1;
> @@ -630,10 +627,8 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
> cfg->highest_bank_bit = 3;
> }
>
> - if (adreno_is_a663(gpu)) {
> + if (adreno_is_a663(gpu))
> cfg->highest_bank_bit = 0;
> - cfg->ubwc_swizzle = 0x4;
> - }
>
> if (adreno_is_7c3(gpu))
> cfg->highest_bank_bit = 1;
>
> --
> 2.49.0
>
^ permalink raw reply [flat|nested] 43+ messages in thread* Re: [PATCH RFT 13/14] drm/msm/a6xx: Drop cfg->ubwc_swizzle override
2025-05-08 19:26 ` Connor Abbott
@ 2025-05-09 13:17 ` Konrad Dybcio
2025-05-09 13:37 ` Konrad Dybcio
0 siblings, 1 reply; 43+ messages in thread
From: Konrad Dybcio @ 2025-05-09 13:17 UTC (permalink / raw)
To: Connor Abbott, Konrad Dybcio
Cc: Bjorn Andersson, Rob Clark, Abhinav Kumar, Dmitry Baryshkov,
Akhil P Oommen, Sean Paul, David Airlie, Simona Vetter,
Marijn Suijten, linux-kernel, linux-arm-msm, dri-devel, freedreno
On 5/8/25 9:26 PM, Connor Abbott wrote:
> On Thu, May 8, 2025 at 2:14 PM Konrad Dybcio <konradybcio@kernel.org> wrote:
>>
>> From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>>
>> On A663 (SA8775P) the value matches exactly.
>>
>> On A610, the value matches on SM6115, but is different on SM6125. That
>> turns out not to be a problem, as the bits that differ aren't even
>> interpreted.
>
> This is definitely going to break userspace, because the kernel
> doesn't expose the UBWC version, instead exposing just the swizzle and
> userspace expects that it sets the right value for older UBWC versions
> before it became configurable (0x7 for UBWC 1.0 and 0x6 for 2.0-3.0).
> It looks like the data for SM6125 is just wrong.
Oh that's sad.. I'll drop this commit
Konrad
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH RFT 13/14] drm/msm/a6xx: Drop cfg->ubwc_swizzle override
2025-05-09 13:17 ` Konrad Dybcio
@ 2025-05-09 13:37 ` Konrad Dybcio
2025-05-09 14:48 ` Connor Abbott
0 siblings, 1 reply; 43+ messages in thread
From: Konrad Dybcio @ 2025-05-09 13:37 UTC (permalink / raw)
To: Konrad Dybcio, Connor Abbott, Konrad Dybcio
Cc: Bjorn Andersson, Rob Clark, Abhinav Kumar, Dmitry Baryshkov,
Akhil P Oommen, Sean Paul, David Airlie, Simona Vetter,
Marijn Suijten, linux-kernel, linux-arm-msm, dri-devel, freedreno
On 5/9/25 3:17 PM, Konrad Dybcio wrote:
> On 5/8/25 9:26 PM, Connor Abbott wrote:
>> On Thu, May 8, 2025 at 2:14 PM Konrad Dybcio <konradybcio@kernel.org> wrote:
>>>
>>> From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>>>
>>> On A663 (SA8775P) the value matches exactly.
>>>
>>> On A610, the value matches on SM6115, but is different on SM6125. That
>>> turns out not to be a problem, as the bits that differ aren't even
>>> interpreted.
>>
>> This is definitely going to break userspace, because the kernel
>> doesn't expose the UBWC version, instead exposing just the swizzle and
>> userspace expects that it sets the right value for older UBWC versions
>> before it became configurable (0x7 for UBWC 1.0 and 0x6 for 2.0-3.0).
>> It looks like the data for SM6125 is just wrong.
>
> Oh that's sad.. I'll drop this commit
Wait uh, we have this data in the common config.. why would it break
userspace?
Konrad
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH RFT 13/14] drm/msm/a6xx: Drop cfg->ubwc_swizzle override
2025-05-09 13:37 ` Konrad Dybcio
@ 2025-05-09 14:48 ` Connor Abbott
2025-05-09 15:52 ` Konrad Dybcio
0 siblings, 1 reply; 43+ messages in thread
From: Connor Abbott @ 2025-05-09 14:48 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Konrad Dybcio, Bjorn Andersson, Rob Clark, Abhinav Kumar,
Dmitry Baryshkov, Akhil P Oommen, Sean Paul, David Airlie,
Simona Vetter, Marijn Suijten, linux-kernel, linux-arm-msm,
dri-devel, freedreno
On Fri, May 9, 2025 at 9:37 AM Konrad Dybcio
<konrad.dybcio@oss.qualcomm.com> wrote:
>
> On 5/9/25 3:17 PM, Konrad Dybcio wrote:
> > On 5/8/25 9:26 PM, Connor Abbott wrote:
> >> On Thu, May 8, 2025 at 2:14 PM Konrad Dybcio <konradybcio@kernel.org> wrote:
> >>>
> >>> From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> >>>
> >>> On A663 (SA8775P) the value matches exactly.
> >>>
> >>> On A610, the value matches on SM6115, but is different on SM6125. That
> >>> turns out not to be a problem, as the bits that differ aren't even
> >>> interpreted.
> >>
> >> This is definitely going to break userspace, because the kernel
> >> doesn't expose the UBWC version, instead exposing just the swizzle and
> >> userspace expects that it sets the right value for older UBWC versions
> >> before it became configurable (0x7 for UBWC 1.0 and 0x6 for 2.0-3.0).
> >> It looks like the data for SM6125 is just wrong.
> >
> > Oh that's sad.. I'll drop this commit
>
> Wait uh, we have this data in the common config.. why would it break
> userspace?
>
> Konrad
As you said in the commit message SM6125 has ubwc_swizzle = 1 which
seems wrong to me (it should be 7), it just didn't matter before that
it was wrong. You should probably just fix that.
Connor
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH RFT 13/14] drm/msm/a6xx: Drop cfg->ubwc_swizzle override
2025-05-09 14:48 ` Connor Abbott
@ 2025-05-09 15:52 ` Konrad Dybcio
0 siblings, 0 replies; 43+ messages in thread
From: Konrad Dybcio @ 2025-05-09 15:52 UTC (permalink / raw)
To: Connor Abbott
Cc: Konrad Dybcio, Bjorn Andersson, Rob Clark, Abhinav Kumar,
Dmitry Baryshkov, Akhil P Oommen, Sean Paul, David Airlie,
Simona Vetter, Marijn Suijten, linux-kernel, linux-arm-msm,
dri-devel, freedreno
On 5/9/25 4:48 PM, Connor Abbott wrote:
> On Fri, May 9, 2025 at 9:37 AM Konrad Dybcio
> <konrad.dybcio@oss.qualcomm.com> wrote:
>>
>> On 5/9/25 3:17 PM, Konrad Dybcio wrote:
>>> On 5/8/25 9:26 PM, Connor Abbott wrote:
>>>> On Thu, May 8, 2025 at 2:14 PM Konrad Dybcio <konradybcio@kernel.org> wrote:
>>>>>
>>>>> From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>>>>>
>>>>> On A663 (SA8775P) the value matches exactly.
>>>>>
>>>>> On A610, the value matches on SM6115, but is different on SM6125. That
>>>>> turns out not to be a problem, as the bits that differ aren't even
>>>>> interpreted.
>>>>
>>>> This is definitely going to break userspace, because the kernel
>>>> doesn't expose the UBWC version, instead exposing just the swizzle and
>>>> userspace expects that it sets the right value for older UBWC versions
>>>> before it became configurable (0x7 for UBWC 1.0 and 0x6 for 2.0-3.0).
>>>> It looks like the data for SM6125 is just wrong.
>>>
>>> Oh that's sad.. I'll drop this commit
>>
>> Wait uh, we have this data in the common config.. why would it break
>> userspace?
>>
>> Konrad
>
> As you said in the commit message SM6125 has ubwc_swizzle = 1 which
> seems wrong to me (it should be 7), it just didn't matter before that
> it was wrong. You should probably just fix that.
Oh so you meant that the 6125's value would break userspace - gotcha
Konrad
^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH RFT 14/14] drm/msm/a5xx: Use UBWC data from the common UBWC config struct
2025-05-08 18:12 [RFT PATCH 00/14] Add a single source of truth for UBWC configuration data Konrad Dybcio
` (12 preceding siblings ...)
2025-05-08 18:12 ` [PATCH RFT 13/14] drm/msm/a6xx: Drop cfg->ubwc_swizzle override Konrad Dybcio
@ 2025-05-08 18:12 ` Konrad Dybcio
13 siblings, 0 replies; 43+ messages in thread
From: Konrad Dybcio @ 2025-05-08 18:12 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Clark, Abhinav Kumar,
Dmitry Baryshkov, Akhil P Oommen, Sean Paul, David Airlie,
Simona Vetter
Cc: Marijn Suijten, linux-kernel, linux-arm-msm, dri-devel, freedreno,
Konrad Dybcio
From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Make use of the SSOT config database, this time including the HBB
which doesn't seem to change between configurations.
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 14 ++++++--------
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
index 1344d461c16dfa942b0b65d747eadca507116806..691393e958cf164b69e7fe1a9df313f813473a35 100644
--- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
@@ -1753,6 +1753,7 @@ struct msm_gpu *a5xx_gpu_init(struct drm_device *dev)
struct msm_drm_private *priv = dev->dev_private;
struct platform_device *pdev = priv->gpu_pdev;
struct adreno_platform_config *config = pdev->dev.platform_data;
+ const struct qcom_ubwc_cfg_data *common_cfg;
struct a5xx_gpu *a5xx_gpu = NULL;
struct adreno_gpu *adreno_gpu;
struct msm_gpu *gpu;
@@ -1789,15 +1790,12 @@ struct msm_gpu *a5xx_gpu_init(struct drm_device *dev)
/* Set up the preemption specific bits and pieces for each ringbuffer */
a5xx_preempt_init(gpu);
- /* Set the highest bank bit */
- if (adreno_is_a540(adreno_gpu) || adreno_is_a530(adreno_gpu))
- adreno_gpu->ubwc_config->highest_bank_bit = 2;
- else
- adreno_gpu->ubwc_config->highest_bank_bit = 1;
+ /* Inherit the common config and make some necessary fixups */
+ common_cfg = qcom_ubwc_config_get_data();
+ if (IS_ERR(common_cfg))
+ return ERR_PTR(-EINVAL);
- /* a5xx only supports UBWC 1.0, these are not configurable */
- adreno_gpu->ubwc_config->macrotile_mode = 0;
- adreno_gpu->ubwc_config->ubwc_swizzle = 0x7;
+ *adreno_gpu->ubwc_config = *common_cfg;
adreno_gpu->uche_trap_base = 0x0001ffffffff0000ull;
--
2.49.0
^ permalink raw reply related [flat|nested] 43+ messages in thread