[PATCH v2] mailbox: tegra-hsp: Clear mailbox before using message

[PATCH v2] mailbox: tegra-hsp: Clear mailbox before using message

[Kartik Rajput]

From: Pekka Pessi <ppessi@nvidia.com>

Some clients depend on mailbox being empty before processing the
message. On RT kernel, the thread processing the message may be on
different CPU or running with higher priority than the interrupt
handler thread and they may act on the message before mailbox is
emptied.

Fixes: 8f585d14030d ("mailbox: tegra-hsp: Add tegra_hsp_sm_ops")
Fixes: 74c20dd0f892 ("mailbox: tegra-hsp: Add 128-bit shared mailbox support")
Cc: stable@vger.kernel.org
Signed-off-by: Pekka Pessi <ppessi@nvidia.com>
Signed-off-by: Kartik Rajput <kkartik@nvidia.com>
---
v1 -> v2:
	* Added "Fixes:" tag in the commit message.
	* Made similar change for 128-bit shared mailboxes.
---
 drivers/mailbox/tegra-hsp.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/mailbox/tegra-hsp.c b/drivers/mailbox/tegra-hsp.c
index 8d5e2d7dc03b..c1981f091bd1 100644
--- a/drivers/mailbox/tegra-hsp.c
+++ b/drivers/mailbox/tegra-hsp.c
@@ -388,7 +388,6 @@ static void tegra_hsp_sm_recv32(struct tegra_hsp_channel *channel)
 	value = tegra_hsp_channel_readl(channel, HSP_SM_SHRD_MBOX);
 	value &= ~HSP_SM_SHRD_MBOX_FULL;
 	msg = (void *)(unsigned long)value;
-	mbox_chan_received_data(channel->chan, msg);
 
 	/*
 	 * Need to clear all bits here since some producers, such as TCU, depend
@@ -398,6 +397,8 @@ static void tegra_hsp_sm_recv32(struct tegra_hsp_channel *channel)
 	 * explicitly, so we have to make sure we cover all possible cases.
 	 */
 	tegra_hsp_channel_writel(channel, 0x0, HSP_SM_SHRD_MBOX);
+
+	mbox_chan_received_data(channel->chan, msg);
 }
 
 static const struct tegra_hsp_sm_ops tegra_hsp_sm_32bit_ops = {
@@ -433,7 +434,6 @@ static void tegra_hsp_sm_recv128(struct tegra_hsp_channel *channel)
 	value[3] = tegra_hsp_channel_readl(channel, HSP_SHRD_MBOX_TYPE1_DATA3);
 
 	msg = (void *)(unsigned long)value;
-	mbox_chan_received_data(channel->chan, msg);
 
 	/*
 	 * Clear data registers and tag.
@@ -443,6 +443,8 @@ static void tegra_hsp_sm_recv128(struct tegra_hsp_channel *channel)
 	tegra_hsp_channel_writel(channel, 0x0, HSP_SHRD_MBOX_TYPE1_DATA2);
 	tegra_hsp_channel_writel(channel, 0x0, HSP_SHRD_MBOX_TYPE1_DATA3);
 	tegra_hsp_channel_writel(channel, 0x0, HSP_SHRD_MBOX_TYPE1_TAG);
+
+	mbox_chan_received_data(channel->chan, msg);
 }
 
 static const struct tegra_hsp_sm_ops tegra_hsp_sm_128bit_ops = {
-- 
2.34.1

Re: [PATCH v2] mailbox: tegra-hsp: Clear mailbox before using message

[Thierry Reding]

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On Thu, Nov 28, 2024 at 02:29:30PM +0530, Kartik Rajput wrote:
> From: Pekka Pessi <ppessi@nvidia.com>
> 
> Some clients depend on mailbox being empty before processing the
> message. On RT kernel, the thread processing the message may be on
> different CPU or running with higher priority than the interrupt
> handler thread and they may act on the message before mailbox is
> emptied.
> 
> Fixes: 8f585d14030d ("mailbox: tegra-hsp: Add tegra_hsp_sm_ops")
> Fixes: 74c20dd0f892 ("mailbox: tegra-hsp: Add 128-bit shared mailbox support")
> Cc: stable@vger.kernel.org
> Signed-off-by: Pekka Pessi <ppessi@nvidia.com>
> Signed-off-by: Kartik Rajput <kkartik@nvidia.com>
> ---
> v1 -> v2:
> 	* Added "Fixes:" tag in the commit message.
> 	* Made similar change for 128-bit shared mailboxes.
> ---
>  drivers/mailbox/tegra-hsp.c | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)

Do we know what exactly "some clients" means? I know that TCU uses this
shared mailbox and sometimes it does go into a weird state where it can
loose characters, so I wonder if that's one case that would be fixed by
this.

Not strictly a requirement, but it would be good if we can give a good
description of a case where this helps.

Thierry

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Re: [PATCH v2] mailbox: tegra-hsp: Clear mailbox before using message

[Kartik Rajput]

On Thu, 2024-11-28 at 11:22 +0100, Thierry Reding wrote:
> On Thu, Nov 28, 2024 at 02:29:30PM +0530, Kartik Rajput wrote:
> > From: Pekka Pessi <ppessi@nvidia.com>
> > 
> > Some clients depend on mailbox being empty before processing the
> > message. On RT kernel, the thread processing the message may be on
> > different CPU or running with higher priority than the interrupt
> > handler thread and they may act on the message before mailbox is
> > emptied.
> > 
> > Fixes: 8f585d14030d ("mailbox: tegra-hsp: Add tegra_hsp_sm_ops")
> > Fixes: 74c20dd0f892 ("mailbox: tegra-hsp: Add 128-bit shared
> > mailbox support")
> > Cc: stable@vger.kernel.org
> > Signed-off-by: Pekka Pessi <ppessi@nvidia.com>
> > Signed-off-by: Kartik Rajput <kkartik@nvidia.com>
> > ---
> > v1 -> v2:
> >         * Added "Fixes:" tag in the commit message.
> >         * Made similar change for 128-bit shared mailboxes.
> > ---
> >  drivers/mailbox/tegra-hsp.c | 6 ++++--
> >  1 file changed, 4 insertions(+), 2 deletions(-)
> 
> Do we know what exactly "some clients" means? I know that TCU uses
> this
> shared mailbox and sometimes it does go into a weird state where it
> can
> loose characters, so I wonder if that's one case that would be fixed
> by
> this.
> 
> Not strictly a requirement, but it would be good if we can give a
> good
> description of a case where this helps.
> 
> Thierry

Hi Thierry,

This patch fixes an issue with the Tegra RCE driver (which is available
as an external module), where it may process an IVC message before the
mailbox data register is cleared, resulting in a loss of IVC
notification.

I have posted v3 of this patch with an updated commit description.

Thanks & Regards,
Kartik