From: Paul Walmsley <pjw@kernel.org>
To: Himanshu Chauhan <himanshu.chauhan@oss.qualcomm.com>
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu,
alex@ghiti.fr, shuah@kernel.org
Subject: Re: [PATCH v2 0/2] riscv: Introduce support for hardware break/watchpoints
Date: Thu, 12 Feb 2026 17:34:00 -0700 (MST) [thread overview]
Message-ID: <e0e40e14-e4f4-c3b3-4ebd-200052b529aa@kernel.org> (raw)
In-Reply-To: <20260106082021.2680658-1-himanshu.chauhan@oss.qualcomm.com>
Hi Himanshu,
On Tue, 6 Jan 2026, Himanshu Chauhan wrote:
> This patchset adds support of hardware breakpoints and watchpoints in RISC-V
> architecture. The framework is built on top of perf subsystem and SBI debug
> trigger extension.
>
> Currently following features are not supported and are in works:
> - Ptrace support
> - Single stepping
> - Virtualization of debug triggers
>
> The SBI debug trigger extension proposal can be found in Chapter-19 of SBI specification:
> https://github.com/riscv-non-isa/riscv-sbi-doc/releases/download/v3.0/riscv-sbi.pdf
>
> The Sdtrig ISA is part of RISC-V debug specification which can be found at:
> https://github.com/riscv/riscv-debug-spec
Can you fix the checkpatch issues with this series? Please use --strict.
In the meantime, I'll add it as an experimental branch, until those get
sorted out.
- Paul
next prev parent reply other threads:[~2026-02-13 0:34 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-01-06 8:20 [PATCH v2 0/2] riscv: Introduce support for hardware break/watchpoints Himanshu Chauhan
2026-01-06 8:20 ` [PATCH v2 1/2] " Himanshu Chauhan
2026-01-06 8:20 ` [PATCH v2 2/2] riscv: Add breakpoint and watchpoint test for riscv Himanshu Chauhan
2026-02-13 0:34 ` Paul Walmsley [this message]
2026-02-17 8:43 ` [PATCH v2 0/2] riscv: Introduce support for hardware break/watchpoints Himanshu Chauhan
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