* Re: [PATCH] clk: qcom: dispcc-sm8750: Drop incorrect CLK_SET_RATE_PARENT on byte intf parent
2025-01-29 15:45 [PATCH] clk: qcom: dispcc-sm8750: Drop incorrect CLK_SET_RATE_PARENT on byte intf parent Krzysztof Kozlowski
@ 2025-01-29 15:55 ` neil.armstrong
2025-01-29 16:25 ` Dmitry Baryshkov
` (3 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: neil.armstrong @ 2025-01-29 15:55 UTC (permalink / raw)
To: Krzysztof Kozlowski, Bjorn Andersson, Michael Turquette,
Stephen Boyd, linux-arm-msm, linux-clk, linux-kernel
On 29/01/2025 16:45, Krzysztof Kozlowski wrote:
> The parent of disp_cc_mdss_byte0_intf_clk clock should not propagate up
> the rates, because this messes up entire clock hierarchy when setting
> clock rates in MSM DSI driver.
>
> The dsi_link_clk_set_rate_6g() first sets entire clock hierarchy rates
> via dev_pm_opp_set_rate() on byte clock and then sets individual clock
> rates, like pixel and byte_intf clocks, to proper frequencies. Having
> CLK_SET_RATE_PARENT caused that entire tree was re-calced and the byte
> clock received halved frequency. Drop CLK_SET_RATE_PARENT to fix this
> and align with SM8550 and SM8650.
>
> Fixes: f1080d8dab0f ("clk: qcom: dispcc-sm8750: Add SM8750 Display clock controller")
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>
> ---
>
> Fix for v6.14-rcX.
> ---
> drivers/clk/qcom/dispcc-sm8750.c | 2 --
> 1 file changed, 2 deletions(-)
>
> diff --git a/drivers/clk/qcom/dispcc-sm8750.c b/drivers/clk/qcom/dispcc-sm8750.c
> index 0358dff91da5..e9bca179998b 100644
> --- a/drivers/clk/qcom/dispcc-sm8750.c
> +++ b/drivers/clk/qcom/dispcc-sm8750.c
> @@ -827,7 +827,6 @@ static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = {
> &disp_cc_mdss_byte0_clk_src.clkr.hw,
> },
> .num_parents = 1,
> - .flags = CLK_SET_RATE_PARENT,
> .ops = &clk_regmap_div_ops,
> },
> };
> @@ -842,7 +841,6 @@ static struct clk_regmap_div disp_cc_mdss_byte1_div_clk_src = {
> &disp_cc_mdss_byte1_clk_src.clkr.hw,
> },
> .num_parents = 1,
> - .flags = CLK_SET_RATE_PARENT,
> .ops = &clk_regmap_div_ops,
> },
> };
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH] clk: qcom: dispcc-sm8750: Drop incorrect CLK_SET_RATE_PARENT on byte intf parent
2025-01-29 15:45 [PATCH] clk: qcom: dispcc-sm8750: Drop incorrect CLK_SET_RATE_PARENT on byte intf parent Krzysztof Kozlowski
2025-01-29 15:55 ` neil.armstrong
@ 2025-01-29 16:25 ` Dmitry Baryshkov
2025-01-29 18:43 ` Abhinav Kumar
` (2 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Dmitry Baryshkov @ 2025-01-29 16:25 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Bjorn Andersson, Michael Turquette, Stephen Boyd, linux-arm-msm,
linux-clk, linux-kernel
On Wed, Jan 29, 2025 at 04:45:19PM +0100, Krzysztof Kozlowski wrote:
> The parent of disp_cc_mdss_byte0_intf_clk clock should not propagate up
> the rates, because this messes up entire clock hierarchy when setting
> clock rates in MSM DSI driver.
>
> The dsi_link_clk_set_rate_6g() first sets entire clock hierarchy rates
> via dev_pm_opp_set_rate() on byte clock and then sets individual clock
> rates, like pixel and byte_intf clocks, to proper frequencies. Having
> CLK_SET_RATE_PARENT caused that entire tree was re-calced and the byte
> clock received halved frequency. Drop CLK_SET_RATE_PARENT to fix this
> and align with SM8550 and SM8650.
>
> Fixes: f1080d8dab0f ("clk: qcom: dispcc-sm8750: Add SM8750 Display clock controller")
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>
> ---
>
> Fix for v6.14-rcX.
> ---
> drivers/clk/qcom/dispcc-sm8750.c | 2 --
> 1 file changed, 2 deletions(-)
>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH] clk: qcom: dispcc-sm8750: Drop incorrect CLK_SET_RATE_PARENT on byte intf parent
2025-01-29 15:45 [PATCH] clk: qcom: dispcc-sm8750: Drop incorrect CLK_SET_RATE_PARENT on byte intf parent Krzysztof Kozlowski
2025-01-29 15:55 ` neil.armstrong
2025-01-29 16:25 ` Dmitry Baryshkov
@ 2025-01-29 18:43 ` Abhinav Kumar
2025-02-26 23:54 ` Stephen Boyd
2025-03-04 4:09 ` Bjorn Andersson
4 siblings, 0 replies; 6+ messages in thread
From: Abhinav Kumar @ 2025-01-29 18:43 UTC (permalink / raw)
To: Krzysztof Kozlowski, Bjorn Andersson, Michael Turquette,
Stephen Boyd, linux-arm-msm, linux-clk, linux-kernel
On 1/29/2025 7:45 AM, Krzysztof Kozlowski wrote:
> The parent of disp_cc_mdss_byte0_intf_clk clock should not propagate up
> the rates, because this messes up entire clock hierarchy when setting
> clock rates in MSM DSI driver.
>
> The dsi_link_clk_set_rate_6g() first sets entire clock hierarchy rates
> via dev_pm_opp_set_rate() on byte clock and then sets individual clock
> rates, like pixel and byte_intf clocks, to proper frequencies. Having
> CLK_SET_RATE_PARENT caused that entire tree was re-calced and the byte
> clock received halved frequency. Drop CLK_SET_RATE_PARENT to fix this
> and align with SM8550 and SM8650.
>
> Fixes: f1080d8dab0f ("clk: qcom: dispcc-sm8750: Add SM8750 Display clock controller")
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>
> ---
>
> Fix for v6.14-rcX.
> ---
> drivers/clk/qcom/dispcc-sm8750.c | 2 --
> 1 file changed, 2 deletions(-)
>
> diff --git a/drivers/clk/qcom/dispcc-sm8750.c b/drivers/clk/qcom/dispcc-sm8750.c
> index 0358dff91da5..e9bca179998b 100644
> --- a/drivers/clk/qcom/dispcc-sm8750.c
> +++ b/drivers/clk/qcom/dispcc-sm8750.c
> @@ -827,7 +827,6 @@ static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = {
> &disp_cc_mdss_byte0_clk_src.clkr.hw,
> },
> .num_parents = 1,
> - .flags = CLK_SET_RATE_PARENT,
> .ops = &clk_regmap_div_ops,
> },
> };
> @@ -842,7 +841,6 @@ static struct clk_regmap_div disp_cc_mdss_byte1_div_clk_src = {
> &disp_cc_mdss_byte1_clk_src.clkr.hw,
> },
> .num_parents = 1,
> - .flags = CLK_SET_RATE_PARENT,
> .ops = &clk_regmap_div_ops,
> },
> };
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH] clk: qcom: dispcc-sm8750: Drop incorrect CLK_SET_RATE_PARENT on byte intf parent
2025-01-29 15:45 [PATCH] clk: qcom: dispcc-sm8750: Drop incorrect CLK_SET_RATE_PARENT on byte intf parent Krzysztof Kozlowski
` (2 preceding siblings ...)
2025-01-29 18:43 ` Abhinav Kumar
@ 2025-02-26 23:54 ` Stephen Boyd
2025-03-04 4:09 ` Bjorn Andersson
4 siblings, 0 replies; 6+ messages in thread
From: Stephen Boyd @ 2025-02-26 23:54 UTC (permalink / raw)
To: Bjorn Andersson, Krzysztof Kozlowski, Michael Turquette,
linux-arm-msm, linux-clk, linux-kernel
Quoting Krzysztof Kozlowski (2025-01-29 07:45:19)
> The parent of disp_cc_mdss_byte0_intf_clk clock should not propagate up
> the rates, because this messes up entire clock hierarchy when setting
> clock rates in MSM DSI driver.
>
> The dsi_link_clk_set_rate_6g() first sets entire clock hierarchy rates
> via dev_pm_opp_set_rate() on byte clock and then sets individual clock
> rates, like pixel and byte_intf clocks, to proper frequencies. Having
> CLK_SET_RATE_PARENT caused that entire tree was re-calced and the byte
> clock received halved frequency. Drop CLK_SET_RATE_PARENT to fix this
> and align with SM8550 and SM8650.
>
> Fixes: f1080d8dab0f ("clk: qcom: dispcc-sm8750: Add SM8750 Display clock controller")
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>
> ---
Applied to clk-fixes
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH] clk: qcom: dispcc-sm8750: Drop incorrect CLK_SET_RATE_PARENT on byte intf parent
2025-01-29 15:45 [PATCH] clk: qcom: dispcc-sm8750: Drop incorrect CLK_SET_RATE_PARENT on byte intf parent Krzysztof Kozlowski
` (3 preceding siblings ...)
2025-02-26 23:54 ` Stephen Boyd
@ 2025-03-04 4:09 ` Bjorn Andersson
4 siblings, 0 replies; 6+ messages in thread
From: Bjorn Andersson @ 2025-03-04 4:09 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, linux-arm-msm, linux-clk,
linux-kernel, Krzysztof Kozlowski
On Wed, 29 Jan 2025 16:45:19 +0100, Krzysztof Kozlowski wrote:
> The parent of disp_cc_mdss_byte0_intf_clk clock should not propagate up
> the rates, because this messes up entire clock hierarchy when setting
> clock rates in MSM DSI driver.
>
> The dsi_link_clk_set_rate_6g() first sets entire clock hierarchy rates
> via dev_pm_opp_set_rate() on byte clock and then sets individual clock
> rates, like pixel and byte_intf clocks, to proper frequencies. Having
> CLK_SET_RATE_PARENT caused that entire tree was re-calced and the byte
> clock received halved frequency. Drop CLK_SET_RATE_PARENT to fix this
> and align with SM8550 and SM8650.
>
> [...]
Applied, thanks!
[1/1] clk: qcom: dispcc-sm8750: Drop incorrect CLK_SET_RATE_PARENT on byte intf parent
commit: 787289a1d13d50ff4ce0f496947f8817ef3fdea9
Best regards,
--
Bjorn Andersson <andersson@kernel.org>
^ permalink raw reply [flat|nested] 6+ messages in thread