* [PATCH] perf/x86/uncore: Correct the number of CHAs on SPR
@ 2023-05-08 14:02 kan.liang
2023-05-08 16:16 ` Stephane Eranian
2023-05-25 9:17 ` [tip: perf/urgent] " tip-bot2 for Kan Liang
0 siblings, 2 replies; 5+ messages in thread
From: kan.liang @ 2023-05-08 14:02 UTC (permalink / raw)
To: peterz, mingo, linux-kernel; +Cc: ak, Kan Liang, Stephane Eranian, stable
From: Kan Liang <kan.liang@linux.intel.com>
The number of CHAs from the discovery table on some SPR variants is
incorrect, because of a firmware issue. An accurate number can be read
from the MSR UNC_CBO_CONFIG.
Fixes: 949b11381f81 ("perf/x86/intel/uncore: Add Sapphire Rapids server CHA support")
Reported-by: Stephane Eranian <eranian@google.com>
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Cc: stable@vger.kernel.org
---
arch/x86/events/intel/uncore_snbep.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/uncore_snbep.c
index 7d1199554fe3..54abd93828bf 100644
--- a/arch/x86/events/intel/uncore_snbep.c
+++ b/arch/x86/events/intel/uncore_snbep.c
@@ -6138,6 +6138,7 @@ static struct intel_uncore_type spr_uncore_mdf = {
};
#define UNCORE_SPR_NUM_UNCORE_TYPES 12
+#define UNCORE_SPR_CHA 0
#define UNCORE_SPR_IIO 1
#define UNCORE_SPR_IMC 6
#define UNCORE_SPR_UPI 8
@@ -6448,12 +6449,22 @@ static int uncore_type_max_boxes(struct intel_uncore_type **types,
return max + 1;
}
+#define SPR_MSR_UNC_CBO_CONFIG 0x2FFE
+
void spr_uncore_cpu_init(void)
{
+ struct intel_uncore_type *type;
+ u64 num_cbo;
+
uncore_msr_uncores = uncore_get_uncores(UNCORE_ACCESS_MSR,
UNCORE_SPR_MSR_EXTRA_UNCORES,
spr_msr_uncores);
+ type = uncore_find_type_by_id(uncore_msr_uncores, UNCORE_SPR_CHA);
+ if (type) {
+ rdmsrl(SPR_MSR_UNC_CBO_CONFIG, num_cbo);
+ type->num_boxes = num_cbo;
+ }
spr_uncore_iio_free_running.num_boxes = uncore_type_max_boxes(uncore_msr_uncores, UNCORE_SPR_IIO);
}
--
2.35.1
^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH] perf/x86/uncore: Correct the number of CHAs on SPR
2023-05-08 14:02 [PATCH] perf/x86/uncore: Correct the number of CHAs on SPR kan.liang
@ 2023-05-08 16:16 ` Stephane Eranian
2023-05-24 19:10 ` Liang, Kan
2023-05-25 9:17 ` [tip: perf/urgent] " tip-bot2 for Kan Liang
1 sibling, 1 reply; 5+ messages in thread
From: Stephane Eranian @ 2023-05-08 16:16 UTC (permalink / raw)
To: kan.liang; +Cc: peterz, mingo, linux-kernel, ak, stable
On Mon, May 8, 2023 at 7:05 AM <kan.liang@linux.intel.com> wrote:
>
> From: Kan Liang <kan.liang@linux.intel.com>
>
> The number of CHAs from the discovery table on some SPR variants is
> incorrect, because of a firmware issue. An accurate number can be read
> from the MSR UNC_CBO_CONFIG.
>
> Fixes: 949b11381f81 ("perf/x86/intel/uncore: Add Sapphire Rapids server CHA support")
> Reported-by: Stephane Eranian <eranian@google.com>
> Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Tested-by: Stephane Eranian <eranian@google.com>
>
> Cc: stable@vger.kernel.org
> ---
> arch/x86/events/intel/uncore_snbep.c | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
> diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/uncore_snbep.c
> index 7d1199554fe3..54abd93828bf 100644
> --- a/arch/x86/events/intel/uncore_snbep.c
> +++ b/arch/x86/events/intel/uncore_snbep.c
> @@ -6138,6 +6138,7 @@ static struct intel_uncore_type spr_uncore_mdf = {
> };
>
> #define UNCORE_SPR_NUM_UNCORE_TYPES 12
> +#define UNCORE_SPR_CHA 0
> #define UNCORE_SPR_IIO 1
> #define UNCORE_SPR_IMC 6
> #define UNCORE_SPR_UPI 8
> @@ -6448,12 +6449,22 @@ static int uncore_type_max_boxes(struct intel_uncore_type **types,
> return max + 1;
> }
>
> +#define SPR_MSR_UNC_CBO_CONFIG 0x2FFE
> +
> void spr_uncore_cpu_init(void)
> {
> + struct intel_uncore_type *type;
> + u64 num_cbo;
> +
> uncore_msr_uncores = uncore_get_uncores(UNCORE_ACCESS_MSR,
> UNCORE_SPR_MSR_EXTRA_UNCORES,
> spr_msr_uncores);
>
> + type = uncore_find_type_by_id(uncore_msr_uncores, UNCORE_SPR_CHA);
> + if (type) {
> + rdmsrl(SPR_MSR_UNC_CBO_CONFIG, num_cbo);
> + type->num_boxes = num_cbo;
> + }
> spr_uncore_iio_free_running.num_boxes = uncore_type_max_boxes(uncore_msr_uncores, UNCORE_SPR_IIO);
> }
>
> --
> 2.35.1
>
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH] perf/x86/uncore: Correct the number of CHAs on SPR
2023-05-08 16:16 ` Stephane Eranian
@ 2023-05-24 19:10 ` Liang, Kan
2023-05-24 20:21 ` Peter Zijlstra
0 siblings, 1 reply; 5+ messages in thread
From: Liang, Kan @ 2023-05-24 19:10 UTC (permalink / raw)
To: Stephane Eranian, Peter Zijlstra; +Cc: mingo, linux-kernel, ak, stable
Hi Peter,
On 2023-05-08 12:16 p.m., Stephane Eranian wrote:
> On Mon, May 8, 2023 at 7:05 AM <kan.liang@linux.intel.com> wrote:
>>
>> From: Kan Liang <kan.liang@linux.intel.com>
>>
>> The number of CHAs from the discovery table on some SPR variants is
>> incorrect, because of a firmware issue. An accurate number can be read
>> from the MSR UNC_CBO_CONFIG.
>>
>> Fixes: 949b11381f81 ("perf/x86/intel/uncore: Add Sapphire Rapids server CHA support")
>> Reported-by: Stephane Eranian <eranian@google.com>
>> Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
>
> Tested-by: Stephane Eranian <eranian@google.com>
>
Gentle ping.
Do you have any comments for the patch?
Thanks,
Kan
>>
>> Cc: stable@vger.kernel.org
>> ---
>> arch/x86/events/intel/uncore_snbep.c | 11 +++++++++++
>> 1 file changed, 11 insertions(+)
>>
>> diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/uncore_snbep.c
>> index 7d1199554fe3..54abd93828bf 100644
>> --- a/arch/x86/events/intel/uncore_snbep.c
>> +++ b/arch/x86/events/intel/uncore_snbep.c
>> @@ -6138,6 +6138,7 @@ static struct intel_uncore_type spr_uncore_mdf = {
>> };
>>
>> #define UNCORE_SPR_NUM_UNCORE_TYPES 12
>> +#define UNCORE_SPR_CHA 0
>> #define UNCORE_SPR_IIO 1
>> #define UNCORE_SPR_IMC 6
>> #define UNCORE_SPR_UPI 8
>> @@ -6448,12 +6449,22 @@ static int uncore_type_max_boxes(struct intel_uncore_type **types,
>> return max + 1;
>> }
>>
>> +#define SPR_MSR_UNC_CBO_CONFIG 0x2FFE
>> +
>> void spr_uncore_cpu_init(void)
>> {
>> + struct intel_uncore_type *type;
>> + u64 num_cbo;
>> +
>> uncore_msr_uncores = uncore_get_uncores(UNCORE_ACCESS_MSR,
>> UNCORE_SPR_MSR_EXTRA_UNCORES,
>> spr_msr_uncores);
>>
>> + type = uncore_find_type_by_id(uncore_msr_uncores, UNCORE_SPR_CHA);
>> + if (type) {
>> + rdmsrl(SPR_MSR_UNC_CBO_CONFIG, num_cbo);
>> + type->num_boxes = num_cbo;
>> + }
>> spr_uncore_iio_free_running.num_boxes = uncore_type_max_boxes(uncore_msr_uncores, UNCORE_SPR_IIO);
>> }
>>
>> --
>> 2.35.1
>>
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH] perf/x86/uncore: Correct the number of CHAs on SPR
2023-05-24 19:10 ` Liang, Kan
@ 2023-05-24 20:21 ` Peter Zijlstra
0 siblings, 0 replies; 5+ messages in thread
From: Peter Zijlstra @ 2023-05-24 20:21 UTC (permalink / raw)
To: Liang, Kan; +Cc: Stephane Eranian, mingo, linux-kernel, ak, stable
On Wed, May 24, 2023 at 03:10:00PM -0400, Liang, Kan wrote:
> Hi Peter,
>
> On 2023-05-08 12:16 p.m., Stephane Eranian wrote:
> > On Mon, May 8, 2023 at 7:05 AM <kan.liang@linux.intel.com> wrote:
> >>
> >> From: Kan Liang <kan.liang@linux.intel.com>
> >>
> >> The number of CHAs from the discovery table on some SPR variants is
> >> incorrect, because of a firmware issue. An accurate number can be read
> >> from the MSR UNC_CBO_CONFIG.
> >>
> >> Fixes: 949b11381f81 ("perf/x86/intel/uncore: Add Sapphire Rapids server CHA support")
> >> Reported-by: Stephane Eranian <eranian@google.com>
> >> Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
> >
> > Tested-by: Stephane Eranian <eranian@google.com>
> >
>
> Gentle ping.
Urgh, too much email.. Queued for perf/urgent.
^ permalink raw reply [flat|nested] 5+ messages in thread
* [tip: perf/urgent] perf/x86/uncore: Correct the number of CHAs on SPR
2023-05-08 14:02 [PATCH] perf/x86/uncore: Correct the number of CHAs on SPR kan.liang
2023-05-08 16:16 ` Stephane Eranian
@ 2023-05-25 9:17 ` tip-bot2 for Kan Liang
1 sibling, 0 replies; 5+ messages in thread
From: tip-bot2 for Kan Liang @ 2023-05-25 9:17 UTC (permalink / raw)
To: linux-tip-commits
Cc: Stephane Eranian, Kan Liang, Peter Zijlstra (Intel), stable, x86,
linux-kernel
The following commit has been merged into the perf/urgent branch of tip:
Commit-ID: 38776cc45eb7603df4735a0410f42cffff8e71a1
Gitweb: https://git.kernel.org/tip/38776cc45eb7603df4735a0410f42cffff8e71a1
Author: Kan Liang <kan.liang@linux.intel.com>
AuthorDate: Mon, 08 May 2023 07:02:06 -07:00
Committer: Peter Zijlstra <peterz@infradead.org>
CommitterDate: Wed, 24 May 2023 22:19:41 +02:00
perf/x86/uncore: Correct the number of CHAs on SPR
The number of CHAs from the discovery table on some SPR variants is
incorrect, because of a firmware issue. An accurate number can be read
from the MSR UNC_CBO_CONFIG.
Fixes: 949b11381f81 ("perf/x86/intel/uncore: Add Sapphire Rapids server CHA support")
Reported-by: Stephane Eranian <eranian@google.com>
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Tested-by: Stephane Eranian <eranian@google.com>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20230508140206.283708-1-kan.liang@linux.intel.com
---
arch/x86/events/intel/uncore_snbep.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/uncore_snbep.c
index fa9b209..d49e90d 100644
--- a/arch/x86/events/intel/uncore_snbep.c
+++ b/arch/x86/events/intel/uncore_snbep.c
@@ -6150,6 +6150,7 @@ static struct intel_uncore_type spr_uncore_mdf = {
};
#define UNCORE_SPR_NUM_UNCORE_TYPES 12
+#define UNCORE_SPR_CHA 0
#define UNCORE_SPR_IIO 1
#define UNCORE_SPR_IMC 6
#define UNCORE_SPR_UPI 8
@@ -6460,12 +6461,22 @@ static int uncore_type_max_boxes(struct intel_uncore_type **types,
return max + 1;
}
+#define SPR_MSR_UNC_CBO_CONFIG 0x2FFE
+
void spr_uncore_cpu_init(void)
{
+ struct intel_uncore_type *type;
+ u64 num_cbo;
+
uncore_msr_uncores = uncore_get_uncores(UNCORE_ACCESS_MSR,
UNCORE_SPR_MSR_EXTRA_UNCORES,
spr_msr_uncores);
+ type = uncore_find_type_by_id(uncore_msr_uncores, UNCORE_SPR_CHA);
+ if (type) {
+ rdmsrl(SPR_MSR_UNC_CBO_CONFIG, num_cbo);
+ type->num_boxes = num_cbo;
+ }
spr_uncore_iio_free_running.num_boxes = uncore_type_max_boxes(uncore_msr_uncores, UNCORE_SPR_IIO);
}
^ permalink raw reply related [flat|nested] 5+ messages in thread
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2023-05-08 14:02 [PATCH] perf/x86/uncore: Correct the number of CHAs on SPR kan.liang
2023-05-08 16:16 ` Stephane Eranian
2023-05-24 19:10 ` Liang, Kan
2023-05-24 20:21 ` Peter Zijlstra
2023-05-25 9:17 ` [tip: perf/urgent] " tip-bot2 for Kan Liang
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