[PATCH 0/4] Support partitioned Host1x

[PATCH 0/4] Support partitioned Host1x

[Mikko Perttunen]

The resources (channels, syncpoints) provided by Host1x can be split 
into multiple independent partitions similar to e.g. PCIe VFs, which can 
be assigned to virtual machines, non-CPU embedded controllers, or other 
bus masters.

Each partition has its own MMIO register region and interrupts through 
which the set of channels and syncpoints assigned to it can be accessed. 
This set is configured via the hypervisor MMIO region earlier during 
boot.

This series adds device tree bindings and support in the driver to 
function when Host1x has been partitioned in this way, by making the 
driver work without access to the hypervisor region and with a limited 
set of channels and syncpoints.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
---
Mikko Perttunen (4):
      dt-bindings: display: tegra: Make non-vm registers optional
      dt-bindings: display: tegra: Add channel/syncpoint range properties
      gpu: host1x: Support running without hv/common registers
      gpu: host1x: Allow limiting usable channel and syncpoint ranges

 .../display/tegra/nvidia,tegra20-host1x.yaml       | 52 ++++++++++++++++------
 drivers/gpu/host1x/channel.c                       |  6 +--
 drivers/gpu/host1x/dev.c                           | 52 +++++++++++++++++++---
 drivers/gpu/host1x/dev.h                           |  3 ++
 drivers/gpu/host1x/hw/cdma_hw.c                    |  3 ++
 drivers/gpu/host1x/hw/debug_hw_1x06.c              |  3 ++
 drivers/gpu/host1x/syncpt.c                        | 21 +++++----
 7 files changed, 110 insertions(+), 30 deletions(-)
---
base-commit: 4549871118cf616eecdd2d939f78e3b9e1dddc48
change-id: 20250919-host1x-nohv-071ed7c6ac4f

[PATCH 1/4] dt-bindings: display: tegra: Make non-vm registers optional

[Mikko Perttunen]

Host1x can be used without accessing the hypervisor or common
registers. Adjust the bindings to make them optional.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
---
 .../display/tegra/nvidia,tegra20-host1x.yaml       | 40 ++++++++++++++--------
 1 file changed, 26 insertions(+), 14 deletions(-)

diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.yaml
index 3563378a01af..ffd0ed857d28 100644
--- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.yaml
+++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.yaml
@@ -145,14 +145,20 @@ allOf:
     then:
       properties:
         reg-names:
-          items:
-            - const: hypervisor
-            - const: vm
+          oneOf:
+            - items:
+                - const: hypervisor
+                - const: vm
+            - items:
+                - const: vm
 
         reg:
-          items:
-            - description: region used by the hypervisor
-            - description: region assigned to the virtual machine
+          oneOf:
+            - items:
+                - description: region used by the hypervisor
+                - description: region assigned to the virtual machine
+            - items:
+                - description: region assigned to the virtual machine
 
         resets:
           maxItems: 1
@@ -195,16 +201,22 @@ allOf:
     then:
       properties:
         reg-names:
-          items:
-            - const: common
-            - const: hypervisor
-            - const: vm
+          oneOf:
+            - items:
+                - const: common
+                - const: hypervisor
+                - const: vm
+            - items:
+                - const: vm
 
         reg:
-          items:
-            - description: region used by host1x server
-            - description: region used by the hypervisor
-            - description: region assigned to the virtual machine
+          oneOf:
+            - items:
+                - description: region used by host1x server
+                - description: region used by the hypervisor
+                - description: region assigned to the virtual machine
+            - items:
+                - description: region assigned to the virtual machine
 
         interrupts:
           items:

-- 
2.53.0

[PATCH 2/4] dt-bindings: display: tegra: Add channel/syncpoint range properties

[Mikko Perttunen]

Channels and syncpoints available may be limited when other system
components are using them. Add properties nvidia,channels and
nvidia,syncpoints to limit the range of usable channels and/or
syncpoints.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
---
 .../bindings/display/tegra/nvidia,tegra20-host1x.yaml        | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.yaml
index ffd0ed857d28..7a543b8b2f3d 100644
--- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.yaml
+++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.yaml
@@ -96,6 +96,18 @@ properties:
     items:
       - description: phandle to the HEG or core power domain
 
+  nvidia,channels:
+    $ref: /schemas/types.yaml#/definitions/uint32-array
+    minItems: 2
+    maxItems: 2
+    description: Describes usable channel range as a <base count> tuple.
+
+  nvidia,syncpoints:
+    $ref: /schemas/types.yaml#/definitions/uint32-array
+    minItems: 2
+    maxItems: 2
+    description: Describes writable syncpoint range as a <base count> tuple.
+
 required:
   - compatible
   - interrupts

-- 
2.53.0

[PATCH 3/4] gpu: host1x: Support running without hv/common registers

[Mikko Perttunen]

Host1x can be used without access to the hypervisor or common regions
when they are configured by other components in the system. Add support
for running without access to them.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
---
 drivers/gpu/host1x/dev.c              | 15 ++++++++++-----
 drivers/gpu/host1x/hw/cdma_hw.c       |  3 +++
 drivers/gpu/host1x/hw/debug_hw_1x06.c |  3 +++
 3 files changed, 16 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/host1x/dev.c b/drivers/gpu/host1x/dev.c
index 3f475f0e6545..545fa2e3f180 100644
--- a/drivers/gpu/host1x/dev.c
+++ b/drivers/gpu/host1x/dev.c
@@ -305,7 +305,7 @@ static void host1x_setup_virtualization_tables(struct host1x *host)
 	const struct host1x_info *info = host->info;
 	unsigned int i;
 
-	if (!info->has_hypervisor)
+	if (!host->hv_regs)
 		return;
 
 	for (i = 0; i < info->num_sid_entries; i++) {
@@ -532,15 +532,20 @@ static int host1x_probe(struct platform_device *pdev)
 	host->info = of_device_get_match_data(&pdev->dev);
 
 	if (host->info->has_hypervisor) {
+		struct resource *res;
+
 		host->regs = devm_platform_ioremap_resource_byname(pdev, "vm");
 		if (IS_ERR(host->regs))
 			return PTR_ERR(host->regs);
 
-		host->hv_regs = devm_platform_ioremap_resource_byname(pdev, "hypervisor");
-		if (IS_ERR(host->hv_regs))
-			return PTR_ERR(host->hv_regs);
+		res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hypervisor");
+		if (res) {
+			host->hv_regs = devm_ioremap_resource(&pdev->dev, res);
+			if (IS_ERR(host->hv_regs))
+				return PTR_ERR(host->hv_regs);
+		}
 
-		if (host->info->has_common) {
+		if (res && host->info->has_common) {
 			host->common_regs = devm_platform_ioremap_resource_byname(pdev, "common");
 			if (IS_ERR(host->common_regs))
 				return PTR_ERR(host->common_regs);
diff --git a/drivers/gpu/host1x/hw/cdma_hw.c b/drivers/gpu/host1x/hw/cdma_hw.c
index 3f3f0018eee0..85f7e5633555 100644
--- a/drivers/gpu/host1x/hw/cdma_hw.c
+++ b/drivers/gpu/host1x/hw/cdma_hw.c
@@ -253,6 +253,9 @@ static void timeout_release_mlock(struct host1x_cdma *cdma)
 	struct host1x *host1x = cdma_to_host1x(cdma);
 	u32 offset;
 
+	if (!host1x->common_regs)
+		return;
+
 	switch (ch->client->class) {
 	case HOST1X_CLASS_NVJPG1:
 		offset = HOST1X_COMMON_NVJPG1_MLOCK;
diff --git a/drivers/gpu/host1x/hw/debug_hw_1x06.c b/drivers/gpu/host1x/hw/debug_hw_1x06.c
index 9d0667879a19..324e76436f7b 100644
--- a/drivers/gpu/host1x/hw/debug_hw_1x06.c
+++ b/drivers/gpu/host1x/hw/debug_hw_1x06.c
@@ -87,6 +87,9 @@ static void host1x_debug_show_channel_fifo(struct host1x *host,
 	host1x_debug_output(o, "CMDFIFO_RDATA %08x\n", val);
 
 #if HOST1X_HW <= 6
+	if (!host->hv_regs)
+		return;
+
 	/* Peek pointer values are invalid during SLCG, so disable it */
 	host1x_hypervisor_writel(host, 0x1, HOST1X_HV_ICG_EN_OVERRIDE);
 

-- 
2.53.0

[PATCH 4/4] gpu: host1x: Allow limiting usable channel and syncpoint ranges

[Mikko Perttunen]

Allow specifying usable channel, and allocatable syncpoint ranges
through the device tree. This is necessary when Host1x resources
are shared between multiple operating systems or independent hardware
units and Linux has limited access to them.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
---
 drivers/gpu/host1x/channel.c |  6 +++---
 drivers/gpu/host1x/dev.c     | 37 +++++++++++++++++++++++++++++++++++++
 drivers/gpu/host1x/dev.h     |  3 +++
 drivers/gpu/host1x/syncpt.c  | 21 +++++++++++++--------
 4 files changed, 56 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/host1x/channel.c b/drivers/gpu/host1x/channel.c
index ca5d0f51cf7d..38fcdda8388a 100644
--- a/drivers/gpu/host1x/channel.c
+++ b/drivers/gpu/host1x/channel.c
@@ -121,13 +121,13 @@ EXPORT_SYMBOL(host1x_channel_put);
 static struct host1x_channel *acquire_unused_channel(struct host1x *host)
 {
 	struct host1x_channel_list *chlist = &host->channel_list;
-	unsigned int max_channels = host->info->nb_channels;
 	unsigned int index;
 
 	mutex_lock(&chlist->lock);
 
-	index = find_first_zero_bit(chlist->allocated_channels, max_channels);
-	if (index >= max_channels) {
+	index = find_next_zero_bit(chlist->allocated_channels,
+				   host->channel_end, host->channel_base);
+	if (index >= host->channel_end) {
 		mutex_unlock(&chlist->lock);
 		dev_err(host->dev, "failed to find free channel\n");
 		return NULL;
diff --git a/drivers/gpu/host1x/dev.c b/drivers/gpu/host1x/dev.c
index 545fa2e3f180..7103f018cb1b 100644
--- a/drivers/gpu/host1x/dev.c
+++ b/drivers/gpu/host1x/dev.c
@@ -331,6 +331,39 @@ static void host1x_setup_virtualization_tables(struct host1x *host)
 	}
 }
 
+static int host1x_get_assigned_resources(struct host1x *host)
+{
+	struct device_node *np = host->dev->of_node;
+	u32 vals[2];
+	int err;
+
+	err = of_property_read_u32_array(np, "nvidia,channels", vals, 2);
+	if (err == 0) {
+		host->channel_base = vals[0];
+		host->channel_end = vals[0] + vals[1];
+	} else if (err == -EINVAL) {
+		host->channel_base = 0;
+		host->channel_end = host->info->nb_channels;
+	} else {
+		dev_err(host->dev, "invalid nvidia,channels property: %d\n", err);
+		return err;
+	}
+
+	err = of_property_read_u32_array(np, "nvidia,syncpoints", vals, 2);
+	if (err == 0) {
+		host->syncpt_base = vals[0];
+		host->syncpt_end = vals[0] + vals[1];
+	} else if (err == -EINVAL) {
+		host->syncpt_base = 0;
+		host->syncpt_end = host->info->nb_pts;
+	} else {
+		dev_err(host->dev, "invalid nvidia,syncpoints property: %d\n", err);
+		return err;
+	}
+
+	return 0;
+}
+
 static bool host1x_wants_iommu(struct host1x *host1x)
 {
 	/* Our IOMMU usage policy doesn't currently play well with GART */
@@ -602,6 +635,10 @@ static int host1x_probe(struct platform_device *pdev)
 	if (IS_ERR(host->clk))
 		return dev_err_probe(&pdev->dev, PTR_ERR(host->clk), "failed to get clock\n");
 
+	err = host1x_get_assigned_resources(host);
+	if (err)
+		return err;
+
 	err = host1x_get_resets(host);
 	if (err)
 		return err;
diff --git a/drivers/gpu/host1x/dev.h b/drivers/gpu/host1x/dev.h
index ef44618ed88a..89f1fc838a1c 100644
--- a/drivers/gpu/host1x/dev.h
+++ b/drivers/gpu/host1x/dev.h
@@ -141,6 +141,9 @@ struct host1x {
 	struct reset_control_bulk_data resets[2];
 	unsigned int nresets;
 
+	unsigned int syncpt_base, syncpt_end;
+	unsigned int channel_base, channel_end;
+
 	struct iommu_group *group;
 	struct iommu_domain *domain;
 	struct iova_domain iova;
diff --git a/drivers/gpu/host1x/syncpt.c b/drivers/gpu/host1x/syncpt.c
index acc7d82e0585..fe27a386cc0c 100644
--- a/drivers/gpu/host1x/syncpt.c
+++ b/drivers/gpu/host1x/syncpt.c
@@ -59,7 +59,7 @@ struct host1x_syncpt *host1x_syncpt_alloc(struct host1x *host,
 					  unsigned long flags,
 					  const char *name)
 {
-	struct host1x_syncpt *sp = host->syncpt;
+	struct host1x_syncpt *sp = host->syncpt + host->syncpt_base;
 	char *full_name;
 	unsigned int i;
 
@@ -68,10 +68,10 @@ struct host1x_syncpt *host1x_syncpt_alloc(struct host1x *host,
 
 	mutex_lock(&host->syncpt_mutex);
 
-	for (i = 0; i < host->info->nb_pts && kref_read(&sp->ref); i++, sp++)
+	for (i = host->syncpt_base; i < host->syncpt_end && kref_read(&sp->ref); i++, sp++)
 		;
 
-	if (i >= host->info->nb_pts)
+	if (i >= host->syncpt_end)
 		goto unlock;
 
 	if (flags & HOST1X_SYNCPT_HAS_BASE) {
@@ -138,7 +138,7 @@ void host1x_syncpt_restore(struct host1x *host)
 	struct host1x_syncpt *sp_base = host->syncpt;
 	unsigned int i;
 
-	for (i = 0; i < host1x_syncpt_nb_pts(host); i++) {
+	for (i = host->syncpt_base; i < host->syncpt_end; i++) {
 		/*
 		 * Unassign syncpt from channels for purposes of Tegra186
 		 * syncpoint protection. This prevents any channel from
@@ -296,6 +296,9 @@ int host1x_syncpt_init(struct host1x *host)
 	for (i = 0; i < host->info->nb_pts; i++) {
 		syncpt[i].id = i;
 		syncpt[i].host = host;
+
+		/* Default to client managed for syncpoints not owned by us */
+		syncpt[i].client_managed = true;
 	}
 
 	for (i = 0; i < host->info->nb_bases; i++)
@@ -305,10 +308,12 @@ int host1x_syncpt_init(struct host1x *host)
 	host->syncpt = syncpt;
 	host->bases = bases;
 
-	/* Allocate sync point to use for clearing waits for expired fences */
-	host->nop_sp = host1x_syncpt_alloc(host, 0, "reserved-nop");
-	if (!host->nop_sp)
-		return -ENOMEM;
+	/* Prevent syncpoint 0 from being allocated by users */
+	if (host->syncpt_base == 0) {
+		host->nop_sp = host1x_syncpt_alloc(host, 0, "reserved-nop");
+		if (!host->nop_sp)
+			return -ENOMEM;
+	}
 
 	if (host->info->reserve_vblank_syncpts) {
 		kref_init(&host->syncpt[26].ref);

-- 
2.53.0

Re: [PATCH 1/4] dt-bindings: display: tegra: Make non-vm registers optional

[Krzysztof Kozlowski]

On Mon, Jun 22, 2026 at 05:22:50PM +0900, Mikko Perttunen wrote:
> Host1x can be used without accessing the hypervisor or common
> registers. Adjust the bindings to make them optional.

You still have these registers in the hardware, so it is not optional,
not flexible. IOW, DTS represents the view of real hardware for the
software, and that hardware still has this address space regardless if
OS should use it or not.

Otherwise you need to provide better background here.

Best regards,
Krzysztof

Re: [PATCH 2/4] dt-bindings: display: tegra: Add channel/syncpoint range properties

[Krzysztof Kozlowski]

On Mon, Jun 22, 2026 at 05:22:51PM +0900, Mikko Perttunen wrote:
> Channels and syncpoints available may be limited when other system

What are channels and syncpoints?

> components are using them. Add properties nvidia,channels and
> nvidia,syncpoints to limit the range of usable channels and/or
> syncpoints.

Why isn't this deducible from the compatible?

Also, nvidia,channels is too broad/generic. This is not ADC, right? And
channels is a common term in IIO. And in few other cases.

Best regards,
Krzysztof

Re: [PATCH 1/4] dt-bindings: display: tegra: Make non-vm registers optional

[Mikko Perttunen]

On Thursday, June 25, 2026 5:34 PM Krzysztof Kozlowski wrote:
> On Mon, Jun 22, 2026 at 05:22:50PM +0900, Mikko Perttunen wrote:
> > Host1x can be used without accessing the hypervisor or common
> > registers. Adjust the bindings to make them optional.
> 
> You still have these registers in the hardware, so it is not optional,
> not flexible. IOW, DTS represents the view of real hardware for the
> software, and that hardware still has this address space regardless if
> OS should use it or not.
> 
> Otherwise you need to provide better background here.
> 
> Best regards,
> Krzysztof
> 
> 

The intent is that the vm-only version is used in situations where the
other register regions are not available to software. Typically that
means running as a virtual machine, and the hypervisor owns the non-vm
register regions and doesn't pass them to the guest.

Since the guest runs under the hypervisor, its view of 'real hardware'
is what the hypervisor is exposing to it -- in this case with just the
"vm" register region.

I'll add further explanation along above lines to the commit message
if you're OK with it.

Thank you
Mikko

Re: [PATCH 2/4] dt-bindings: display: tegra: Add channel/syncpoint range properties

[Mikko Perttunen]

On Thursday, June 25, 2026 5:36 PM Krzysztof Kozlowski wrote:
> On Mon, Jun 22, 2026 at 05:22:51PM +0900, Mikko Perttunen wrote:
> > Channels and syncpoints available may be limited when other system
> 
> What are channels and syncpoints?

Very host1x-specific hardware resources. Somewhat close to GPU channels
and semaphores / fences if you're familiar with those.

> 
> > components are using them. Add properties nvidia,channels and
> > nvidia,syncpoints to limit the range of usable channels and/or
> > syncpoints.
> 
> Why isn't this deducible from the compatible?

When Host1x is partitioned, the hypervisor (or other software entity
with access to the non-vm host1x register regions) can configure which
channels and syncpoints are available to each partition arbitrarily.

How that partitioning was done is not discoverable through hardware
directly, so we need to pass that information through device tree.

> 
> Also, nvidia,channels is too broad/generic. This is not ADC, right? And
> channels is a common term in IIO. And in few other cases.

It's not ADC. Yes, it's a common term in a lot of contexts. I can call
it nvidia,host1x-channels if you prefer but that seems a bit redundant
given the context.

> 
> Best regards,
> Krzysztof
> 
> 

Thank you
Mikko

Re: [PATCH 1/4] dt-bindings: display: tegra: Make non-vm registers optional

[Krzysztof Kozlowski]

On Thu, Jun 25, 2026 at 06:17:39PM +0900, Mikko Perttunen wrote:
> On Thursday, June 25, 2026 5:34 PM Krzysztof Kozlowski wrote:
> > On Mon, Jun 22, 2026 at 05:22:50PM +0900, Mikko Perttunen wrote:
> > > Host1x can be used without accessing the hypervisor or common
> > > registers. Adjust the bindings to make them optional.
> > 
> > You still have these registers in the hardware, so it is not optional,
> > not flexible. IOW, DTS represents the view of real hardware for the
> > software, and that hardware still has this address space regardless if
> > OS should use it or not.
> > 
> > Otherwise you need to provide better background here.
> > 
> > Best regards,
> > Krzysztof
> > 
> > 
> 
> The intent is that the vm-only version is used in situations where the
> other register regions are not available to software. Typically that
> means running as a virtual machine, and the hypervisor owns the non-vm
> register regions and doesn't pass them to the guest.
> 
> Since the guest runs under the hypervisor, its view of 'real hardware'
> is what the hypervisor is exposing to it -- in this case with just the
> "vm" register region.
> 
> I'll add further explanation along above lines to the commit message
> if you're OK with it.

Yeah, it's fine. Please extend the commit msg to make it more obvious.

Best regards,
Krzysztof

Re: [PATCH 2/4] dt-bindings: display: tegra: Add channel/syncpoint range properties

[Krzysztof Kozlowski]

On Thu, Jun 25, 2026 at 06:26:43PM +0900, Mikko Perttunen wrote:
> On Thursday, June 25, 2026 5:36 PM Krzysztof Kozlowski wrote:
> > On Mon, Jun 22, 2026 at 05:22:51PM +0900, Mikko Perttunen wrote:
> > > Channels and syncpoints available may be limited when other system
> > 
> > What are channels and syncpoints?
> 
> Very host1x-specific hardware resources. Somewhat close to GPU channels
> and semaphores / fences if you're familiar with those.
> 
> > 
> > > components are using them. Add properties nvidia,channels and
> > > nvidia,syncpoints to limit the range of usable channels and/or
> > > syncpoints.
> > 
> > Why isn't this deducible from the compatible?
> 
> When Host1x is partitioned, the hypervisor (or other software entity
> with access to the non-vm host1x register regions) can configure which
> channels and syncpoints are available to each partition arbitrarily.

So you will have different boards for the same SoC with different
values?

> 
> How that partitioning was done is not discoverable through hardware
> directly, so we need to pass that information through device tree.
> 
> > 
> > Also, nvidia,channels is too broad/generic. This is not ADC, right? And
> > channels is a common term in IIO. And in few other cases.
> 
> It's not ADC. Yes, it's a common term in a lot of contexts. I can call
> it nvidia,host1x-channels if you prefer but that seems a bit redundant
> given the context.

host1x is indeed poor, but maybe there is some way to be a bit more
descriptive? message-channels?

Best regards,
Krzysztof

Re: [PATCH 2/4] dt-bindings: display: tegra: Add channel/syncpoint range properties

[Mikko Perttunen]

On Friday, June 26, 2026 7:26 PM Krzysztof Kozlowski wrote:
> On Thu, Jun 25, 2026 at 06:26:43PM +0900, Mikko Perttunen wrote:
> > On Thursday, June 25, 2026 5:36 PM Krzysztof Kozlowski wrote:
> > > On Mon, Jun 22, 2026 at 05:22:51PM +0900, Mikko Perttunen wrote:
> > > > Channels and syncpoints available may be limited when other system
> > > 
> > > What are channels and syncpoints?
> > 
> > Very host1x-specific hardware resources. Somewhat close to GPU channels
> > and semaphores / fences if you're familiar with those.
> > 
> > > 
> > > > components are using them. Add properties nvidia,channels and
> > > > nvidia,syncpoints to limit the range of usable channels and/or
> > > > syncpoints.
> > > 
> > > Why isn't this deducible from the compatible?
> > 
> > When Host1x is partitioned, the hypervisor (or other software entity
> > with access to the non-vm host1x register regions) can configure which
> > channels and syncpoints are available to each partition arbitrarily.
> 
> So you will have different boards for the same SoC with different
> values?
> 

Yes -- even the same board will have different values depending on the
use case of the system. The hypervisor or bootloader has to update the
properties according to the configuration it has programmed in the
hardware.

I will update the commit message with clarification.

> > 
> > How that partitioning was done is not discoverable through hardware
> > directly, so we need to pass that information through device tree.
> > 
> > > 
> > > Also, nvidia,channels is too broad/generic. This is not ADC, right? And
> > > channels is a common term in IIO. And in few other cases.
> > 
> > It's not ADC. Yes, it's a common term in a lot of contexts. I can call
> > it nvidia,host1x-channels if you prefer but that seems a bit redundant
> > given the context.
> 
> host1x is indeed poor, but maybe there is some way to be a bit more
> descriptive? message-channels?

I would prefer to keep these as is -- anyone working with host1x will
know what 'channels' and 'syncpoints' mean, and changing the name could
cause confusion since the name would not match other code or
documentation discussing these.

I can update the binding documentation with some more explanation about
what these properties mean.

Thank you
Mikko

> 
> Best regards,
> Krzysztof
>