Re: [PATCH v3 2/3] drivers: clk: Add support for versa3 clock driver

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* Re: [PATCH v3 2/3] drivers: clk: Add support for versa3 clock driver
       [not found] <20230403103257.328954-3-biju.das.jz@bp.renesas.com>
@ 2023-04-04  0:47 ` kernel test robot
  2023-04-04  6:12   ` Biju Das
  0 siblings, 1 reply; 2+ messages in thread
From: kernel test robot @ 2023-04-04  0:47 UTC (permalink / raw)
  To: Biju Das, Michael Turquette, Stephen Boyd
  Cc: llvm, oe-kbuild-all, Biju Das, linux-clk, Geert Uytterhoeven,
	Prabhakar Mahadev Lad, linux-renesas-soc

Hi Biju,

kernel test robot noticed the following build warnings:

[auto build test WARNING on clk/clk-next]
[also build test WARNING on next-20230403]
[cannot apply to geert-renesas-devel/next robh/for-next linus/master v6.3-rc5]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Biju-Das/dt-bindings-clock-Add-Renesas-versa3-clock-generator-bindings/20230403-183501
base:   https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-next
patch link:    https://lore.kernel.org/r/20230403103257.328954-3-biju.das.jz%40bp.renesas.com
patch subject: [PATCH v3 2/3] drivers: clk: Add support for versa3 clock driver
config: i386-allmodconfig (https://download.01.org/0day-ci/archive/20230404/202304040800.ncpvZq1s-lkp@intel.com/config)
compiler: clang version 14.0.6 (https://github.com/llvm/llvm-project f28c006a5895fc0e329fe15fead81e37457cb1d1)
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # https://github.com/intel-lab-lkp/linux/commit/bd1f4d06603f7dc65276411a65078a8ffaf5b844
        git remote add linux-review https://github.com/intel-lab-lkp/linux
        git fetch --no-tags linux-review Biju-Das/dt-bindings-clock-Add-Renesas-versa3-clock-generator-bindings/20230403-183501
        git checkout bd1f4d06603f7dc65276411a65078a8ffaf5b844
        # save the config file
        mkdir build_dir && cp config build_dir/.config
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=i386 olddefconfig
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=i386 SHELL=/bin/bash drivers/clk/ drivers/gpio/

If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>
| Link: https://lore.kernel.org/oe-kbuild-all/202304040800.ncpvZq1s-lkp@intel.com/

All warnings (new ones prefixed by >>):

>> drivers/clk/clk-versaclock3.c:263:8: warning: variable 'premul' is uninitialized when used here [-Wuninitialized]
                           if (premul & VC3_PLL2_MDIV_DOUBLER)
                               ^~~~~~
   drivers/clk/clk-versaclock3.c:244:29: note: initialize the variable 'premul' to silence this warning
           unsigned int prediv, premul;
                                      ^
                                       = 0
   1 warning generated.


vim +/premul +263 drivers/clk/clk-versaclock3.c

   238	
   239	static unsigned long vc3_pfd_recalc_rate(struct clk_hw *hw,
   240						 unsigned long parent_rate)
   241	{
   242		struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw);
   243		const struct vc3_pfd_data *pfd = vc3->data;
   244		unsigned int prediv, premul;
   245		unsigned long rate;
   246		u8 mdiv;
   247	
   248		regmap_read(vc3->regmap, pfd->offs, &prediv);
   249		if (pfd->num == VC3_PFD1) {
   250			/* The bypass_prediv is set, PLL fed from Ref_in directly. */
   251			if (prediv & pfd->mdiv1_bitmsk) {
   252				/* check doubler is set or not */
   253				regmap_read(vc3->regmap, VC3_PLL1_CTRL_OUTDIV5, &premul);
   254				if (premul & VC3_PLL1_CTRL_OUTDIV5_PLL1_MDIV_DOUBLER)
   255					parent_rate *= 2;
   256				return parent_rate;
   257			}
   258			mdiv = VC3_PLL1_M_DIV(prediv);
   259		} else if (pfd->num == VC3_PFD2) {
   260			/* The bypass_prediv is set, PLL fed from Ref_in directly. */
   261			if (prediv & pfd->mdiv1_bitmsk) {
   262				/* check doubler is set or not */
 > 263				if (premul & VC3_PLL2_MDIV_DOUBLER)
   264					parent_rate *= 2;
   265				return parent_rate;
   266			}
   267	
   268			mdiv = VC3_PLL2_M_DIV(prediv);
   269		} else {
   270			/* The bypass_prediv is set, PLL fed from Ref_in directly. */
   271			if (prediv & pfd->mdiv1_bitmsk)
   272				return parent_rate;
   273	
   274			mdiv = VC3_PLL3_M_DIV(prediv);
   275		}
   276	
   277		if (prediv & pfd->mdiv2_bitmsk)
   278			rate = parent_rate / 2;
   279		else
   280			rate = parent_rate / mdiv;
   281	
   282		return rate;
   283	}
   284	

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests

^ permalink raw reply	[flat|nested] 2+ messages in thread

* RE: [PATCH v3 2/3] drivers: clk: Add support for versa3 clock driver
  2023-04-04  0:47 ` [PATCH v3 2/3] drivers: clk: Add support for versa3 clock driver kernel test robot
@ 2023-04-04  6:12   ` Biju Das
  0 siblings, 0 replies; 2+ messages in thread
From: Biju Das @ 2023-04-04  6:12 UTC (permalink / raw)
  To: kernel test robot, Michael Turquette, Stephen Boyd
  Cc: llvm@lists.linux.dev, oe-kbuild-all@lists.linux.dev,
	linux-clk@vger.kernel.org, Geert Uytterhoeven,
	Prabhakar Mahadev Lad, linux-renesas-soc@vger.kernel.org

Hi Kernel test robot,

Thanks for the feedback.

> -----Original Message-----
> From: kernel test robot <lkp@intel.com>
> Sent: Tuesday, April 4, 2023 1:48 AM
> To: Biju Das <biju.das.jz@bp.renesas.com>; Michael Turquette
> <mturquette@baylibre.com>; Stephen Boyd <sboyd@kernel.org>
> Cc: llvm@lists.linux.dev; oe-kbuild-all@lists.linux.dev; Biju Das
> <biju.das.jz@bp.renesas.com>; linux-clk@vger.kernel.org; Geert Uytterhoeven
> <geert+renesas@glider.be>; Prabhakar Mahadev Lad <prabhakar.mahadev-
> lad.rj@bp.renesas.com>; linux-renesas-soc@vger.kernel.org
> Subject: Re: [PATCH v3 2/3] drivers: clk: Add support for versa3 clock
> driver
> 
> Hi Biju,
> 
> kernel test robot noticed the following build warnings:
> 
> [auto build test WARNING on clk/clk-next] [also build test WARNING on next-
> 20230403] [cannot apply to geert-renesas-devel/next robh/for-next
> linus/master v6.3-rc5] [If your patch is applied to the wrong git tree,
> kindly drop us a note.
> And when submitting patch, we suggest to use '--base' as documented in
> 
> url:
> https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.com
> %2Fintel-lab-lkp%2Flinux%2Fcommits%2FBiju-Das%2Fdt-bindings-clock-Add-
> Renesas-versa3-clock-generator-bindings%2F20230403-
> 183501&data=05%7C01%7Cbiju.das.jz%40bp.renesas.com%7C58183605a92243fe44db08d
> b34a63aba%7C53d82571da1947e49cb4625a166a4a2a%7C0%7C0%7C638161660780169608%7C
> Unknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLC
> JXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=%2FlQd5k6qitRjbT3FFrwsiiFRxsPc0bPR9ssY2U%
> 2BTvmI%3D&reserved=0
> base:
> https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgit.kernel
> .org%2Fpub%2Fscm%2Flinux%2Fkernel%2Fgit%2Fclk%2Flinux.git&data=05%7C01%7Cbij
> u.das.jz%40bp.renesas.com%7C58183605a92243fe44db08db34a63aba%7C53d82571da194
> 7e49cb4625a166a4a2a%7C0%7C0%7C638161660780169608%7CUnknown%7CTWFpbGZsb3d8eyJ
> WIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C
> %7C&sdata=n65lwFazrJlBTaePPOypLBT6NbnGpoePrA%2BALALQlD0%3D&reserved=0 clk-
> next
> patch link:
> https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore.kerne
> l.org%2Fr%2F20230403103257.328954-3-
> biju.das.jz%2540bp.renesas.com&data=05%7C01%7Cbiju.das.jz%40bp.renesas.com%7
> C58183605a92243fe44db08db34a63aba%7C53d82571da1947e49cb4625a166a4a2a%7C0%7C0
> %7C638161660780169608%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2
> luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=2vmd29m6ifdZdZMD%
> 2FC0F9L9nX0rBUv%2BgTV0tKLn%2Bkb0%3D&reserved=0
> patch subject: [PATCH v3 2/3] drivers: clk: Add support for versa3 clock
> driver
> config: i386-allmodconfig
> (https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fdownload.
> 01.org%2F0day-ci%2Farchive%2F20230404%2F202304040800.ncpvZq1s-
> lkp%40intel.com%2Fconfig&data=05%7C01%7Cbiju.das.jz%40bp.renesas.com%7C58183
> 605a92243fe44db08db34a63aba%7C53d82571da1947e49cb4625a166a4a2a%7C0%7C0%7C638
> 161660780169608%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIi
> LCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=JMiZ588SYVvNqlMaOt1qh6h
> iN9%2BOcVqbUMkjtV842MQ%3D&reserved=0)
> compiler: clang version 14.0.6
> (https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.co
> m%2Fllvm%2Fllvm-
> project&data=05%7C01%7Cbiju.das.jz%40bp.renesas.com%7C58183605a92243fe44db08
> db34a63aba%7C53d82571da1947e49cb4625a166a4a2a%7C0%7C0%7C638161660780169608%7
> CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiL
> CJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=PR98XaFLqi%2BNzWnn9FDX3lU6vS1PChtzEelYqv
> t077Y%3D&reserved=0 f28c006a5895fc0e329fe15fead81e37457cb1d1)
> reproduce (this is a W=1 build):
>         wget
> https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fraw.github
> usercontent.com%2Fintel%2Flkp-
> tests%2Fmaster%2Fsbin%2Fmake.cross&data=05%7C01%7Cbiju.das.jz%40bp.renesas.c
> om%7C58183605a92243fe44db08db34a63aba%7C53d82571da1947e49cb4625a166a4a2a%7C0
> %7C0%7C638161660780169608%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIj
> oiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=fF7xxF2viUDJj
> LVZQXq8Vgk9QsZOgiI3ffa9oPVGzfo%3D&reserved=0 -O ~/bin/make.cross
>         chmod +x ~/bin/make.cross
>         #
> https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.com
> %2Fintel-lab-
> lkp%2Flinux%2Fcommit%2Fbd1f4d06603f7dc65276411a65078a8ffaf5b844&data=05%7C01
> %7Cbiju.das.jz%40bp.renesas.com%7C58183605a92243fe44db08db34a63aba%7C53d8257
> 1da1947e49cb4625a166a4a2a%7C0%7C0%7C638161660780169608%7CUnknown%7CTWFpbGZsb
> 3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000
> %7C%7C%7C&sdata=seeuNQwOMRNcZEb6iBQsenX3J1ABOFlqiXcPGBnMPHA%3D&reserved=0
>         git remote add linux-review
> https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.com
> %2Fintel-lab-
> lkp%2Flinux&data=05%7C01%7Cbiju.das.jz%40bp.renesas.com%7C58183605a92243fe44
> db08db34a63aba%7C53d82571da1947e49cb4625a166a4a2a%7C0%7C0%7C6381616607801696
> 08%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1ha
> WwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=fbe%2BNELrfZ%2B6ovAfKfPAugDF2oyiacAL
> 2g%2BnKunFD%2BE%3D&reserved=0
>         git fetch --no-tags linux-review Biju-Das/dt-bindings-clock-Add-
> Renesas-versa3-clock-generator-bindings/20230403-183501
>         git checkout bd1f4d06603f7dc65276411a65078a8ffaf5b844
>         # save the config file
>         mkdir build_dir && cp config build_dir/.config
>         COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1
> O=build_dir ARCH=i386 olddefconfig
>         COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1
> O=build_dir ARCH=i386 SHELL=/bin/bash drivers/clk/ drivers/gpio/
> 
> If you fix the issue, kindly add following tag where applicable
> | Reported-by: kernel test robot <lkp@intel.com>
> | Link:
> | https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore
> | .kernel.org%2Foe-kbuild-all%2F202304040800.ncpvZq1s-lkp%40intel.com%2F
> | &data=05%7C01%7Cbiju.das.jz%40bp.renesas.com%7C58183605a92243fe44db08d
> | b34a63aba%7C53d82571da1947e49cb4625a166a4a2a%7C0%7C0%7C638161660780169
> | 608%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTi
> | I6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=Ii1JCf7g5RtSpgCR%2FMklY
> | EM5m12V%2BgrH401aJUZZVSg%3D&reserved=0
> 
> All warnings (new ones prefixed by >>):
> 
> >> drivers/clk/clk-versaclock3.c:263:8: warning: variable 'premul' is
> >> uninitialized when used here [-Wuninitialized]
>                            if (premul & VC3_PLL2_MDIV_DOUBLER)
>                                ^~~~~~
>    drivers/clk/clk-versaclock3.c:244:29: note: initialize the variable
> 'premul' to silence this warning
>            unsigned int prediv, premul;
>                                       ^
>                                        = 0
>    1 warning generated.
> 
> 
> vim +/premul +263 drivers/clk/clk-versaclock3.c

OK, will fix this warning in the next version.

Cheers,
Biju

> 
>    238
>    239	static unsigned long vc3_pfd_recalc_rate(struct clk_hw *hw,
>    240						 unsigned long parent_rate)
>    241	{
>    242		struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data,
> hw);
>    243		const struct vc3_pfd_data *pfd = vc3->data;
>    244		unsigned int prediv, premul;
>    245		unsigned long rate;
>    246		u8 mdiv;
>    247
>    248		regmap_read(vc3->regmap, pfd->offs, &prediv);
>    249		if (pfd->num == VC3_PFD1) {
>    250			/* The bypass_prediv is set, PLL fed from Ref_in
> directly. */
>    251			if (prediv & pfd->mdiv1_bitmsk) {
>    252				/* check doubler is set or not */
>    253				regmap_read(vc3->regmap, VC3_PLL1_CTRL_OUTDIV5,
> &premul);
>    254				if (premul &
> VC3_PLL1_CTRL_OUTDIV5_PLL1_MDIV_DOUBLER)
>    255					parent_rate *= 2;
>    256				return parent_rate;
>    257			}
>    258			mdiv = VC3_PLL1_M_DIV(prediv);
>    259		} else if (pfd->num == VC3_PFD2) {
>    260			/* The bypass_prediv is set, PLL fed from Ref_in
> directly. */
>    261			if (prediv & pfd->mdiv1_bitmsk) {
>    262				/* check doubler is set or not */
>  > 263				if (premul & VC3_PLL2_MDIV_DOUBLER)
>    264					parent_rate *= 2;
>    265				return parent_rate;
>    266			}
>    267
>    268			mdiv = VC3_PLL2_M_DIV(prediv);
>    269		} else {
>    270			/* The bypass_prediv is set, PLL fed from Ref_in
> directly. */
>    271			if (prediv & pfd->mdiv1_bitmsk)
>    272				return parent_rate;
>    273
>    274			mdiv = VC3_PLL3_M_DIV(prediv);
>    275		}
>    276
>    277		if (prediv & pfd->mdiv2_bitmsk)
>    278			rate = parent_rate / 2;
>    279		else
>    280			rate = parent_rate / mdiv;
>    281
>    282		return rate;
>    283	}
>    284
> 
> --
> 0-DAY CI Kernel Test Service
> https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.com
> %2Fintel%2Flkp-
> tests&data=05%7C01%7Cbiju.das.jz%40bp.renesas.com%7C58183605a92243fe44db08db
> 34a63aba%7C53d82571da1947e49cb4625a166a4a2a%7C0%7C0%7C638161660780169608%7CU
> nknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJ
> XVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=YKqKrtq1gai%2FVmXX36nxTuU4kWNIMoWXr0Q%2Flc
> YIaZE%3D&reserved=0

^ permalink raw reply	[flat|nested] 2+ messages in thread

end of thread, other threads:[~2023-04-04  6:12 UTC | newest]

Thread overview: 2+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
     [not found] <20230403103257.328954-3-biju.das.jz@bp.renesas.com>
2023-04-04  0:47 ` [PATCH v3 2/3] drivers: clk: Add support for versa3 clock driver kernel test robot
2023-04-04  6:12   ` Biju Das

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