[ardb:x86-efi-peheader-backport-for-v5.15 29/77] arch/x86/boot/compressed/pgtable_64.c:134:3: error: use of undeclared identifier '__pgtable_l5_enabled'

[ardb:x86-efi-peheader-backport-for-v5.15 29/77] arch/x86/boot/compressed/pgtable_64.c:134:3: error: use of undeclared identifier '__pgtable_l5_enabled'

[kernel test robot]

tree:   git://git.kernel.org/pub/scm/linux/kernel/git/ardb/linux.git x86-efi-peheader-backport-for-v5.15
head:   51ff9e27b53cd980cd3f4a8ec02b1b34d99091db
commit: 32a1efd2dd3eb5863ff81e49a3f78526747ef2af [29/77] x86/decompressor: Assign paging related global variables earlier
config: x86_64-allnoconfig (https://download.01.org/0day-ci/archive/20240401/202404010344.7OPWIxxT-lkp@intel.com/config)
compiler: clang version 17.0.6 (https://github.com/llvm/llvm-project 6009708b4367171ccdbf4b5905cb6a803753fe18)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240401/202404010344.7OPWIxxT-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202404010344.7OPWIxxT-lkp@intel.com/

All errors (new ones prefixed by >>):

>> arch/x86/boot/compressed/pgtable_64.c:134:3: error: use of undeclared identifier '__pgtable_l5_enabled'
     134 |                 __pgtable_l5_enabled = 1;
         |                 ^
   1 error generated.


vim +/__pgtable_l5_enabled +134 arch/x86/boot/compressed/pgtable_64.c

   107	
   108	struct paging_config paging_prepare(void *rmode)
   109	{
   110		struct paging_config paging_config = {};
   111	
   112		/* Initialize boot_params. Required for cmdline_find_option_bool(). */
   113		boot_params = rmode;
   114	
   115		/*
   116		 * Check if LA57 is desired and supported.
   117		 *
   118		 * There are several parts to the check:
   119		 *   - if the kernel supports 5-level paging: CONFIG_X86_5LEVEL=y
   120		 *   - if user asked to disable 5-level paging: no5lvl in cmdline
   121		 *   - if the machine supports 5-level paging:
   122		 *     + CPUID leaf 7 is supported
   123		 *     + the leaf has the feature bit set
   124		 *
   125		 * That's substitute for boot_cpu_has() in early boot code.
   126		 */
   127		if (IS_ENABLED(CONFIG_X86_5LEVEL) &&
   128				!cmdline_find_option_bool("no5lvl") &&
   129				native_cpuid_eax(0) >= 7 &&
   130				(native_cpuid_ecx(7) & (1 << (X86_FEATURE_LA57 & 31)))) {
   131			paging_config.l5_required = 1;
   132	
   133			/* Initialize variables for 5-level paging */
 > 134			__pgtable_l5_enabled = 1;
   135			pgdir_shift = 48;
   136			ptrs_per_p4d = 512;
   137		}
   138	
   139		paging_config.trampoline_start = find_trampoline_placement();
   140	
   141		trampoline_32bit = (unsigned long *)paging_config.trampoline_start;
   142	
   143		/* Preserve trampoline memory */
   144		memcpy(trampoline_save, trampoline_32bit, TRAMPOLINE_32BIT_SIZE);
   145	
   146		/* Clear trampoline memory first */
   147		memset(trampoline_32bit, 0, TRAMPOLINE_32BIT_SIZE);
   148	
   149		/* Copy trampoline code in place */
   150		memcpy(trampoline_32bit + TRAMPOLINE_32BIT_CODE_OFFSET / sizeof(unsigned long),
   151				&trampoline_32bit_src, TRAMPOLINE_32BIT_CODE_SIZE);
   152	
   153		/*
   154		 * The code below prepares page table in trampoline memory.
   155		 *
   156		 * The new page table will be used by trampoline code for switching
   157		 * from 4- to 5-level paging or vice versa.
   158		 *
   159		 * If switching is not required, the page table is unused: trampoline
   160		 * code wouldn't touch CR3.
   161		 */
   162	
   163		/*
   164		 * We are not going to use the page table in trampoline memory if we
   165		 * are already in the desired paging mode.
   166		 */
   167		if (paging_config.l5_required == !!(native_read_cr4() & X86_CR4_LA57))
   168			goto out;
   169	
   170		if (paging_config.l5_required) {
   171			/*
   172			 * For 4- to 5-level paging transition, set up current CR3 as
   173			 * the first and the only entry in a new top-level page table.
   174			 */
   175			trampoline_32bit[TRAMPOLINE_32BIT_PGTABLE_OFFSET] = __native_read_cr3() | _PAGE_TABLE_NOENC;
   176		} else {
   177			unsigned long src;
   178	
   179			/*
   180			 * For 5- to 4-level paging transition, copy page table pointed
   181			 * by first entry in the current top-level page table as our
   182			 * new top-level page table.
   183			 *
   184			 * We cannot just point to the page table from trampoline as it
   185			 * may be above 4G.
   186			 */
   187			src = *(unsigned long *)__native_read_cr3() & PAGE_MASK;
   188			memcpy(trampoline_32bit + TRAMPOLINE_32BIT_PGTABLE_OFFSET / sizeof(unsigned long),
   189			       (void *)src, PAGE_SIZE);
   190		}
   191	
   192	out:
   193		return paging_config;
   194	}
   195	

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