Re: [PATCH 1/1] cxl/mem: Fix no cxl_nvd during pmem region auto-assembing

Re: [PATCH 1/1] cxl/mem: Fix no cxl_nvd during pmem region auto-assembing

[kernel test robot]

Hi Li,

kernel test robot noticed the following build warnings:

[auto build test WARNING on cxl/next]
[also build test WARNING on linus/master v6.10-rc1 next-20240531]
[cannot apply to cxl/pending]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Li-Ming/cxl-mem-Fix-no-cxl_nvd-during-pmem-region-auto-assembing/20240531-150446
base:   https://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl.git next
patch link:    https://lore.kernel.org/r/20240531070229.1596811-1-ming4.li%40intel.com
patch subject: [PATCH 1/1] cxl/mem: Fix no cxl_nvd during pmem region auto-assembing
config: i386-buildonly-randconfig-001-20240531 (https://download.01.org/0day-ci/archive/20240531/202405312008.SFZRRSYU-lkp@intel.com/config)
compiler: clang version 18.1.5 (https://github.com/llvm/llvm-project 617a15a9eac96088ae5e9134248d8236e34b91b1)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240531/202405312008.SFZRRSYU-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202405312008.SFZRRSYU-lkp@intel.com/

All warnings (new ones prefixed by >>):

>> drivers/cxl/core/pmem.c:71: warning: expecting prototype for cxl_nvdimm_bridge(). Prototype was for cxl_find_nvdimm_bridge() instead


vim +71 drivers/cxl/core/pmem.c

2e52b6256b9af2 Dan Williams 2021-09-14  64  
0417bd9707cb07 Li Ming      2024-05-31  65  /**
0417bd9707cb07 Li Ming      2024-05-31  66   * cxl_nvdimm_bridge() - find a bridge device relative to a port
0417bd9707cb07 Li Ming      2024-05-31  67   * @port: any descendant port of an nvdimm-bridge associated
0417bd9707cb07 Li Ming      2024-05-31  68   *        root-cxl-port
0417bd9707cb07 Li Ming      2024-05-31  69   */
0417bd9707cb07 Li Ming      2024-05-31  70  struct cxl_nvdimm_bridge *cxl_find_nvdimm_bridge(struct cxl_port *port)
2e52b6256b9af2 Dan Williams 2021-09-14 @71  {
0417bd9707cb07 Li Ming      2024-05-31  72  	struct cxl_root *cxl_root __free(put_cxl_root) = find_cxl_root(port);
2e52b6256b9af2 Dan Williams 2021-09-14  73  	struct device *dev;
2e52b6256b9af2 Dan Williams 2021-09-14  74  
44cd71ef7bacdf Dave Jiang   2024-01-05  75  	if (!cxl_root)
a46cfc0f011ce7 Dan Williams 2022-01-31  76  		return NULL;
a46cfc0f011ce7 Dan Williams 2022-01-31  77  
66f11890d35a60 Dave Jiang   2024-01-05  78  	dev = device_find_child(&cxl_root->port.dev, NULL, match_nvdimm_bridge);
a46cfc0f011ce7 Dan Williams 2022-01-31  79  
2e52b6256b9af2 Dan Williams 2021-09-14  80  	if (!dev)
2e52b6256b9af2 Dan Williams 2021-09-14  81  		return NULL;
a46cfc0f011ce7 Dan Williams 2022-01-31  82  
2e52b6256b9af2 Dan Williams 2021-09-14  83  	return to_cxl_nvdimm_bridge(dev);
2e52b6256b9af2 Dan Williams 2021-09-14  84  }
affec782742e08 Dan Williams 2021-11-12  85  EXPORT_SYMBOL_NS_GPL(cxl_find_nvdimm_bridge, CXL);
2e52b6256b9af2 Dan Williams 2021-09-14  86  

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